JP4401500B2 - 静電放電における寄生バイポーラ効果を低減する半導体装置および方法 - Google Patents

静電放電における寄生バイポーラ効果を低減する半導体装置および方法 Download PDF

Info

Publication number
JP4401500B2
JP4401500B2 JP33849799A JP33849799A JP4401500B2 JP 4401500 B2 JP4401500 B2 JP 4401500B2 JP 33849799 A JP33849799 A JP 33849799A JP 33849799 A JP33849799 A JP 33849799A JP 4401500 B2 JP4401500 B2 JP 4401500B2
Authority
JP
Japan
Prior art keywords
current
coupled
transistor
voltage
esd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33849799A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000174133A (ja
Inventor
ジェレミー・シー・スミス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2000174133A publication Critical patent/JP2000174133A/ja
Application granted granted Critical
Publication of JP4401500B2 publication Critical patent/JP4401500B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0277Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP33849799A 1998-11-30 1999-11-29 静電放電における寄生バイポーラ効果を低減する半導体装置および方法 Expired - Fee Related JP4401500B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/201,392 US6329692B1 (en) 1998-11-30 1998-11-30 Circuit and method for reducing parasitic bipolar effects during eletrostatic discharges
US201392 1998-11-30

Publications (2)

Publication Number Publication Date
JP2000174133A JP2000174133A (ja) 2000-06-23
JP4401500B2 true JP4401500B2 (ja) 2010-01-20

Family

ID=22745641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33849799A Expired - Fee Related JP4401500B2 (ja) 1998-11-30 1999-11-29 静電放電における寄生バイポーラ効果を低減する半導体装置および方法

Country Status (5)

Country Link
US (3) US6329692B1 (ko)
JP (1) JP4401500B2 (ko)
KR (1) KR100717973B1 (ko)
CN (1) CN1167132C (ko)
TW (1) TW454306B (ko)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809348B1 (en) * 1999-10-08 2004-10-26 Denso Corporation Semiconductor device and method for manufacturing the same
JP3217336B2 (ja) * 1999-11-18 2001-10-09 株式会社 沖マイクロデザイン 半導体装置
JP2002083931A (ja) * 2000-09-08 2002-03-22 Nec Corp 半導体集積回路装置
JP2002305254A (ja) * 2001-04-05 2002-10-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6650103B2 (en) * 2001-05-31 2003-11-18 Analog Devices, Inc. Magnetic snapback sensor circuit and electrostatic discharge circuit using same
JP2003031669A (ja) * 2001-07-13 2003-01-31 Ricoh Co Ltd 半導体装置
DE10201056B4 (de) * 2002-01-14 2007-06-21 Infineon Technologies Ag Halbleitereinrichtung mit einem bipolaren Schutztransistor
US7042689B2 (en) * 2003-01-21 2006-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage tolerant ESD design for analog and RF applications in deep submicron CMOS technologies
US7075763B2 (en) * 2002-10-31 2006-07-11 Micron Technology, Inc. Methods, circuits, and applications using a resistor and a Schottky diode
US6900970B2 (en) * 2003-01-22 2005-05-31 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US6879476B2 (en) * 2003-01-22 2005-04-12 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US6844597B2 (en) * 2003-02-10 2005-01-18 Freescale Semiconductor, Inc. Low voltage NMOS-based electrostatic discharge clamp
US8000067B1 (en) 2003-05-15 2011-08-16 Marvell International Ltd. Method and apparatus for improving supply noise rejection
US7196887B2 (en) * 2003-05-28 2007-03-27 Texas Instruments Incorporated PMOS electrostatic discharge (ESD) protection device
JP2005093696A (ja) * 2003-09-17 2005-04-07 Matsushita Electric Ind Co Ltd 横型mosトランジスタ
US6996786B2 (en) * 2003-09-30 2006-02-07 International Business Machines Corporation Latch-up analysis and parameter modification
US7089520B2 (en) * 2003-11-19 2006-08-08 International Business Machines Corporation Methodology for placement based on circuit function and latchup sensitivity
US7819079B2 (en) 2004-12-22 2010-10-26 Applied Materials, Inc. Cartesian cluster tool configuration for lithography type processes
US7798764B2 (en) 2005-12-22 2010-09-21 Applied Materials, Inc. Substrate processing sequence in a cartesian robot cluster tool
US7371022B2 (en) 2004-12-22 2008-05-13 Sokudo Co., Ltd. Developer endpoint detection in a track lithography system
US7651306B2 (en) 2004-12-22 2010-01-26 Applied Materials, Inc. Cartesian robot cluster tool architecture
TW200739872A (en) * 2006-04-04 2007-10-16 Univ Nat Chiao Tung Power line electrostatic discharge protection circuit featuring triple voltage tolerance
TW200816878A (en) * 2006-09-27 2008-04-01 Silicon Motion Inc Electrostatic discharge (ESD) protection device
US7672101B2 (en) 2007-09-10 2010-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection circuit and method
CN101533830B (zh) * 2008-03-11 2012-05-09 义隆电子股份有限公司 高压垫的静电放电保护装置
WO2010038101A1 (en) * 2008-10-03 2010-04-08 Freescale Semiconductor, Inc. Semiconductor device and electronic device
US8693149B2 (en) * 2009-05-20 2014-04-08 Semiconductor Components Industries, Llc. Transient suppression device and method therefor
US8193585B2 (en) * 2009-10-29 2012-06-05 Freescale Semiconductor, Inc. Semiconductor device with increased snapback voltage
US20110102046A1 (en) * 2009-10-31 2011-05-05 Pankaj Kumar Interfacing between differing voltage level requirements in an integrated circuit system
US8344472B2 (en) 2010-03-30 2013-01-01 Freescale Semiconductor, Inc. Semiconductor device and method
US8338872B2 (en) 2010-03-30 2012-12-25 Freescale Semiconductor, Inc. Electronic device with capcitively coupled floating buried layer
US8927391B2 (en) * 2011-05-27 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package process for applying molding compound
CN102332403A (zh) * 2011-09-20 2012-01-25 中国科学院微电子研究所 一种半导体结构及其制造方法
US10553633B2 (en) * 2014-05-30 2020-02-04 Klaus Y.J. Hsu Phototransistor with body-strapped base
TWI521824B (zh) * 2014-08-08 2016-02-11 朋程科技股份有限公司 靜電放電防護電路及具有此電路的電壓調節器晶片
US10332871B2 (en) * 2016-03-18 2019-06-25 Intel IP Corporation Area-efficient and robust electrostatic discharge circuit
US10840907B1 (en) 2019-11-19 2020-11-17 Honeywell International Inc. Source-coupled logic with reference controlled inputs
US11329481B2 (en) 2020-05-18 2022-05-10 Littelfuse, Inc. Current limiting circuit arrangement

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019888A (en) 1987-07-23 1991-05-28 Texas Instruments Incorporated Circuit to improve electrostatic discharge protection
US5157573A (en) 1989-05-12 1992-10-20 Western Digital Corporation ESD protection circuit with segmented buffer transistor
US5465189A (en) 1990-03-05 1995-11-07 Texas Instruments Incorporated Low voltage triggering semiconductor controlled rectifiers
US5021853A (en) 1990-04-27 1991-06-04 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
US5153529A (en) * 1991-08-30 1992-10-06 Motorola, Inc. Rail-to-rail input stage of an operational amplifier
US5225702A (en) 1991-12-05 1993-07-06 Texas Instruments Incorporated Silicon controlled rectifier structure for electrostatic discharge protection
US5440162A (en) 1994-07-26 1995-08-08 Rockwell International Corporation ESD protection for submicron CMOS circuits
US5528193A (en) * 1994-11-21 1996-06-18 National Semiconductor Corporation Circuit for generating accurate voltage levels below substrate voltage
US5534792A (en) * 1995-02-15 1996-07-09 Burr-Brown Corporation Low capacitance electronically controlled active bus terminator circuit and method
US5798658A (en) * 1995-06-15 1998-08-25 Werking; Paul M. Source-coupled logic with reference controlled inputs
KR100223923B1 (ko) * 1996-11-19 1999-10-15 구본준 정전기 방지장치
US5903419A (en) 1997-09-29 1999-05-11 Motorola, Inc. Circuit for electrostatic discharge (ESD) protection
US6204715B1 (en) * 1999-02-26 2001-03-20 General Motors Corporation Signal amplifying circuit

Also Published As

Publication number Publication date
KR20000035771A (ko) 2000-06-26
JP2000174133A (ja) 2000-06-23
US6284616B1 (en) 2001-09-04
US6373104B1 (en) 2002-04-16
US6329692B1 (en) 2001-12-11
KR100717973B1 (ko) 2007-05-16
TW454306B (en) 2001-09-11
CN1167132C (zh) 2004-09-15
CN1256516A (zh) 2000-06-14

Similar Documents

Publication Publication Date Title
JP4401500B2 (ja) 静電放電における寄生バイポーラ効果を低減する半導体装置および方法
US7236339B2 (en) Electrostatic discharge circuit and method therefor
US7196887B2 (en) PMOS electrostatic discharge (ESD) protection device
US6236087B1 (en) SCR cell for electrical overstress protection of electronic circuits
US6479872B1 (en) Dynamic substrate-coupled electrostatic discharging protection circuit
US11315919B2 (en) Circuit for controlling a stacked snapback clamp
JP3992855B2 (ja) 静電気放電保護のための回路
US9029910B2 (en) Programmable SCR for ESD protection
US8703547B2 (en) Thyristor comprising a special doped region characterized by an LDD region and a halo implant
US6433979B1 (en) Electrostatic discharge protection device using semiconductor controlled rectifier
JP2008524857A (ja) 低電圧トリガ要素を有するデバイス
JPH06196634A (ja) 空乏制御型分離ステージ
US20040042143A1 (en) Electrostatic discharge protection circuit with active device
US7449751B2 (en) High voltage operating electrostatic discharge protection device
US6879476B2 (en) Electrostatic discharge circuit and method therefor
KR19980071441A (ko) 정전기 방전 보호용 회로
JPH07193195A (ja) Cmos集積回路装置
KR100504203B1 (ko) 반도체장치의 보호소자
KR100435807B1 (ko) 정전방전 보호 회로용 반도체 제어 정류기
JPH07263633A (ja) 半導体装置の対静電気放電保護装置
US20040120086A1 (en) Device for electrostatic discharge protection
JPH04226062A (ja) 半導体装置
WO2006113288A2 (en) Guardwall structures for esd protection

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20041217

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060117

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061124

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20081120

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090416

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090428

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090710

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091006

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091028

R150 Certificate of patent or registration of utility model

Ref document number: 4401500

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121106

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121106

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131106

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees