US20110102046A1 - Interfacing between differing voltage level requirements in an integrated circuit system - Google Patents
Interfacing between differing voltage level requirements in an integrated circuit system Download PDFInfo
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- US20110102046A1 US20110102046A1 US12/610,277 US61027709A US2011102046A1 US 20110102046 A1 US20110102046 A1 US 20110102046A1 US 61027709 A US61027709 A US 61027709A US 2011102046 A1 US2011102046 A1 US 2011102046A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- This disclosure relates generally to Input/Output (IO) circuits and, more particularly, to a method, an apparatus, and a system to generate a bias voltage to protect IO circuits during a failsafe operation and a tolerant operation.
- IO Input/Output
- An integrated circuit may include a constituent section that operates at a voltage different from another constituent section. Interfacing between constituent sections operating at different voltages may require a buffer circuit that may include active elements (e.g., Metal-Oxide-Semiconductor (MOS) transistors) operating at a voltage (e.g., 1.8 V) lower than a voltage across terminals thereof.
- active elements e.g., Metal-Oxide-Semiconductor (MOS) transistors
- FIG. 1 shows a schematic view of an output stage 100 of a buffer circuit.
- the output stage 100 may include a p-channel Metal-Oxide-Semiconductor (PMOS) transistor M 1 102 and an n-channel MOS (NMOS) transistor M 2 104 .
- the source (S) terminal of M 1 102 may be connected to a supply voltage V DDIO 106
- the source (S) terminal of M 2 104 may be connected to a supply voltage V SS 110 .
- the bulk (B) terminals of the transistors (M 1 102 , M 2 104 ) may be shorted with the source (S) terminals thereof to connect the bulk (B) terminals of the transistors (M 1 102 , M 2 104 ) also to V DDIO 106 and V SS 110 respectively.
- the drain (D) terminals of M 1 102 and M 2 104 may be connected to one another, as shown in FIG. 1 .
- An external voltage from an Input/Output (IO) pad 108 of an IC may be supplied to each of the drain (D) terminals of M 1 102 and M 2 104 .
- the gate (G) terminals of the transistors (M 1 102 , M 2 104 ) may be driven by control signals (CTRL 1 112 and CTRL 2 114 ) generated from a control circuit of the buffer circuit.
- the IO pad 108 voltage e.g., 3.465 V
- V DDIO 106 e.g., 1.8 V, 2.5 V
- the parasitic diode D 1 116 shown in FIG.
- FIG. 1 also shows the parasitic diode D 2 118 associated with Q 2 104 .
- a high value of the IO pad 108 voltage may, therefore, compromise the reliability of the buffer circuit.
- IO Input/Output
- a method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad.
- the method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
- the external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation.
- the supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- a bias voltage generating circuit includes a multiplexer block configured to receive a first bias voltage controllably generated from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an IO core device of an IC to be interfaced with an IO pad, and to receive a second bias voltage controllably generated from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element (s) of the IO core device to be interfaced with the IO pad.
- the multiplexer block is also configured to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation through a controllable utilization of a control signal generated by the IO core.
- the external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation.
- the supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- an Input/Output includes an IO core-end block to generate a control signal, a driver block to drive one or more external active circuit element(s), an IO pad interfaced with the driver block, and a bias voltage generating circuit.
- the IO core-end block includes one or more constituent active circuit element(s) having an upper tolerable limit of an operating voltage thereof.
- the bias voltage generating circuit is configured to receive a supply voltage, to receive an external voltage supplied through the IO pad, and to generate an output bias voltage within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block.
- the bias voltage generating circuit includes a multiplexer block configured to receive a first bias voltage controllably generated from the supply voltage to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block to be interfaced with the IO pad, and to receive a second bias voltage controllably generated from the external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block to be interfaced with the IO pad.
- the bias voltage generating circuit is also configured to derive the output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation through a controllable utilization of the control signal generated by the IO core-end block.
- the external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation.
- the supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- FIG. 1 shows a schematic view of an output stage of a buffer circuit.
- FIG. 2 is a schematic view of a multiplexer circuit, according to one or more embodiments.
- FIG. 3 is a schematic view of a transistor implementation of the multiplexer circuit of FIG. 2 , according to one or more embodiments.
- FIG. 4 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during a driver mode of operation, according to one or more embodiments.
- FIG. 5 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during a failsafe mode of operation, according to one or more embodiments.
- FIG. 6 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during a tolerant mode of operation, according to one or more embodiments.
- FIG. 7 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during the failsafe mode of operation, according to one or more embodiments.
- FIG. 8 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during the tolerant mode of operation, according to one or more embodiments.
- FIG. 9 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit of FIG. 2 during the driver mode of operation, according to one or more embodiments.
- FIG. 10 is a system view of an Input/Output (IO) circuit, according to one or more embodiments.
- IO Input/Output
- FIG. 11 is a process flow detailing the operations involved in a method of generating an output bias voltage, according to one or more embodiments.
- Example embodiments may be used to generate a bias voltage to protect Input/Output (IO) circuits during a failsafe operation and a tolerant operation.
- IO Input/Output
- FIG. 2 shows a multiplexer circuit 200 , according to one or more embodiments.
- the multiplexer circuit 200 includes a multiplexer block 202 that may receive a first bias voltage 206 and a second bias voltage 208 as the inputs.
- the first bias voltage 206 may be controllably generated from a supply voltage (not shown in FIG. 2 )
- the second bias voltage 208 may be controllably generated from an external voltage supplied through an Input/Output (IO) pad (not shown in FIG. 2 ).
- IO Input/Output
- the first bias voltage 206 and the second bias voltage 208 may be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) (e.g., Metal-Oxide-Semiconductor (MOS) transistor) of an IO core device of an integrated circuit (IC) to be interfaced with the IO pad.
- MOS Metal-Oxide-Semiconductor
- the output of the multiplexer block 202 may be derived from the first bias voltage 206 during a driver mode of operation, where the external voltage supplied through the IO pad may vary from zero to a value of the supply voltage, or from the second bias voltage 208 during a failsafe mode of operation and a tolerant mode of operation.
- the supply voltage may be zero during the failsafe mode of operation, and the external voltage supplied through the IO pad may increase to a value above the supply voltage during the tolerant mode of operation.
- the output of the multiplexer block 210 may be based on a “high” or “low” state of a control signal 204 (e.g., Output Enable (OE)).
- the “high” state of the control signal 204 which is a logic “1,” may indicate the presence of the supply voltage.
- the “low” state of the control signal 204 which is a logic “0,” may indicate the absence of the supply voltage or the tolerant case, where the external voltage supplied through the IO pad may increase to a value above the supply voltage. Therefore, during the “low” state of the control signal 204 , the supply voltage may or may not be present.
- the control signal 204 may be generated by the IO core.
- control signal 204 may be utilized in a controllable manner to derive the output bias voltage 210 . Therefore, the output bias voltage 210 may be derived from the first bias voltage 206 during the driver mode of operation when the state of the control signal 204 is “high,” or the second bias voltage 208 during the failsafe mode of operation and the tolerant mode of operation when the state of the control signal 204 is “low.”
- the first bias voltage 206 may be controllably generated as a fraction of the supply voltage.
- the second bias voltage 208 may be controllably generated as the external voltage supplied through the IO pad reduced by a threshold voltage of one or more active element(s) (e.g., Metal-Oxide-Semiconductor (MOS) transistors).
- MOS Metal-Oxide-Semiconductor
- FIG. 3 shows a transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 , according to one or more embodiments.
- the source (S) and drain (S) terminals of a MOS transistor are interchangeable and, therefore, coupling a voltage to the source (S) terminal and outputting another voltage from the drain (D) terminal is equivalent to coupling the voltage to the drain (D) terminal and outputting another voltage from the source (S) terminal.
- a drain-drain (D-D) path may also be equivalent to a source-drain (S-D) path.
- the multiplexer block 202 includes a first MOS transistor Q 4 322 configured to receive the first bias voltage 206 at the source (S) terminal thereof, and a pair of MOS transistors (Q 3 320 and Q 5 324 ) configured to receive a controllable level shifted version of the control signal 204 (control signal LS 302 ) at gate (G) terminals thereof.
- control signal LS 302 may be at a fraction of the supply voltage, V DDIO (not shown in FIG. 3 ), during each of the driver mode of operation and the tolerant mode of operation.
- control signal LS 302 may be at a value higher (e.g., 0.6 V DDIO ) than the value of control signal LS 302 (e.g., 0.1 V DDIO ) during the tolerant mode of operation. In one or more embodiments, control signal LS 302 may be zero when the supply voltage (V DDIO ) is zero during the failsafe mode of operation.
- control signal LS 302 may switch between 0.6 V DDIO during the driver mode of operation and 0.1 V DDIO during the tolerant mode of operation, depending on whether the control signal 204 represents a logic “1” or logic “0.” However, as shown in FIG. 2 , logic “0” may also represent the failsafe mode of operation, where control signal LS 302 is zero. Therefore, the two states of the control signal 204 may be better described as a logic “high” (during the driver mode of operation) and a logic “low” (during the tolerant mode of operation and the failsafe mode of operation).
- the drain (D) terminal of Q 3 320 may be coupled to the drain (D) terminal of Q 5 324 .
- the source (S) terminals of Q 3 320 and Q 5 324 may be coupled to the gate (G) terminal and the drain (D) terminal of Q 4 322 respectively.
- Q 5 324 may be configured to receive the second bias voltage 208 at the drain (D) terminal thereof.
- the drain (D) terminals of Q 3 320 and Q 5 324 may be coupled to one another.
- Q 3 320 , Q 4 322 and Q 5 324 may be p-channel MOS (PMOS) transistors.
- the output of the multiplexer block 202 , the output bias voltage 210 may be taken at the drain-source (D-S) path between Q 4 322 and Q 5 324 (node C 338 ).
- control signal 204 and the first bias voltage 206 may be applied at the gate (G) terminals of MOS transistors Q 2 318 and Q 1 316 respectively.
- the source (S) terminal of Q 1 316 may be coupled to the drain (D) terminal of Q 2 318
- the drain (D) terminal of Q 1 316 may be coupled to the gate (G) terminal of Q 4 322 .
- the bulk (B) terminals of Q 1 316 and Q 2 318 , and the source (S) terminal of Q 2 318 may be held at a second supply voltage 314 (V SS ).
- Q 1 316 and Q 2 318 may be pass transistors (shown in FIG.
- the first bias voltage 206 may be a fraction of the supply voltage V DDIO (e.g., 0.55 V DDIO ).
- a pair of MOS transistors may be provided in the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 to reduce the external voltage supplied through the IO pad (IO pad 304 voltage) by the threshold voltages of Q 6 326 and Q 7 328 . Therefore, at node B 336 , the second bias voltage 208 may be expressed as Example Equation 1.
- V SB IO PAD ⁇ 2 V tn , (1)
- FIG. 3 shows Q 6 326 and Q 7 328 as n-channel MOS (NMOS) transistors, where the source (S) terminal of Q 6 326 may be coupled to the drain (D) terminal of Q 7 328 .
- IO pad 304 voltage may be applied at the source (S) terminal and the gate (G) terminal of Q 7 328 .
- the gate (G) terminal of Q 6 326 may be coupled to the source (S) terminal thereof.
- the bulk (B) terminals of Q 6 326 and Q 7 328 may be held at the second supply voltage 314 (V SS ).
- V SS second supply voltage 314
- active elements e.g., MOS transistors Q 6 326 and Q 7 328
- the number of active elements may vary, and that such a variation is within the scope of the exemplary embodiments.
- the second bias voltage 208 may, thus, be within an upper tolerable limit of one or more constituent active circuit element(s) (e.g., MOS transistors) of an IO core device of an IC to be interfaced with the IO pad.
- a MOS transistor Q 9 332 in order to generate an output bias voltage 210 in and around the upper tolerance limit of the aforementioned constituent active circuit elements of the IO core device, a MOS transistor Q 9 332 , whose gate (G) terminal and the drain (D) terminal are configured to receive controllable input voltages (V 3 306 and V 1 308 respectively), may be provided.
- the source (S) terminal of Q 9 332 shown in FIG.
- V 3 306 and V 1 308 may be controlled to be fractions of the supply voltage V DDIO .
- V 3 306 may be equal to 0.3 V DDIO and V 1 308 may be equal to 0.1 V DDIO .
- Q 9 332 when supply voltage V DDIO is zero during the failsafe mode of operation, Q 9 332 may pull maximum current to maximize the diode drops across Q 6 326 and Q 7 328 . In one or more embodiments, when the supply voltage is present during the driver mode of operation and the tolerant mode of operation, Q 9 332 may pull a current that is less compared to the current during the failsafe mode of operation. In one or more embodiments, the diode drops across Q 6 326 and Q 7 328 may, therefore, decrease.
- the bulk (B) terminals of Q 3 320 , Q 4 322 , Q 5 324 , and Q 9 332 may be coupled to the output of a floating well (FW) circuit to avoid the forward biasing of parasitic diodes associated with the aforementioned transistors.
- FW floating well
- the first bias voltage 206 may be appropriately scaled to a fraction of V DDIO (e.g., 0.55 V DDIO ).
- control signal LS 302 may also be adjusted appropriately to a fraction of V DDIO .
- the logic “high” of the control signal 204 may indicate a control signal LS 302 value of 0.6 V DDIO .
- pass transistors Q 1 316 and Q 2 318 may be turned ON, thereby enabling node A 334 to be discharged.
- the discharging of node A 334 may switch Q 4 322 oN, and the adjusted “high” level of control signal LS 302 (e.g., 0.6 V DDIO ) may keep Q 3 320 and Q 5 324 switched OFF.
- any perturbation at the node B 336 may not affect the output at node C 338 , i.e., the output bias voltage 210 .
- the output bias voltage 210 may faithfully track the first bias voltage 206 , and may be equal to the first bias voltage 206 .
- the first bias voltage 206 and control signal LS 302 may also be zero. Therefore, in one or more embodiments, node A 334 may not be able to discharge through the Q 1 316 -Q 2 318 path.
- Q 6 326 and Q 7 328 may be turned ON, thereby enabling the second bias voltage 208 to track the IO pad 304 voltage as per example Equation 1.
- the logic “low” of control signal LS 302 may cause Q 3 320 and Q 5 324 to be turned ON, which may charge node A 334 .
- the charging of node A 334 may turn Q 4 322 OFF.
- the output bias voltage 210 may track the second bias voltage 208 .
- a decoupling capacitor Q 8 330 may be used at node C 338 to mitigate the effects of capacitive noise on the output bias voltage 210 , which may be coupled to the gate (G) terminal of a MOS transistor of a driver of the IO pad, during switching of the IO pad 304 voltage.
- Q 8 330 may be a NMOS capacitor, where the output bias voltage 210 is coupled to the gate (G) terminal thereof.
- the gate (G), bulk (B), and drain (D) terminals of Q 8 330 may all be held at the second supply voltage 310 (V SS ) level.
- control signal LS 302 may switch to a fraction of the supply voltage V DDIO that is lower than the value thereof during the driver mode of operation. For example, control signal LS 302 may switch to 0.1 V DDIO , which still may represent the logic “low.”
- control signal LS 302 may switch to 0.1 V DDIO , which still may represent the logic “low.”
- Q 6 326 and Q 7 328 may be OFF, along with Q 2 318 . Therefore, in one or more embodiments, node A 334 may not have a path to discharge, except for through Q 4 322 . In one or more embodiments, the discharging of node A 334 may cause the output bias voltage 210 to settle close to the first bias voltage 206 of Q 4 322 through leakage current thereof.
- the tolerant mode of operation may be analogous to the driver mode of operation when the IO pad 304 voltage is low.
- the two cases have differing control signal LS 302 values (0.6 V DDIO and 0.1 V DDIO respectively) to differentiate between the tolerant mode of operation and the driver mode of operation, when the IO pad 304 voltage increases to a value above the supply voltage V DDIO .
- Q 6 326 and Q 7 328 may be turned ON, thereby enabling the second bias voltage 208 to track the IO pad 304 voltage as per example Equation 1.
- the logic “low” of control signal LS 302 may cause Q 3 320 and Q 5 324 to be turned ON, which may charge node A 334 .
- the charging of node A 334 may turn Q 4 322 OFF.
- Q 5 324 may be ON, the output bias voltage 210 may track the second bias voltage 208 .
- the supply voltage V DDIO may be 2.75 V (2.5V+10% tolerance)
- IO pad 304 voltage may be 3.465 V (3.3 V+5% tolerance)
- the operating voltage of one or more constituent active circuit element(s) of the IO core device may be 1.98 V (1.8 V+10% tolerance).
- the first bias voltage 206 , the second bias voltage 208 , and the output bias voltage 210 may all be within 1.98 V. Additionally, the first bias voltage 206 and the second bias voltage 208 being within 1.98 V may facilitate reliable operation of constituent MOS transistors of the multiplexer circuit 200 .
- FIG. 4 shows the DC characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the driver mode of operation, according to one or more embodiments.
- the x-axis 402 may represent IO pad 304 voltage and the y-axis 404 may represent a voltage variable (V).
- the output bias voltage 210 may be equal to the first bias voltage 206 during all values of IO pad 304 voltage.
- control signal LS 302 and the first bias voltage 206 may be a fraction of the supply voltage V DDIO (e.g., 0.6 V DDIO ) during the driver mode of operation (e.g., 0.6 V DDIO and 0.55 V DDIO respectively).
- FIG. 5 shows the DC characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the failsafe mode of operation, according to one or more embodiments.
- the x-axis 502 may refer to the IO pad 304 voltage and the y-axis 504 may be a voltage variable (V).
- the supply voltage V DDIO may be zero during the failsafe mode of operation.
- the output bias voltage 210 may track the second bias voltage 208 , as shown in FIG. 5 . In other words, the output bias voltage 210 may increase with the increase in IO pad 304 voltage.
- FIG. 6 shows the DC characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the tolerant mode of operation, according to one or more embodiments.
- the x-axis 602 may refer to the IO pad 304 voltage and the y-axis 604 may refer to a voltage variable (V).
- the supply voltage V DDIO may be present during the tolerant mode of operation, and control signal LS 302 may be at a logic “low” (e.g., 0.1 V DDIO ).
- the output bias voltage 210 may settle close to the first bias voltage 206 when the IO pad 304 voltage is low.
- Q 6 326 and Q 7 328 may turn ON, and the output bias voltage 210 may start tracking the second bias voltage 208 .
- FIG. 7 shows the transient characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the failsafe mode of operation, according to one or more embodiments.
- the x-axis 702 may refer to time (t) and the y-axis 704 may refer to a voltage variable (V).
- V voltage variable
- the output bias voltage 210 may switch from a low value (i.e., threshold voltage of Q 4 322 ) to approximately the second bias voltage 208 and the second bias voltage 208 to the low value, as shown in FIG. 7 .
- the output bias voltage 210 may be clamped to the threshold voltage of Q 4 322 as there is no discharge path for node A 334 otherwise.
- FIG. 8 shows the transient characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the tolerant mode of operation, according to one or more embodiments.
- the x-axis 802 may refer to time (t) and the y-axis 804 may refer to a voltage variable (V).
- V voltage variable
- the output bias voltage 210 may switch between two voltages, i.e., one close to the first bias voltage 206 and the other close to the second bias voltage 208 , and vice versa.
- FIG. 9 shows the transient characteristics of the transistor implementation 300 of the multiplexer circuit 200 of FIG. 2 during the driver mode of operation, according to one or more embodiments.
- the x-axis 902 may refer to time (t) and the y-axis 904 may refer to a voltage variable (V).
- the IO pad 304 voltage may vary from 0 to the value of the supply voltage V DDIO during the driver mode of operation.
- the output bias voltage 210 may be constant at the value of the first bias voltage 206 (e.g., 0.55 V DDIO ).
- control signal LS 302 may also be a fraction of the supply voltage V DDIO (e.g., 0.6 V DDIO ).
- FIG. 10 shows a system view of an IO circuit 1000 , according to one or more embodiments.
- the IO circuit 1000 may include a driver block 1006 to drive external active circuit elements (e.g., MOS transistors) that may be interfaced with the IO core-end block 1002 through the multiplexer circuit 200 of FIG. 2 .
- the IO core-end block 1002 may include one or more constituent active circuit element(s) (e.g., MOS transistors) that have an upper tolerable limit of an operating voltage thereof (e.g., 1.98 V, 1.8 V+10% tolerance).
- the control signal 204 may be generated by the IO core-end block 1002 .
- the multiplexer circuit 200 may receive the supply voltage (V DDIO ) 1004 and the external voltage supplied through an IO pad (shown as PAD 1008 ), IO pad 304 voltage, as shown in FIG. 10 .
- PAD 1008 may be interfaced with the driver block 1006 .
- the multiplexer circuit 200 may generate an output bias voltage 210 that may be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block 1002 .
- FIG. 11 is a process flow diagram detailing the operations involved in a method of generating the output bias voltage 210 , according to one or more embodiments.
- operation 1102 may involve controllably generating a first bias voltage 206 from a supply voltage V DDIO 1004 to be within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block 1002 .
- the IO core-end block 1002 may be an IO device of an integrated circuit (IC) to be interfaced with an IO pad (PAD 1008 ).
- operation 1104 may involve controllably generating a second bias voltage 208 from the external voltage supplied through the IO pad (PAD 1008 ), IO pad 304 voltage, to be within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block 1002 .
- operation 1106 may involve controllably utilizing the control signal 204 generated by the IO core-end block 1002 to derive an output bias voltage 210 from the first bias voltage 206 during a driver mode of operation or the second bias voltage 208 during a failsafe mode of operation and a tolerant mode of operation.
- the external voltage supplied through the IO pad (PAD 1008 ), IO pad 304 voltage may vary from zero to a value of the supply voltage V DDIO 1004 during the driver mode of operation.
- the supply voltage V DDIO ) 1004 may be zero during the failsafe mode of operation, and the external voltage supplied through the IO pad (PAD 1008 ), IO pad 304 voltage, may increase to a value above the supply voltage V DDIO 1004 during the tolerant mode of operation.
- the various devices and modules described herein may be enabled and operated using hardware circuitry (e.g., CMOS based logic circuitry), firmware, software or any combination of hardware, firmware, and software (e.g., embodied in a machine readable medium).
- hardware circuitry e.g., CMOS based logic circuitry
- firmware e.g., software or any combination of hardware, firmware, and software (e.g., embodied in a machine readable medium).
- the various electrical structure and methods may be embodied using transistors, logic gates, and electrical circuits (e.g., application specific integrated (ASIC) circuitry and/or in Digital Signal Processor (DSP) circuitry).
- ASIC application specific integrated
- DSP Digital Signal Processor
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Abstract
A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
Description
- This disclosure relates generally to Input/Output (IO) circuits and, more particularly, to a method, an apparatus, and a system to generate a bias voltage to protect IO circuits during a failsafe operation and a tolerant operation.
- An integrated circuit (IC) may include a constituent section that operates at a voltage different from another constituent section. Interfacing between constituent sections operating at different voltages may require a buffer circuit that may include active elements (e.g., Metal-Oxide-Semiconductor (MOS) transistors) operating at a voltage (e.g., 1.8 V) lower than a voltage across terminals thereof.
-
FIG. 1 shows a schematic view of anoutput stage 100 of a buffer circuit. Theoutput stage 100 may include a p-channel Metal-Oxide-Semiconductor (PMOS)transistor M 1 102 and an n-channel MOS (NMOS)transistor M 2 104. The source (S) terminal ofM 1 102 may be connected to asupply voltage V DDIO 106, and the source (S) terminal ofM 2 104 may be connected to asupply voltage V SS 110. The bulk (B) terminals of the transistors (M 1 102, M2 104) may be shorted with the source (S) terminals thereof to connect the bulk (B) terminals of the transistors (M 1 102, M2 104) also toV DDIO 106 andV SS 110 respectively. The drain (D) terminals ofM 1 102 andM 2 104 may be connected to one another, as shown inFIG. 1 . - An external voltage from an Input/Output (IO)
pad 108 of an IC may be supplied to each of the drain (D) terminals ofM 1 102 andM 2 104. The gate (G) terminals of the transistors (M 1 102, M2 104) may be driven by control signals (CTRL1 112 and CTRL2 114) generated from a control circuit of the buffer circuit. When theIO pad 108 voltage (e.g., 3.465 V) is higher than the supply voltage, VDDIO 106 (e.g., 1.8 V, 2.5 V), theparasitic diode D 1 116, shown inFIG. 1 as being associated withM 1 102, may be turned ON, leading to there being a direct path between theIO pad 108 voltage and thesupply voltage V DDIO 106. The turning ON ofD 1 116 may lead to the conducting of a large current, which, in turn, may cause large leakage currents to flow.FIG. 1 also shows theparasitic diode D 2 118 associated withQ 2 104. - A high value of the
IO pad 108 voltage may, therefore, compromise the reliability of the buffer circuit. - Disclosed are a method, an apparatus, and a system to generate a bias voltage to protect Input/Output (IO) circuits during a failsafe operation and a tolerant operation.
- In one aspect, a method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
- The external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation. The supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- In another aspect, a bias voltage generating circuit includes a multiplexer block configured to receive a first bias voltage controllably generated from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an IO core device of an IC to be interfaced with an IO pad, and to receive a second bias voltage controllably generated from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element (s) of the IO core device to be interfaced with the IO pad. The multiplexer block is also configured to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation through a controllable utilization of a control signal generated by the IO core.
- The external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation. The supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- In yet another aspect, an Input/Output (IO) includes an IO core-end block to generate a control signal, a driver block to drive one or more external active circuit element(s), an IO pad interfaced with the driver block, and a bias voltage generating circuit. The IO core-end block includes one or more constituent active circuit element(s) having an upper tolerable limit of an operating voltage thereof. The bias voltage generating circuit is configured to receive a supply voltage, to receive an external voltage supplied through the IO pad, and to generate an output bias voltage within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block.
- The bias voltage generating circuit includes a multiplexer block configured to receive a first bias voltage controllably generated from the supply voltage to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block to be interfaced with the IO pad, and to receive a second bias voltage controllably generated from the external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block to be interfaced with the IO pad. The bias voltage generating circuit is also configured to derive the output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation through a controllable utilization of the control signal generated by the IO core-end block.
- The external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation. The supply voltage is zero during the failsafe mode of operation, and the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.
- The methods and systems disclosed herein may be implemented in any means for achieving various aspects, and may be executed in a form of a machine-readable medium embodying a set of instructions that, when executed by a machine, cause the machine to perform any of the operations disclosed herein. Other features will be apparent from the accompanying drawings and from the detailed description that follows.
- The embodiments of this invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
-
FIG. 1 shows a schematic view of an output stage of a buffer circuit. -
FIG. 2 is a schematic view of a multiplexer circuit, according to one or more embodiments. -
FIG. 3 is a schematic view of a transistor implementation of the multiplexer circuit ofFIG. 2 , according to one or more embodiments. -
FIG. 4 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during a driver mode of operation, according to one or more embodiments. -
FIG. 5 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during a failsafe mode of operation, according to one or more embodiments. -
FIG. 6 is a plot of the DC characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during a tolerant mode of operation, according to one or more embodiments. -
FIG. 7 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during the failsafe mode of operation, according to one or more embodiments. -
FIG. 8 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during the tolerant mode of operation, according to one or more embodiments. -
FIG. 9 is a plot of the transient characteristics of the transistor implementation of the multiplexer circuit ofFIG. 2 during the driver mode of operation, according to one or more embodiments. -
FIG. 10 is a system view of an Input/Output (IO) circuit, according to one or more embodiments. -
FIG. 11 is a process flow detailing the operations involved in a method of generating an output bias voltage, according to one or more embodiments. - Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.
- Example embodiments, as described below, may be used to generate a bias voltage to protect Input/Output (IO) circuits during a failsafe operation and a tolerant operation. Although the present embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments.
-
FIG. 2 shows amultiplexer circuit 200, according to one or more embodiments. In one or more embodiments, themultiplexer circuit 200 includes amultiplexer block 202 that may receive afirst bias voltage 206 and asecond bias voltage 208 as the inputs. In one or more embodiments, thefirst bias voltage 206 may be controllably generated from a supply voltage (not shown inFIG. 2 ), and thesecond bias voltage 208 may be controllably generated from an external voltage supplied through an Input/Output (IO) pad (not shown inFIG. 2 ). In one or more embodiments, thefirst bias voltage 206 and thesecond bias voltage 208 may be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) (e.g., Metal-Oxide-Semiconductor (MOS) transistor) of an IO core device of an integrated circuit (IC) to be interfaced with the IO pad. - In one or more embodiments, the output of the
multiplexer block 202, shown as theoutput bias voltage 210 inFIG. 2 , may be derived from thefirst bias voltage 206 during a driver mode of operation, where the external voltage supplied through the IO pad may vary from zero to a value of the supply voltage, or from thesecond bias voltage 208 during a failsafe mode of operation and a tolerant mode of operation. In one or more embodiments, the supply voltage may be zero during the failsafe mode of operation, and the external voltage supplied through the IO pad may increase to a value above the supply voltage during the tolerant mode of operation. - In other words, as shown in
FIG. 2 , the output of themultiplexer block 210 may be based on a “high” or “low” state of a control signal 204 (e.g., Output Enable (OE)). The “high” state of thecontrol signal 204, which is a logic “1,” may indicate the presence of the supply voltage. The “low” state of thecontrol signal 204, which is a logic “0,” may indicate the absence of the supply voltage or the tolerant case, where the external voltage supplied through the IO pad may increase to a value above the supply voltage. Therefore, during the “low” state of thecontrol signal 204, the supply voltage may or may not be present. In one or more embodiments, thecontrol signal 204 may be generated by the IO core. - In one or more embodiments, the
control signal 204 may be utilized in a controllable manner to derive theoutput bias voltage 210. Therefore, theoutput bias voltage 210 may be derived from thefirst bias voltage 206 during the driver mode of operation when the state of thecontrol signal 204 is “high,” or thesecond bias voltage 208 during the failsafe mode of operation and the tolerant mode of operation when the state of thecontrol signal 204 is “low.” - In one or more embodiments, the
first bias voltage 206 may be controllably generated as a fraction of the supply voltage. In one or more embodiments, thesecond bias voltage 208 may be controllably generated as the external voltage supplied through the IO pad reduced by a threshold voltage of one or more active element(s) (e.g., Metal-Oxide-Semiconductor (MOS) transistors). -
FIG. 3 shows a transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 , according to one or more embodiments. It is obvious to one of ordinary skill in the art that the source (S) and drain (S) terminals of a MOS transistor are interchangeable and, therefore, coupling a voltage to the source (S) terminal and outputting another voltage from the drain (D) terminal is equivalent to coupling the voltage to the drain (D) terminal and outputting another voltage from the source (S) terminal. A drain-drain (D-D) path may also be equivalent to a source-drain (S-D) path. - In one or more embodiments, the
multiplexer block 202 includes a firstMOS transistor Q 4 322 configured to receive thefirst bias voltage 206 at the source (S) terminal thereof, and a pair of MOS transistors (Q 3 320 and Q5 324) configured to receive a controllable level shifted version of the control signal 204 (control signal LS 302) at gate (G) terminals thereof. In one or more embodiments,control signal LS 302 may be at a fraction of the supply voltage, VDDIO (not shown inFIG. 3 ), during each of the driver mode of operation and the tolerant mode of operation. In one or more embodiments, during the driver mode of operation,control signal LS 302 may be at a value higher (e.g., 0.6 VDDIO) than the value of control signal LS 302 (e.g., 0.1 VDDIO) during the tolerant mode of operation. In one or more embodiments,control signal LS 302 may be zero when the supply voltage (VDDIO) is zero during the failsafe mode of operation. - Therefore, in one or more embodiments,
control signal LS 302 may switch between 0.6 VDDIO during the driver mode of operation and 0.1 VDDIO during the tolerant mode of operation, depending on whether thecontrol signal 204 represents a logic “1” or logic “0.” However, as shown inFIG. 2 , logic “0” may also represent the failsafe mode of operation, wherecontrol signal LS 302 is zero. Therefore, the two states of thecontrol signal 204 may be better described as a logic “high” (during the driver mode of operation) and a logic “low” (during the tolerant mode of operation and the failsafe mode of operation). - In one or more embodiments, the drain (D) terminal of
Q 3 320 may be coupled to the drain (D) terminal ofQ 5 324. In one or more embodiments, the source (S) terminals ofQ 3 320 andQ 5 324 may be coupled to the gate (G) terminal and the drain (D) terminal ofQ 4 322 respectively. In one or more embodiments,Q 5 324 may be configured to receive thesecond bias voltage 208 at the drain (D) terminal thereof. In one or more embodiments, the drain (D) terminals ofQ 3 320 andQ 5 324 may be coupled to one another. In one or more embodiments,Q 3 320,Q 4 322 andQ 5 324 may be p-channel MOS (PMOS) transistors. In one or more embodiments, the output of themultiplexer block 202, theoutput bias voltage 210, may be taken at the drain-source (D-S) path betweenQ 4 322 and Q5 324 (node C 338). - In one or more embodiments, the
control signal 204 and thefirst bias voltage 206 may be applied at the gate (G) terminals ofMOS transistors Q 2 318 andQ 1 316 respectively. In one or more embodiments, the source (S) terminal ofQ 1 316 may be coupled to the drain (D) terminal ofQ 2 318, and the drain (D) terminal ofQ 1 316 may be coupled to the gate (G) terminal ofQ 4 322. In one or more embodiments, the bulk (B) terminals ofQ 1 316 andQ 2 318, and the source (S) terminal ofQ 2 318 may be held at a second supply voltage 314 (VSS). In one or more embodiments,Q 1 316 andQ 2 318 may be pass transistors (shown inFIG. 3 as NMOS transistors) configured to enablenode A 334 to be discharged whenQ 1 316 andQ 2 318 are switched ON during a logic “high” of thecontrol signal 204. In one or more embodiments, thefirst bias voltage 206 may be a fraction of the supply voltage VDDIO (e.g., 0.55 VDDIO). - In one or more embodiments, a pair of MOS transistors (
Q 6 326 and Q7 328) may be provided in the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 to reduce the external voltage supplied through the IO pad (IO pad 304 voltage) by the threshold voltages ofQ 6 326 andQ 7 328. Therefore, atnode B 336, thesecond bias voltage 208 may be expressed asExample Equation 1. -
V SB=IOPAD−2V tn, (1) - where VSB is the
second bias voltage 208, IOPAD is theIO pad 304 voltage, and Vtn is the threshold voltage of each ofQ 6 326 andQ 7 328.FIG. 3 showsQ 6 326 andQ 7 328 as n-channel MOS (NMOS) transistors, where the source (S) terminal ofQ 6 326 may be coupled to the drain (D) terminal ofQ 7 328. In one or more embodiments,IO pad 304 voltage may be applied at the source (S) terminal and the gate (G) terminal ofQ 7 328. In one or more embodiments, the gate (G) terminal ofQ 6 326 may be coupled to the source (S) terminal thereof. In one or more embodiments, the bulk (B) terminals ofQ 6 326 andQ 7 328 may be held at the second supply voltage 314 (VSS). One skilled in the art will appreciate that the number of active elements (e.g.,MOS transistors Q 6 326 and Q7 328) provided to reduce theIO pad 304 voltage may vary, and that such a variation is within the scope of the exemplary embodiments. - In one or more embodiments, the
second bias voltage 208 may, thus, be within an upper tolerable limit of one or more constituent active circuit element(s) (e.g., MOS transistors) of an IO core device of an IC to be interfaced with the IO pad. In one or more embodiments, in order to generate anoutput bias voltage 210 in and around the upper tolerance limit of the aforementioned constituent active circuit elements of the IO core device, aMOS transistor Q 9 332, whose gate (G) terminal and the drain (D) terminal are configured to receive controllable input voltages (V 3 306 andV 1 308 respectively), may be provided. In one or more embodiments, the source (S) terminal ofQ 9 332, shown inFIG. 3 as an NMOS transistor, may be coupled tonode B 336. In one or more embodiments,V 3 306 andV 1 308 may be controlled to be fractions of the supply voltage VDDIO. Forexample V 3 306 may be equal to 0.3 VDDIO andV 1 308 may be equal to 0.1 VDDIO. - In one or more embodiments, when supply voltage VDDIO is zero during the failsafe mode of operation,
Q 9 332 may pull maximum current to maximize the diode drops acrossQ 6 326 andQ 7 328. In one or more embodiments, when the supply voltage is present during the driver mode of operation and the tolerant mode of operation,Q 9 332 may pull a current that is less compared to the current during the failsafe mode of operation. In one or more embodiments, the diode drops acrossQ 6 326 andQ 7 328 may, therefore, decrease. - In one or more embodiments, the bulk (B) terminals of
Q 3 320,Q 4 322,Q 5 324, andQ 9 332 may be coupled to the output of a floating well (FW) circuit to avoid the forward biasing of parasitic diodes associated with the aforementioned transistors. - In one or more embodiments, during the driver mode of operation, i.e., when the control signal 204 (e.g., OE) is a logic “high” and the supply voltage VDDIO (e.g., 2.5 V) is present, the
first bias voltage 206 may be appropriately scaled to a fraction of VDDIO (e.g., 0.55 VDDIO). In one or more embodiments,control signal LS 302 may also be adjusted appropriately to a fraction of VDDIO. For example, the logic “high” of thecontrol signal 204 may indicate acontrol signal LS 302 value of 0.6 VDDIO. In one or more embodiments,pass transistors Q 1 316 andQ 2 318 may be turned ON, thereby enablingnode A 334 to be discharged. In one or more embodiments, the discharging ofnode A 334 may switchQ 4 322 oN, and the adjusted “high” level of control signal LS 302 (e.g., 0.6 VDDIO) may keepQ 3 320 andQ 5 324 switched OFF. In one or more embodiments, any perturbation at thenode B 336 may not affect the output atnode C 338, i.e., theoutput bias voltage 210. In one or more embodiments, theoutput bias voltage 210 may faithfully track thefirst bias voltage 206, and may be equal to thefirst bias voltage 206. - In one or more embodiments, during the failsafe mode of operation, i.e., when the
control signal 204 is a logic “low” and the supply voltage VDDIO is zero, thefirst bias voltage 206 andcontrol signal LS 302 may also be zero. Therefore, in one or more embodiments,node A 334 may not be able to discharge through the Q1 316-Q 2 318 path. When theIO pad 304 voltage increases,Q 6 326 andQ 7 328 may be turned ON, thereby enabling thesecond bias voltage 208 to track theIO pad 304 voltage as perexample Equation 1. In one or more embodiments, the logic “low” ofcontrol signal LS 302 may causeQ 3 320 andQ 5 324 to be turned ON, which may chargenode A 334. In one or more embodiments, the charging ofnode A 334 may turnQ 4 322 OFF. In one or more embodiments, asQ 5 324 may be ON, theoutput bias voltage 210 may track thesecond bias voltage 208. - In one or more embodiments, a
decoupling capacitor Q 8 330 may be used atnode C 338 to mitigate the effects of capacitive noise on theoutput bias voltage 210, which may be coupled to the gate (G) terminal of a MOS transistor of a driver of the IO pad, during switching of theIO pad 304 voltage. In one or more embodiments,Q 8 330 may be a NMOS capacitor, where theoutput bias voltage 210 is coupled to the gate (G) terminal thereof. In one or more embodiments, the gate (G), bulk (B), and drain (D) terminals ofQ 8 330 may all be held at the second supply voltage 310 (VSS) level. - In one or more embodiments, during the tolerant mode of operation, i.e, when the
control signal 204 is a logic “low” and the supply voltage VDDIO is present,control signal LS 302 may switch to a fraction of the supply voltage VDDIO that is lower than the value thereof during the driver mode of operation. For example,control signal LS 302 may switch to 0.1 VDDIO, which still may represent the logic “low.” In one or more embodiments, whenIO pad 304 voltage is low,Q 6 326 andQ 7 328 may be OFF, along withQ 2 318. Therefore, in one or more embodiments,node A 334 may not have a path to discharge, except for throughQ 4 322. In one or more embodiments, the discharging ofnode A 334 may cause theoutput bias voltage 210 to settle close to thefirst bias voltage 206 ofQ 4 322 through leakage current thereof. - In one or more embodiments, the tolerant mode of operation may be analogous to the driver mode of operation when the
IO pad 304 voltage is low. Here, the two cases have differingcontrol signal LS 302 values (0.6 VDDIO and 0.1 VDDIO respectively) to differentiate between the tolerant mode of operation and the driver mode of operation, when theIO pad 304 voltage increases to a value above the supply voltage VDDIO. - In one or more embodiments, when the
IO pad 304 voltage increases,Q 6 326 andQ 7 328 may be turned ON, thereby enabling thesecond bias voltage 208 to track theIO pad 304 voltage as perexample Equation 1. In one or more embodiments, the logic “low” ofcontrol signal LS 302 may causeQ 3 320 andQ 5 324 to be turned ON, which may chargenode A 334. In one or more embodiments, the charging ofnode A 334 may turnQ 4 322 OFF. In one or more embodiments, asQ 5 324 may be ON, theoutput bias voltage 210 may track thesecond bias voltage 208. - In one example embodiment, the supply voltage VDDIO may be 2.75 V (2.5V+10% tolerance),
IO pad 304 voltage may be 3.465 V (3.3 V+5% tolerance), and the operating voltage of one or more constituent active circuit element(s) of the IO core device may be 1.98 V (1.8 V+10% tolerance). In such a case, thefirst bias voltage 206, thesecond bias voltage 208, and theoutput bias voltage 210 may all be within 1.98 V. Additionally, thefirst bias voltage 206 and thesecond bias voltage 208 being within 1.98 V may facilitate reliable operation of constituent MOS transistors of themultiplexer circuit 200. -
FIG. 4 shows the DC characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the driver mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 402 may representIO pad 304 voltage and the y-axis 404 may represent a voltage variable (V). In one or more embodiments, as shown inFIG. 4 , theoutput bias voltage 210 may be equal to thefirst bias voltage 206 during all values ofIO pad 304 voltage. In one or more embodiments,control signal LS 302 and thefirst bias voltage 206 may be a fraction of the supply voltage VDDIO (e.g., 0.6 VDDIO) during the driver mode of operation (e.g., 0.6 VDDIO and 0.55 VDDIO respectively). -
FIG. 5 shows the DC characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the failsafe mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 502 may refer to theIO pad 304 voltage and the y-axis 504 may be a voltage variable (V). In one or more embodiments, the supply voltage VDDIO may be zero during the failsafe mode of operation. In one or more embodiments, theoutput bias voltage 210 may track thesecond bias voltage 208, as shown inFIG. 5 . In other words, theoutput bias voltage 210 may increase with the increase inIO pad 304 voltage. -
FIG. 6 shows the DC characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the tolerant mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 602 may refer to theIO pad 304 voltage and the y-axis 604 may refer to a voltage variable (V). In one or more embodiments, the supply voltage VDDIO may be present during the tolerant mode of operation, andcontrol signal LS 302 may be at a logic “low” (e.g., 0.1 VDDIO). In one or more embodiments, as shown inFIG. 6 and as discussed above, theoutput bias voltage 210 may settle close to thefirst bias voltage 206 when theIO pad 304 voltage is low. In one or more embodiments, when theIO pad 304 voltage increases,Q 6 326 andQ 7 328 may turn ON, and theoutput bias voltage 210 may start tracking thesecond bias voltage 208. -
FIG. 7 shows the transient characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the failsafe mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 702 may refer to time (t) and the y-axis 704 may refer to a voltage variable (V). In one or more embodiments, as theIO pad 304 voltage switches from 0 to a maximum value thereof (e.g., 3.465 V) and from the maximum value to 0, theoutput bias voltage 210 may switch from a low value (i.e., threshold voltage of Q4 322) to approximately thesecond bias voltage 208 and thesecond bias voltage 208 to the low value, as shown inFIG. 7 . In one or more embodiments, theoutput bias voltage 210 may be clamped to the threshold voltage ofQ 4 322 as there is no discharge path fornode A 334 otherwise. -
FIG. 8 shows the transient characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the tolerant mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 802 may refer to time (t) and the y-axis 804 may refer to a voltage variable (V). In one or more embodiments, as theIO pad 304 voltage switches from 0 to a maximum value thereof (e.g., 3.465 V) and from the maximum value to 0, theoutput bias voltage 210 may switch between two voltages, i.e., one close to thefirst bias voltage 206 and the other close to thesecond bias voltage 208, and vice versa. -
FIG. 9 shows the transient characteristics of the transistor implementation 300 of themultiplexer circuit 200 ofFIG. 2 during the driver mode of operation, according to one or more embodiments. In one or more embodiments, thex-axis 902 may refer to time (t) and the y-axis 904 may refer to a voltage variable (V). In one or more embodiments, theIO pad 304 voltage may vary from 0 to the value of the supply voltage VDDIO during the driver mode of operation. In one or more embodiments, as theIO pad 304 voltage switches between 0 and a maximum value thereof (e.g., VDDIO of 2.75 V), theoutput bias voltage 210 may be constant at the value of the first bias voltage 206 (e.g., 0.55 VDDIO). In one or more embodiments,control signal LS 302 may also be a fraction of the supply voltage VDDIO (e.g., 0.6 VDDIO). -
FIG. 10 shows a system view of anIO circuit 1000, according to one or more embodiments. In one or more embodiments, theIO circuit 1000 may include adriver block 1006 to drive external active circuit elements (e.g., MOS transistors) that may be interfaced with the IO core-end block 1002 through themultiplexer circuit 200 ofFIG. 2 . In one or more embodiments, the IO core-end block 1002 may include one or more constituent active circuit element(s) (e.g., MOS transistors) that have an upper tolerable limit of an operating voltage thereof (e.g., 1.98 V, 1.8 V+10% tolerance). In one or more embodiments, thecontrol signal 204 may be generated by the IO core-end block 1002. In one or more embodiments, themultiplexer circuit 200 may receive the supply voltage (VDDIO) 1004 and the external voltage supplied through an IO pad (shown as PAD 1008),IO pad 304 voltage, as shown inFIG. 10 . In one or more embodiments,PAD 1008 may be interfaced with thedriver block 1006. In one or more embodiments, themultiplexer circuit 200 may generate anoutput bias voltage 210 that may be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core-end block 1002. -
FIG. 11 is a process flow diagram detailing the operations involved in a method of generating theoutput bias voltage 210, according to one or more embodiments. In one or more embodiments,operation 1102 may involve controllably generating afirst bias voltage 206 from asupply voltage V DDIO 1004 to be within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block 1002. In one or more embodiments, the IO core-end block 1002 may be an IO device of an integrated circuit (IC) to be interfaced with an IO pad (PAD 1008). In one or more embodiments,operation 1104 may involve controllably generating asecond bias voltage 208 from the external voltage supplied through the IO pad (PAD 1008),IO pad 304 voltage, to be within the upper tolerable limit of the operating voltage of one or more constituent active circuit element(s) of the IO core-end block 1002. - In one or more embodiments,
operation 1106 may involve controllably utilizing thecontrol signal 204 generated by the IO core-end block 1002 to derive anoutput bias voltage 210 from thefirst bias voltage 206 during a driver mode of operation or thesecond bias voltage 208 during a failsafe mode of operation and a tolerant mode of operation. In one or more embodiments, the external voltage supplied through the IO pad (PAD 1008),IO pad 304 voltage, may vary from zero to a value of thesupply voltage V DDIO 1004 during the driver mode of operation. In one or more embodiments, the supply voltage VDDIO) 1004 may be zero during the failsafe mode of operation, and the external voltage supplied through the IO pad (PAD 1008),IO pad 304 voltage, may increase to a value above thesupply voltage V DDIO 1004 during the tolerant mode of operation. - Although the present embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. For example, variations in operating voltages and/or external voltages are within the scope of the exemplary embodiments. Also, for example, the various devices and modules described herein may be enabled and operated using hardware circuitry (e.g., CMOS based logic circuitry), firmware, software or any combination of hardware, firmware, and software (e.g., embodied in a machine readable medium). For example, the various electrical structure and methods may be embodied using transistors, logic gates, and electrical circuits (e.g., application specific integrated (ASIC) circuitry and/or in Digital Signal Processor (DSP) circuitry).
- In addition, it will be appreciated that the various operations, processes, and methods disclosed herein may be embodied in a machine-readable medium and/or a machine accessible medium compatible with a data processing system (e.g., a computer devices), and may be performed in any order (e.g., including using means for achieving the various operations). Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (20)
1. A method comprising:
controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an Input/Output (IO) receiver;
controllably generating a second bias voltage from an external voltage supplied through an IO pad, the second bias voltage being within the upper tolerable limit of the operating voltage of the IO receiver;
deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, the tolerant condition being a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage; and
deriving the output voltage from the second bias voltage during a failsafe condition, the failsafe condition being a mode of operation where the supply voltage is zero.
2. The method of claim 1 , comprising controllably generating a fraction of the supply voltage as the first bias voltage.
3. The method of claim 1 , comprising controllably generating the second bias voltage by reducing the external voltage supplied through the IO pad by a threshold voltage of at least one active element.
4. The method of claim 1 , comprising multiplexing the first bias voltage and the second bias voltage to output one of the first bias voltage and the second bias voltage based on the corresponding one of a presence and an absence of the supply voltage.
5. The method of claim 4 , wherein multiplexing the first bias voltage and the second bias voltage further comprises:
receiving the first bias voltage at one of a source terminal and a drain terminal of a first MOS transistor;
receiving the second bias voltage at one of a source terminal and a drain terminal of a second MOS transistor;
receiving the supply voltage at each of a gate terminal of the first MOS transistor and the second MOS transistor; and
coupling the one of the source terminal and the drain terminal of the first MOS transistor not receiving the first bias voltage to the one of the source terminal and the drain terminal of the second MOS transistor not receiving the second bias voltage.
6. The method of claim 5 , further comprising:
coupling a bulk terminal of the first MOS transistor to a second supply voltage;
coupling the one of the source terminal and the drain terminal of the second MOS transistor not receiving the second bias voltage to a bulk terminal of the second MOS transistor; and
deriving the output of the multiplexing from one of the first bias voltage during the normal condition and the tolerant condition and the second bias voltage during the failsafe operation through a path coupling the one of the source terminal and the drain terminal of the first MOS transistor not receiving the first bias voltage and the one of the source terminal and the drain terminal of the second MOS transistor not receiving the second bias voltage.
7. The method of claim 6 , further comprising:
applying the output of the multiplexing to a gate terminal of a pass MOS transistor;
coupling one of a source terminal and a drain terminal of the pass MOS transistor to the external voltage supplied through the IO pad;
coupling a bulk terminal of the pass MOS transistor to the second supply voltage; and
deriving the output voltage from the output of the multiplexing as an output from the one of the source terminal and the drain terminal of the pass MOS transistor not coupled to the external voltage supplied through the IO pad.
8. The method of claim 7 , further comprising reliably interfacing the output voltage derived from the output of the multiplexing with the IO receiver.
9. The method of claim 7 , further comprising ensuring the output voltage derived from the output of the multiplexing to be within the upper tolerable limit of the operating voltage of the IO receiver by providing a leakage path for the second bias voltage.
10. A circuit comprising:
a multiplexer block:
configured to receive a first bias voltage controllably generated from a supply voltage and a second bias voltage controllably generated from an external voltage supplied through an IO pad, the first bias voltage and the second bias voltage being within an upper tolerable limit of an operating voltage of an IO receiver, and
configured to output one of the first bias voltage during a normal condition and a tolerant condition and an output based on the second bias voltage during a failsafe condition based on a corresponding one of a presence and an absence of the supply voltage,
wherein the tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and
wherein the failsafe condition is a mode of operation where the supply voltage is zero.
11. The circuit of claim 10 , wherein:
the first bias voltage is a fraction of the supply voltage, and
the second bias voltage is equal to the external voltage supplied through the TO pad reduced by a threshold voltage of at least one active element.
12. The circuit of claim 10 , wherein the multiplexer block comprises:
a first MOS transistor configured to receive the first bias voltage at one of a source terminal and a drain terminal thereof; and
a second MOS transistor configured to receive the second bias voltage at one of a source terminal and a drain terminal thereof,
wherein each of a gate terminal of the first MOS transistor and the second MOS transistor is configured to receive the supply voltage, and
wherein the one of the source terminal and the drain terminal of the first MOS transistor not configured to receive the first bias voltage is configured to be coupled to the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage.
13. The circuit of claim 12 , wherein:
a bulk terminal of the first MOS transistor is configured to be coupled to a second supply voltage,
the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage is configured to be coupled to a bulk terminal of the second MOS transistor, and
the output of the multiplexer block is derived from a path configured to couple the one of the source terminal and the drain terminal of the first MOS transistor not configured to receive the first bias voltage and the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage.
14. The circuit of claim 13 , further comprising a pass MOS transistor configured to receive the output of the multiplexer block at a gate terminal thereof,
wherein one of a source terminal and a drain terminal of the pass MOS transistor is configured to be coupled to the external voltage supplied through the IO pad,
wherein a bulk terminal of the pass MOS transistor is configured to be coupled to the second supply voltage; and
wherein an output voltage is derived from the one of the source terminal and the drain terminal of the pass MOS transistor not configured to be coupled to the external voltage supplied through the IO pad.
15. The circuit of claim 14 , wherein the output voltage derived from the one of the source terminal and the drain terminal of the pass MOS transistor not configured to be coupled to the external voltage supplied through the IO pad is interfaced with the IO receiver.
16. The circuit of claim 14 , further comprising a leakage path for the second bias voltage to ensure that the output voltage derived from the one of the source terminal and the drain terminal of the pass MOS transistor not configured to be coupled to the external voltage supplied through the IO pad is within the upper tolerable limit of the operating voltage of the IO receiver.
17. An integrated circuit system comprising:
an IO pad of an integrated circuit;
an IO receiver; and
an IO interface circuit configured to interface the IO pad of the integrated circuit with the IO receiver, the IO interface circuit comprising:
a multiplexer block:
configured to receive a first bias voltage controllably generated from a supply voltage and a second bias voltage controllably generated from an external voltage supplied through the IO pad of the integrated circuit, the first bias voltage and the second bias voltage being within an upper tolerable limit of an operating voltage of the IO receiver, and
configured to output one of the first bias voltage during a normal condition and a tolerant condition and an output based on the second bias voltage during a failsafe condition based on a corresponding one of a presence and an absence of the supply voltage,
wherein the tolerant condition is a mode of operation where the external voltage supplied through the IO pad of the integrated circuit varies from zero to a value higher than the supply voltage, and
wherein the failsafe condition is a mode of operation where the supply voltage is zero.
18. The integrated circuit system of claim 17 , wherein:
the first bias voltage is a fraction of the supply voltage, and
the second bias voltage is equal to the external voltage supplied through the IO pad of the integrated circuit reduced by a threshold voltage of at least one active element.
19. The integrated circuit system of claim 17 , wherein the multiplexer block comprises:
a first MOS transistor configured to receive the first bias voltage at one of a source terminal and a drain terminal thereof; and
a second MOS transistor configured to receive the second bias voltage at one of a source terminal and a drain terminal thereof,
wherein each of a gate terminal of the first MOS transistor and the second MOS transistor is configured to receive the supply voltage, and
wherein the one of the source terminal and the drain terminal of the first MOS transistor not configured to receive the first bias voltage is configured to be coupled to the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage.
20. The integrated circuit system of claim 19 , wherein
a bulk terminal of the first MOS transistor is configured to be coupled to a second supply voltage,
the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage is configured to be coupled to a bulk terminal of the second MOS transistor, and
the output of the multiplexer block is derived from a path configured to couple the one of the source terminal and the drain terminal of the first MOS transistor not configured to receive the first bias voltage and the one of the source terminal and the drain terminal of the second MOS transistor not configured to receive the second bias voltage.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/610,277 US20110102046A1 (en) | 2009-10-31 | 2009-10-31 | Interfacing between differing voltage level requirements in an integrated circuit system |
CN201010000758.7A CN102055459B (en) | 2009-10-31 | 2010-01-18 | Bias voltage generation to protect input/output (IO) circuits during failsafe operation and tolerant operation |
EP10152680.4A EP2317651B1 (en) | 2009-10-31 | 2010-02-04 | Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation |
TW099103684A TWI406500B (en) | 2009-10-31 | 2010-02-06 | Bias voltage generation to protect input/output (io) circuits during a failsafe operation and a tolerant operation |
JP2010043602A JP5598750B2 (en) | 2009-10-31 | 2010-02-27 | Method for generating bias voltage for protecting input / output circuit in fail-safe mode and tolerant mode, bias voltage generating circuit, and input / output circuit |
US12/889,440 US8125267B2 (en) | 2009-10-31 | 2010-09-24 | Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US12/610,277 US20110102046A1 (en) | 2009-10-31 | 2009-10-31 | Interfacing between differing voltage level requirements in an integrated circuit system |
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US12/889,440 Continuation US8125267B2 (en) | 2009-10-31 | 2010-09-24 | Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation |
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US20110102046A1 true US20110102046A1 (en) | 2011-05-05 |
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Application Number | Title | Priority Date | Filing Date |
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US12/889,440 Expired - Fee Related US8125267B2 (en) | 2009-10-31 | 2010-09-24 | Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation |
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US12/889,440 Expired - Fee Related US8125267B2 (en) | 2009-10-31 | 2010-09-24 | Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation |
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US (2) | US20110102046A1 (en) |
EP (1) | EP2317651B1 (en) |
JP (1) | JP5598750B2 (en) |
CN (1) | CN102055459B (en) |
TW (1) | TWI406500B (en) |
Cited By (1)
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US11664659B2 (en) * | 2017-11-03 | 2023-05-30 | Continental Teves Ag & Co. Ohg | Polarity-reversal protection arrangement, method for operating the polarity-reversal-protection arrangement and corresponding use |
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US7834653B1 (en) * | 2009-10-31 | 2010-11-16 | Lsi Corporation | Failsafe and tolerant driver architecture and method |
CN106961271B (en) * | 2016-01-12 | 2020-07-07 | 中芯国际集成电路制造(上海)有限公司 | Signal receiving device and signal processing apparatus |
US11169590B2 (en) * | 2019-07-19 | 2021-11-09 | Arm Limited | Core ramp detection circuitry |
US11652476B2 (en) | 2021-01-28 | 2023-05-16 | Mediatek Inc. | Pad-tracking circuit design to prevent leakage current during power ramp up or ramp down of output buffer |
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Also Published As
Publication number | Publication date |
---|---|
TW201115919A (en) | 2011-05-01 |
CN102055459B (en) | 2014-04-09 |
JP5598750B2 (en) | 2014-10-01 |
EP2317651B1 (en) | 2013-09-11 |
US20110102048A1 (en) | 2011-05-05 |
CN102055459A (en) | 2011-05-11 |
US8125267B2 (en) | 2012-02-28 |
TWI406500B (en) | 2013-08-21 |
JP2011097551A (en) | 2011-05-12 |
EP2317651A1 (en) | 2011-05-04 |
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