JP4398223B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4398223B2 JP4398223B2 JP2003371053A JP2003371053A JP4398223B2 JP 4398223 B2 JP4398223 B2 JP 4398223B2 JP 2003371053 A JP2003371053 A JP 2003371053A JP 2003371053 A JP2003371053 A JP 2003371053A JP 4398223 B2 JP4398223 B2 JP 4398223B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring board
- semiconductor device
- wiring
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図1は、本発明の半導体装置の好適な構造の一例を示す断面図であり、図2は、図1の半導体装置の要部である配線基板の半導体素子搭載面を示す平面図である。
半導体素子1:底面に半田バンプを有するシリコンチップ
大きさ;15mm平方
厚さ;0.6mm
配線基板2;上面に銅製配線パターン、下面に半田ボール7が形成され、配線パターンと半田ボール7とはビアホール導体で接続されたガラスエポキシ樹脂製
大きさ;40mm平方
厚さ;0.7mm
支持フレーム;外形40mm平方、内径26mm平方、厚さ0.7mm
放熱板;アルミ製
大きさ;40mm平方
厚さ0.5mm
2:配線基板
3:放熱板
4:支持フレーム
5:半田バンプ
7:半田ボール
10:補強フレーム
Claims (3)
- 樹脂製絶縁基板に配線パターンを形成してなり、上面に支持フレームを有する配線基板と、底面に半田バンプを有し且つ該半田バンプを介して前記配線基板の上面にフリップチップ実装された半導体素子と、前記配線基板の上面を覆うように配置され且つ前記支持フレーム及び前記半導体素子に接着固定された放熱板とからなる半導体装置において、高さ0.2mm以上で前記半導体素子の厚みよりも低い金属製または有機樹脂製の補強フレームが、前記半導体素子と前記支持フレームとの間に前記半導体素子を取り囲むように上端が前記放熱板とは非接触に配置され、前記配線基板の上面に接着されていることを特徴とする半導体装置。
- 前記補強フレームは、実装された半導体素子と同心相似形に配置されており、且つ該補強フレームの各辺部の内側長さは、該半導体素子の対応する辺の長さの1.2倍以下である請求項1に記載の半導体装置。
- 前記配線基板の裏面には、前記半導体素子に導通し且つ半導体素子底面に形成された半田バンプよりも低融点の半田バンプが設けられている請求項1または2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371053A JP4398223B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371053A JP4398223B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005136220A JP2005136220A (ja) | 2005-05-26 |
JP4398223B2 true JP4398223B2 (ja) | 2010-01-13 |
Family
ID=34647862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003371053A Expired - Fee Related JP4398223B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4398223B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8313984B2 (en) * | 2008-03-19 | 2012-11-20 | Ati Technologies Ulc | Die substrate with reinforcement structure |
JP2010103338A (ja) * | 2008-10-24 | 2010-05-06 | Nec Electronics Corp | 半導体装置、及びその製造方法 |
JPWO2011074221A1 (ja) | 2009-12-14 | 2013-04-25 | パナソニック株式会社 | 半導体装置 |
-
2003
- 2003-10-30 JP JP2003371053A patent/JP4398223B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005136220A (ja) | 2005-05-26 |
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