JP4388926B2 - 半導体装置のパッケージ構造 - Google Patents

半導体装置のパッケージ構造 Download PDF

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Publication number
JP4388926B2
JP4388926B2 JP2005336256A JP2005336256A JP4388926B2 JP 4388926 B2 JP4388926 B2 JP 4388926B2 JP 2005336256 A JP2005336256 A JP 2005336256A JP 2005336256 A JP2005336256 A JP 2005336256A JP 4388926 B2 JP4388926 B2 JP 4388926B2
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
electrode
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005336256A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006080564A (ja
JP2006080564A5 (enExample
Inventor
盛義 中島
和男 小林
夏夫 味香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Genusion Inc
Original Assignee
Genusion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genusion Inc filed Critical Genusion Inc
Priority to JP2005336256A priority Critical patent/JP4388926B2/ja
Publication of JP2006080564A publication Critical patent/JP2006080564A/ja
Publication of JP2006080564A5 publication Critical patent/JP2006080564A5/ja
Application granted granted Critical
Publication of JP4388926B2 publication Critical patent/JP4388926B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Tests Of Electronic Circuits (AREA)
JP2005336256A 2005-11-21 2005-11-21 半導体装置のパッケージ構造 Expired - Fee Related JP4388926B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005336256A JP4388926B2 (ja) 2005-11-21 2005-11-21 半導体装置のパッケージ構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005336256A JP4388926B2 (ja) 2005-11-21 2005-11-21 半導体装置のパッケージ構造

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004164489A Division JP3842272B2 (ja) 2004-06-02 2004-06-02 インターポーザー、半導体チップマウントサブ基板および半導体パッケージ

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2008157557A Division JP4303772B2 (ja) 2008-06-17 2008-06-17 半導体パッケージ
JP2008160559A Division JP4388989B2 (ja) 2008-06-19 2008-06-19 半導体チップマウント封止サブ基板

Publications (3)

Publication Number Publication Date
JP2006080564A JP2006080564A (ja) 2006-03-23
JP2006080564A5 JP2006080564A5 (enExample) 2007-07-19
JP4388926B2 true JP4388926B2 (ja) 2009-12-24

Family

ID=36159708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005336256A Expired - Fee Related JP4388926B2 (ja) 2005-11-21 2005-11-21 半導体装置のパッケージ構造

Country Status (1)

Country Link
JP (1) JP4388926B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545031B2 (en) * 2005-04-11 2009-06-09 Stats Chippac Ltd. Multipackage module having stacked packages with asymmetrically arranged die and molding
US7420206B2 (en) 2006-07-12 2008-09-02 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
US7638868B2 (en) * 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package

Also Published As

Publication number Publication date
JP2006080564A (ja) 2006-03-23

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