JP4376448B2 - プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法 - Google Patents

プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法 Download PDF

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Publication number
JP4376448B2
JP4376448B2 JP2000369833A JP2000369833A JP4376448B2 JP 4376448 B2 JP4376448 B2 JP 4376448B2 JP 2000369833 A JP2000369833 A JP 2000369833A JP 2000369833 A JP2000369833 A JP 2000369833A JP 4376448 B2 JP4376448 B2 JP 4376448B2
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JP
Japan
Prior art keywords
region
resin
base material
semiconductor device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000369833A
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English (en)
Japanese (ja)
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JP2001344587A (ja
JP2001344587A5 (enExample
Inventor
健児 前田
隆 高田
浩喜 楢岡
太 本間
茂 野々山
良之 新井
雄一郎 山田
史人 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000369833A priority Critical patent/JP4376448B2/ja
Publication of JP2001344587A publication Critical patent/JP2001344587A/ja
Publication of JP2001344587A5 publication Critical patent/JP2001344587A5/ja
Application granted granted Critical
Publication of JP4376448B2 publication Critical patent/JP4376448B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2000369833A 2000-03-30 2000-12-05 プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法 Expired - Fee Related JP4376448B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000369833A JP4376448B2 (ja) 2000-03-30 2000-12-05 プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000093188 2000-03-30
JP2000-93188 2000-03-30
JP2000369833A JP4376448B2 (ja) 2000-03-30 2000-12-05 プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法

Publications (3)

Publication Number Publication Date
JP2001344587A JP2001344587A (ja) 2001-12-14
JP2001344587A5 JP2001344587A5 (enExample) 2006-08-17
JP4376448B2 true JP4376448B2 (ja) 2009-12-02

Family

ID=26588818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000369833A Expired - Fee Related JP4376448B2 (ja) 2000-03-30 2000-12-05 プリント配線基板およびそれを用いたicカード用モジュールならびにその製造方法

Country Status (1)

Country Link
JP (1) JP4376448B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3866178B2 (ja) 2002-10-08 2007-01-10 株式会社ルネサステクノロジ Icカード
WO2008152774A1 (ja) * 2007-06-15 2008-12-18 Panasonic Corporation メモリカードおよびその製造方法
JP4634436B2 (ja) * 2007-12-14 2011-02-16 ルネサスエレクトロニクス株式会社 Icカードの製造方法
WO2013132815A1 (ja) * 2012-03-09 2013-09-12 日本電気株式会社 電子部品内蔵モジュールおよび電子機器並びに電子部品内蔵モジュールの製造方法
JP2015130379A (ja) * 2014-01-06 2015-07-16 アピックヤマダ株式会社 樹脂封止製品の製造方法および樹脂封止製品
JP6016965B2 (ja) * 2015-03-02 2016-10-26 三菱電機株式会社 電子機器ユニット及びその製造金型装置

Also Published As

Publication number Publication date
JP2001344587A (ja) 2001-12-14

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