JP4373065B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP4373065B2
JP4373065B2 JP2002274466A JP2002274466A JP4373065B2 JP 4373065 B2 JP4373065 B2 JP 4373065B2 JP 2002274466 A JP2002274466 A JP 2002274466A JP 2002274466 A JP2002274466 A JP 2002274466A JP 4373065 B2 JP4373065 B2 JP 4373065B2
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JP
Japan
Prior art keywords
wiring
center
distance
layer
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002274466A
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English (en)
Japanese (ja)
Other versions
JP2004111771A (ja
Inventor
知生 村田
忍 矢吹
毅雄 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2002274466A priority Critical patent/JP4373065B2/ja
Priority to TW092122781A priority patent/TW200405515A/zh
Priority to US10/647,373 priority patent/US7245019B2/en
Priority to KR1020030059429A priority patent/KR20040025817A/ko
Priority to CNB031555985A priority patent/CN100336198C/zh
Publication of JP2004111771A publication Critical patent/JP2004111771A/ja
Application granted granted Critical
Publication of JP4373065B2 publication Critical patent/JP4373065B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2002274466A 2002-09-20 2002-09-20 半導体装置およびその製造方法 Expired - Fee Related JP4373065B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002274466A JP4373065B2 (ja) 2002-09-20 2002-09-20 半導体装置およびその製造方法
TW092122781A TW200405515A (en) 2002-09-20 2003-08-19 Semiconductor device and the manufacturing method thereof
US10/647,373 US7245019B2 (en) 2002-09-20 2003-08-26 Semiconductor device with improved wiring arrangement utilizing a projecting portion and a method of manufacturing the same
KR1020030059429A KR20040025817A (ko) 2002-09-20 2003-08-27 반도체장치 및 그 제조방법
CNB031555985A CN100336198C (zh) 2002-09-20 2003-08-29 半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002274466A JP4373065B2 (ja) 2002-09-20 2002-09-20 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2004111771A JP2004111771A (ja) 2004-04-08
JP4373065B2 true JP4373065B2 (ja) 2009-11-25

Family

ID=31986958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002274466A Expired - Fee Related JP4373065B2 (ja) 2002-09-20 2002-09-20 半導体装置およびその製造方法

Country Status (5)

Country Link
US (1) US7245019B2 (enExample)
JP (1) JP4373065B2 (enExample)
KR (1) KR20040025817A (enExample)
CN (1) CN100336198C (enExample)
TW (1) TW200405515A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071097B2 (en) * 2004-07-09 2006-07-04 International Business Machines Corporation Method for improved process latitude by elongated via integration
JP4801333B2 (ja) 2004-07-23 2011-10-26 パナソニック株式会社 電源配線構造および該電源配線構造を備えた半導体集積回路
US7332812B2 (en) * 2005-04-14 2008-02-19 Infineon Technologies Ag Memory card with connecting portions for connection to an adapter
JP4796817B2 (ja) * 2005-10-31 2011-10-19 エルピーダメモリ株式会社 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
US7685480B1 (en) * 2007-06-18 2010-03-23 Netlogic Microsystems, Inc. Content addressable memory having redundant row isolated noise circuit and method of use
JP2010003712A (ja) * 2007-08-09 2010-01-07 Renesas Technology Corp 半導体装置、半導体装置の配置配線方法、及びデータ処理システム
US7886240B2 (en) * 2008-01-29 2011-02-08 International Business Machines Corporation Modifying layout of IC based on function of interconnect and related circuit and design structure
JP2010187005A (ja) * 2010-03-30 2010-08-26 Fujitsu Semiconductor Ltd 複数の配線層を有する半導体回路の端子層設定に用いられる端子延長用コンポーネント
US8533641B2 (en) * 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
US10020261B2 (en) * 2016-10-14 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Split rail structures located in adjacent metal layers
US10964639B2 (en) 2017-10-20 2021-03-30 Samsung Electronics Co., Ltd. Integrated circuits including via array and methods of manufacturing the same
DE102020105474A1 (de) 2020-03-02 2021-09-02 Infineon Technologies Ag Integrierter Schaltkreis

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186655A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体集積回路
JP3221383B2 (ja) 1997-12-17 2001-10-22 日本電気株式会社 半導体装置の多層配線構造
JP2000077634A (ja) * 1998-09-02 2000-03-14 Seiko Epson Corp 半導体装置
JP2001044196A (ja) 1999-07-30 2001-02-16 Fujitsu Ltd 半導体装置
JP3822009B2 (ja) * 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体

Also Published As

Publication number Publication date
US7245019B2 (en) 2007-07-17
US20040056280A1 (en) 2004-03-25
JP2004111771A (ja) 2004-04-08
CN100336198C (zh) 2007-09-05
TWI314351B (enExample) 2009-09-01
TW200405515A (en) 2004-04-01
CN1487580A (zh) 2004-04-07
KR20040025817A (ko) 2004-03-26

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