JP4368795B2 - プロセッサ間で通信を行うための改良プロセッサ間通信システム - Google Patents

プロセッサ間で通信を行うための改良プロセッサ間通信システム Download PDF

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Publication number
JP4368795B2
JP4368795B2 JP2004522393A JP2004522393A JP4368795B2 JP 4368795 B2 JP4368795 B2 JP 4368795B2 JP 2004522393 A JP2004522393 A JP 2004522393A JP 2004522393 A JP2004522393 A JP 2004522393A JP 4368795 B2 JP4368795 B2 JP 4368795B2
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processor
unit
direct memory
memory access
programmable
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Japanese (ja)
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JP2005534094A (ja
Inventor
シュテファン、コッホ
ハンス‐ヨアヒム、ゲルケ
ハラルト、バウアー
アルトゥル、トリッタート
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NXP BV
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NXP BV
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Exchange Systems With Centralized Control (AREA)
JP2004522393A 2002-07-23 2003-07-16 プロセッサ間で通信を行うための改良プロセッサ間通信システム Expired - Fee Related JP4368795B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02016492 2002-07-23
PCT/IB2003/002813 WO2004010308A2 (en) 2002-07-23 2003-07-16 Improved inter-processor communication system for communication between processors

Publications (2)

Publication Number Publication Date
JP2005534094A JP2005534094A (ja) 2005-11-10
JP4368795B2 true JP4368795B2 (ja) 2009-11-18

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JP2004522393A Expired - Fee Related JP4368795B2 (ja) 2002-07-23 2003-07-16 プロセッサ間で通信を行うための改良プロセッサ間通信システム

Country Status (7)

Country Link
US (1) US20060123152A1 (de)
EP (1) EP1535169B1 (de)
JP (1) JP4368795B2 (de)
CN (1) CN100447768C (de)
AT (1) ATE543138T1 (de)
AU (1) AU2003246991A1 (de)
WO (1) WO2004010308A2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100334581C (zh) * 2004-04-02 2007-08-29 明基电通股份有限公司 在多个微处理器间传输数据的嵌入式计算机系统及方法
JP2006059303A (ja) * 2004-08-24 2006-03-02 Oki Electric Ind Co Ltd コンピュータシステム
JP2006133968A (ja) * 2004-11-04 2006-05-25 Fujitsu Ltd 情報処理装置
US8732368B1 (en) * 2005-02-17 2014-05-20 Hewlett-Packard Development Company, L.P. Control system for resource selection between or among conjoined-cores
CN101098527B (zh) * 2006-06-27 2012-06-13 雅斯拓（北京）智能卡科技有限公司 同时处理个人令牌中的数据传输会话的线程控制器
US7984301B2 (en) 2006-08-17 2011-07-19 Inside Contactless S.A. Bi-processor architecture for secure systems
JP4476267B2 (ja) * 2006-10-06 2010-06-09 株式会社日立製作所 プロセッサ及びデータ転送ユニット
US20100077472A1 (en) * 2008-09-23 2010-03-25 Atmel Corporation Secure Communication Interface for Secure Multi-Processor System
US8321618B1 (en) 2009-07-28 2012-11-27 Nvidia Corporation Managing conflicts on shared L2 bus
US8195858B1 (en) * 2009-07-28 2012-06-05 Nvidia Corporation Managing conflicts on shared L2 bus
CN102063337B (zh) * 2009-11-17 2014-01-08 中兴通讯股份有限公司 多处理器核的信息交互和资源分配的方法及系统
US8458377B2 (en) * 2010-03-05 2013-06-04 Lsi Corporation DMA engine capable of concurrent data manipulation
KR101685407B1 (ko) * 2010-07-29 2016-12-13 삼성전자주식회사 멀티코어 시스템을 위한 다이렉트 메모리 억세스 장치 및 다이렉트 메모리 억세스 장치의 동작 방법
US9762434B2 (en) 2011-08-12 2017-09-12 Rambus Inc. Temporal redundancy
FR3026869B1 (fr) * 2014-10-07 2016-10-28 Sagem Defense Securite Systeme embarque sur puce a haute surete de fonctionnement
US10303630B2 (en) * 2017-10-08 2019-05-28 Huawei Technologies Co., Ltd. Configurable hardware accelerators
CN111427816A (zh) * 2020-03-04 2020-07-17 深圳震有科技股份有限公司 一种amp系统核间通讯方法、计算机设备及存储介质
CN112181878B (zh) * 2020-08-28 2022-04-08 珠海欧比特宇航科技股份有限公司 RapidIO接口架构和数据处理方法
CN112838888A (zh) * 2021-01-11 2021-05-25 深圳震有科技股份有限公司 一种基于5g的卫星编解码并发计算方法和系统
CN114228725A (zh) * 2021-11-23 2022-03-25 深圳元戎启行科技有限公司 车载控制系统以及无人驾驶车辆
US20260088976A1 (en) * 2024-09-26 2026-03-26 Xilinx, Inc. Acceleration of cryptographic operations

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229160A (ja) * 1984-04-26 1985-11-14 Toshiba Corp マルチプロセツサシステム
US5283903A (en) * 1986-12-25 1994-02-01 Nec Corporation Priority selector
US5222227A (en) * 1987-01-16 1993-06-22 Hitachi, Ltd. Direct memory access controller for a multi-microcomputer system
JPH02109153A (ja) * 1988-10-18 1990-04-20 Fujitsu Ltd プロセッサ間データ伝送方式
US5289588A (en) * 1990-04-24 1994-02-22 Advanced Micro Devices, Inc. Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
JP3196637B2 (ja) * 1996-04-26 2001-08-06 三菱電機株式会社 ソートプロセッサおよびソート処理装置
US5890013A (en) * 1996-09-30 1999-03-30 Intel Corporation Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency
CN1293494C (zh) * 1999-09-09 2007-01-03 上海贝尔有限公司 主从式多处理器系统中的通信接口
JP4915631B2 (ja) * 2000-09-06 2012-04-11 エスティー‐エリクソン、ソシエテ、アノニム プロセッサ間通信システム
US6775717B1 (en) * 2001-08-31 2004-08-10 Integrated Device Technology, Inc. Method and apparatus for reducing latency due to set up time between DMA transfers

Also Published As

Publication number Publication date
AU2003246991A1 (en) 2004-02-09
CN100447768C (zh) 2008-12-31
EP1535169A2 (de) 2005-06-01
US20060123152A1 (en) 2006-06-08
AU2003246991A8 (en) 2004-02-09
WO2004010308A2 (en) 2004-01-29
EP1535169B1 (de) 2012-01-25
ATE543138T1 (de) 2012-02-15
CN1688986A (zh) 2005-10-26
WO2004010308A3 (en) 2005-04-07
JP2005534094A (ja) 2005-11-10

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