JP4353324B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an interface unit for interfacing multiple bits of information in parallel with the outside, and more particularly to a technique for suppressing a deviation in fixed timing of a multiple bit signal interfaced in parallel by an interface unit. For example, the present invention relates to a technique effective when applied to an SDRAM (Synchronous Dynamic Random Access Memory) capable of DDR (Double Data Rate) operation.
[0002]
[Prior art]
The operation timing of a synchronous memory such as SDRAM is controlled based on an external clock signal such as an external system clock signal. This type of synchronous memory is characterized in that the internal operation timing can be set relatively easily by using an external clock signal, and a relatively high-speed operation can be achieved.
[0003]
For example, as an SDRAM, a so-called SDR (Single Data Rate) type SDRAM (SDR-SDRAM) in which data input and output are performed in synchronization with a rising edge of an external clock signal, and data input and output are external clock signals or A so-called DDR type SDRAM (DDR-SDRAM) is known which is performed in synchronization with both the rising edge and falling edge of a data strobe signal.
[0004]
Examples of documents describing such SDRAM include 64 Meg DDR-SDRAM JEDDDRDS. pm65-Rev. 7/5/99 JEDEC (Joint Electron Engineering Engineering Council) data sheet.
[0005]
A clock synchronous memory represented by an SDRAM has an output timing control circuit such as a latch circuit for determining data output timing in the data output circuit, and an input timing control circuit such as a latch circuit for determining data input timing. It has in the data input circuit. For example, in a data input circuit of an SDRAM, data supplied in synchronization with an external clock signal or data strobe signal is input to a data input buffer, and the input data is latched in an input data latch circuit and transmitted to a subsequent stage. To go. The latch operation of the input data latch circuit is controlled by an internal timing signal (input latch timing signal) synchronized with the external clock signal or data strobe signal. The data output circuit of the SDRAM latches data to be output by an output latch timing signal generated internally in synchronization with the external clock signal, and outputs the latched data from the output buffer to the outside. The DDR-SDRAM outputs a data strobe signal in synchronization with the output latch timing signal together with the data output.
[0006]
In general, the data input circuit and the data output circuit are arranged in the vicinity of an array of external data terminals such as bonding pads and bump electrodes in the semiconductor chip. In such a layout, output timing signals are sequentially propagated serially to each output timing control circuit of the data output circuit arranged in parallel along the external data terminal, and also arranged in parallel along the external data terminal. Input timing signals are sequentially propagated serially to each input timing control circuit of the data input circuit.
[0007]
[Problems to be solved by the invention]
The present inventor has studied the difference between the output latch timing and the input latch timing at the base end and the end of the timing control wiring through which the timing signal is propagated in series.
[0008]
First, since the output latch timing is shifted between the base end and the terminal end of the timing control wiring through which the output timing signal is propagated, the time range in which the output data is valid or determined is sequentially shifted at each data terminal accordingly. Therefore, the time range (output data valid window) in which the output data of all data terminals that perform parallel data output are valid or fixed for all bits is a common divisor range for each valid time range of the output data, and the timing It becomes narrower as the shift of the output latch timing between the base end and the end of the control wiring becomes larger. If the output data valid window is relatively small with respect to each effective time range of the output data, the time margin for receiving the read data of the SDRAM is reduced, and the timing design on the data processing system using the SDRAM is reduced. It becomes difficult and it becomes impossible to cope with the increase in operating speed.
[0009]
Similarly, since the input latch timing is shifted between the base end and the end of the timing control wiring through which the input timing signal is propagated, the time range in which the input circuit can latch input data supplied in parallel to each data terminal Will shift sequentially. For this reason, the time range (input data valid window) in which all bits of input data to be supplied in parallel to all data terminals are valid or determined is for each valid time range in which each input circuit can latch input data. The time range becomes a common multiple and becomes wider as the shift of the input latch timing between the base end and the end of the timing control wiring increases. If the input data valid window is relatively wide with respect to the valid time range in which each input circuit can latch input data, the setup time and hold time of the input data cannot be taken relatively large, and the operation speed can be increased. become unable.
[0010]
Considering the above-mentioned problem from the viewpoint of layout, when the input circuit and output circuit pairs are arranged alternately corresponding to the arrangement of the data terminals, the timing control wiring and output timing through which the input timing signal is propagated As a result of laying the timing control wiring through which the signal is propagated along the arrangement of the input circuit and the output circuit, the tendency that the input data valid window is relatively wide and the output data valid window is relatively narrow becomes remarkable. It was revealed that it was easy. In particular, since the DDR-SDRAM has a data rate twice that of the SDR-SDRAM even when the operation clock frequency is the same, it is indispensable to cope with high speed in terms of the input data valid window and the output data valid window.
[0011]
Further, the present inventors have clarified that the sizes of the input data valid window and the output data valid window are not only due to the length or time constant of the timing control wiring but also depend on the configuration of the latch circuit. . That is, assuming a latch circuit including an input gate composed of a first clocked inverter and a static latch having a second clocked inverter that is activated in the opposite phase to the first clocked inverter, When the clock signal and the clock signal obtained by inverting the clock signal by the inverter are used for activation control of both clocked inverters, the first clocked inverter of the input gate is changed from the inactive state to the active state. In the transient response state until the clocked inverter of the transition from the active state to the inactive state, the input change may not be reflected in the output. Such a transient response condition causes the input data valid window to be undesirably widened and the output data valid window to be undesirably narrowed.
[0012]
An object of the present invention is to provide a semiconductor device capable of reducing variation or deviation in data input timing in a plurality of data input circuits to which data is supplied in parallel. Furthermore, the present invention intends to provide a semiconductor device capable of narrowing an input data valid window.
[0013]
Another object of the present invention is to provide a semiconductor device capable of reducing variation or deviation in data output timing in a plurality of data output circuits that output data in parallel. Furthermore, the present invention intends to provide a semiconductor device capable of increasing the output data valid window.
[0014]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0015]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0016]
[1] The first aspect of the present invention focuses on reducing skew on the timing control wiring of interface operation timing signals of interface circuits operated in parallel.
[0017]
That is, the semiconductor device has a plurality of bits for interfacing with a plurality of bits of information in parallel. First Interface terminal A plurality of first interface terminals through which the corresponding information is input / output via each of the first interface terminals When , Double Several The first A plurality of interface circuits provided corresponding to each of the interface terminals A plurality of first interface circuits each having an input circuit and an output circuit; And the semiconductor chip, the plurality of The first of The interface circuit of A first input circuit group in which the respective input circuits are grouped, and a first output circuit group in which the respective output circuits are grouped. Each group is divided into To Is , Timing signals for controlling interface operations are supplied serially in groups. First Timing control wiring is connected.
[0018]
According to the above, compared to the case where a plurality of interface circuits used for parallel interface with the outside are grouped together and the timing signal is supplied in series with a common timing control wiring, the base end of the timing control wiring And the difference (skew) in the propagation delay of the timing signal at the end. In other words, variation in data input timing in a plurality of data input circuits to which data is input in parallel, and variation in data output timing in a plurality of data output circuits that output data in parallel are Can be distributed every time. In short, the skew of the timing signal can be reduced for each group. As a result, the input data valid window can be made smaller and the output data valid window can be made larger than when no grouping is performed.
[0019]
As the interface circuits of each group are concentrated and arranged for each group, the difference in propagation delay of the timing signal between the base end and the end of the timing control wiring in the group becomes smaller. In other words, the skew of the timing signal is reduced within the group.
[0020]
The interface terminal includes a data terminal, and the interface circuit includes a data output circuit connected to the data terminal. The interface circuit includes a data input circuit connected to the data terminal. For example, the data terminal is used as a data input / output terminal that is also used for data input and output. Each data terminal is coupled to the input terminal of the data input circuit on one side and to the output terminal of the data output circuit on the other side. .
[0021]
The layout of the group of the circuits operated in parallel interface can be symmetric with respect to the base end of the control wiring, and can be asymmetric with respect to the left and right. A driver is provided at the base end of the timing control wiring for each group, and a driver having a relatively large driving capability may be connected to a timing control line having a relatively large load.
[0022]
When the interface circuit includes a buffer circuit connected to a corresponding interface terminal and a latch circuit connected to the corresponding buffer circuit and performing a latch operation of information to be interfaced, the timing signal is the latch circuit Latch control signal. In the case of the input circuit, for example, data supplied in synchronization with the change in the data strobe signal is input to the buffer circuit, and latched in the latch circuit in response to the latch control signal in synchronization with the change in the data strobe signal. Is transmitted to. In the case of an output circuit, for example, data to be output obtained by an internal operation is latched in a data latch circuit by a latch control signal synchronized with an external clock signal, and is output to the outside through an output buffer.
[0023]
In addition to the means for reducing the skew of the timing signal, at least a substantially equal delay component (time constant) in each of the groups is set in the interface signal wiring connecting the buffer circuit and the interface terminal. Thus, it is possible to easily reduce the situation in which the input data valid window and the output data valid window are adversely affected by the delay variation caused by the interface signal wiring. Here, setting equal delay components means matching with the delay time of the route requiring the longest delay time.
[0024]
Assuming application to an SDRAM, the semiconductor device further includes a plurality of memory cells in which data input from the data terminal is stored and the stored data can be output from the data terminal. In a data read operation, data read from a memory cell selected from the plurality of memory cells is latched by the latch circuit of the data output circuit and applied to the data terminal. In the data write operation, data latched in the latch circuit of the data input circuit from the plurality of data terminals is written into a memory cell selected from the plurality of memory cells.
[0025]
In particular, when applied to a DDR type SDRAM, the semiconductor device outputs a data strobe signal in synchronization with a timing signal for latching the latch circuit of the output circuit in response to a data read operation, and in response to a data write operation. An external signal terminal for inputting a data strobe signal for synchronizing a timing signal for latching the latch circuit of the input circuit is further provided as the interface terminal.
[0026]
[2] The second aspect of the present invention focuses on the transient response operation by the clocked inverter constituting the latch circuit on the interface circuit operated in parallel.
[0027]
In other words, paying attention to the input circuit arranged on the semiconductor chip, Above The input circuit is An input buffer circuit connected to the first interface terminal; and an input latch circuit connected to the input buffer circuit for performing a latch operation of the information; The input latch circuit is Above Input buffer circuit And an input gate connected to the input gate and a static latch connected to the input gate. The input gate includes a first clocked inverter that is activated and controlled by receiving a complementary clock signal having the same edge change timing, and the static latch receives the complementary clock signal and the first clocked inverter. Is configured to include a second clocked inverter that is activated and controlled in reverse phase.
[0028]
According to the above, since the complementary clock signals having the same edge change timing are used, the transient response in which both the first and second clocked inverters are inactivated due to the shift of the edge change timing. The period is shortened, and the period during which the input change is not reflected in the output during such a transient response period can be shortened. This helps to prevent the input data valid window from undesirably spreading.
[0029]
Paying attention to the output circuit arranged on the semiconductor chip, Above The output circuit is An output buffer circuit connected to the first interface terminal; and an input latch circuit connected to the output buffer circuit and performing a latch operation of information from a memory cell; The output latch circuit includes an input gate and an output having an input connected to the input gate. circuit And a static latch connected to the. At this time, the input gate is composed of a clocked inverter that is activated and controlled by receiving complementary clock signals having the same edge change timing.
[0030]
According to the above, since the complementary clock signal having the same edge change timing is used, the transient response period in which the clocked inverter is changed from the inactive state to the active state is shortened, which makes the output data valid window undesired. Helps reduce the narrowing situation.
[0031]
The complementary clock signal having the same edge change timing may be formed by a signal generation circuit on a semiconductor chip. The signal generation circuit includes a pair of differential amplifier circuits, and a clock terminal is commonly connected to one differential input terminal of the pair of differential amplifier circuits having different polarities, and the pair of differential amplifier circuits A reference voltage terminal is connected to the other differential input terminal having a different polarity from each other, and a complementary clock signal in which the edge change timing is aligned is output from the same polarity output node of the pair of differential amplifier circuits. is there.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
<Outline of DDR-SDRAM>
FIG. 1 shows a DDR-SDRAM as an example of a semiconductor device according to the present invention. The DDR-SDRAM shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known MOS semiconductor integrated circuit manufacturing technique.
[0033]
The DDR-SDRAM 1 is not particularly limited, and has four memory banks BNK0 to BNK3. Although not shown, each of the memory banks BNK0 to BNK3 is not particularly limited, but each has four memory mats, and each memory mat is constituted by two memory arrays. One memory array is assigned to a data storage area in which the least significant bit of the column address signal corresponds to the logical value “0”, and the other memory array has data of which the least significant bit of the column address signal corresponds to the logical value “1”. Allocated to storage area. The memory bank memory mat and the memory array partition structure are not limited to the above. Therefore, in this specification, unless otherwise noted, each memory bank is composed of one memory mat. explain.
[0034]
The memory mats of the respective memory banks BNK0 to BNK3 include dynamic memory cells MC arranged in a matrix, and according to the figure, the selection terminals of the memory cells MC arranged in the same column are word lines WL for each column. The data input / output terminals of the memory cells arranged in the same row are coupled to one bit line BL of the complementary bit lines BL and BL for each row. Although only a part of the word lines WL and the complementary bit lines BL are representatively shown in the figure, a large number are actually arranged in a matrix and have a folded bit line structure with a sense amplifier as the center. Yes.
[0035]
For each of the memory banks BNK0 to BNK3, row decoders RDEC0 to RDEC3, data input / output circuits DIO0 to DIO3, and column decoders CDEC0 to CDEC3 are provided.
[0036]
The word line WL of the memory mat is selected and driven to the selected level according to the decoding result of the row address signal by the row decoders RDEC0 to RDEC3 provided for the memory banks BNK0 to BNK3.
[0037]
The data input / output circuits DIO0 to DIO3 include a sense amplifier, a column selection circuit, and a write amplifier. The sense amplifier is an amplifying circuit that detects and amplifies a minute potential difference appearing on the complementary bit lines BL and BL by reading data from the memory cell MC. The column selection circuit is a switch circuit for selecting the complementary bit lines BL and BL to conduct to the input / output bus 2 such as a complementary common data line. The column selection circuit is selected according to the decoding result of the column address signal by the corresponding one of the column decoders CDEC0 to CDEC3. The write amplifier is a circuit that differentially amplifies the complementary bit lines BL and BL via the column switch circuit in accordance with write data.
[0038]
A data input circuit 3 and a data output circuit 4 are connected to the input / output bus 2. The data input circuit 3 receives externally supplied write data in the write mode and transmits it to the input / output bus 2. The data output circuit 4 inputs read data transmitted from the memory cell MC to the input / output bus 2 in the read mode and outputs the read data to the outside. Although the input terminal of the data input circuit 3 and the output terminal of the data output circuit 4 are not particularly limited, they are coupled to 16-bit data input / output terminals DQ0 to DQ15. For convenience, reference numerals DQ0 to DQ15 may be attached to the data that the SDRAM 1 inputs and outputs to the outside.
[0039]
Although not particularly limited, the DDR-SDRAM 1 has 15-bit address input terminals A0 to A14. Address input terminals A0-A14 are coupled to address buffer 5. Of the address information supplied to the address buffer 5 in a multiplexed form, the row address signals AX0 to AX12 are regarded as a row address latch 6 and the column address signals AY0 to AY11 are regarded as a bank selection signal as a bank selection signal. The select signals AX13 and AX14 are supplied to the bank selector 8 and the mode register setting information A0 to A14 are supplied to the mode register 9.
[0040]
The operation of the four memory banks BNK0 to BNK3 is selected by the bank selector 8 according to the logical values of the 2-bit bank selection signals AX13 and AX14. That is, only the memory bank whose operation is selected can be operated. For example, sense amplifiers, write amplifiers, column decoders and the like are not activated in memory banks whose operations are not selected.
[0041]
The row address signals AX0 to AX12 latched in the row address latch 6 are supplied to the row address decoders RDEC0 to RDEC3.
[0042]
Column address signals AY0 to AY11 latched in the column address latch 7 are preset in the column address counter 10 and supplied to the column address decoders CDEC0 to CDEC3. When burst access, which is continuous memory access, is instructed, the column address counter 10 is incremented by the number of consecutive times (the number of bursts), and a column address signal is generated internally.
[0043]
The refresh counter 11 is an address counter that itself generates a row address for refreshing stored information. When the refresh operation is instructed, the word line WL is selected according to the row address signal output from the refresh counter 11, and the stored information is refreshed.
[0044]
The control circuit 12 is not particularly limited, but the clock signals CLK and CLKb, the clock enable signal CKE, and the chip select signal CSb (suffix b means that the signal to which it is attached is a low enable signal or a level inverted signal. ), Predetermined information is input from the mode register 9 together with external control signals such as the column address strobe signal CASb, the row address strobe signal RASb, the write enable signal WEb, the data mask signals DMU and DML, and the data strobe signal DQS. The operation of the DDR-SDRAM 1 is determined by a command defined by a combination of the states of these input signals, and the control circuit 12 has control logic for forming an internal timing signal corresponding to the operation designated by the command.
[0045]
The clock signals CLK and CLKb are SDRAM master clocks, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK.
[0046]
The chip select signal CSb instructs the start of the command input cycle by its low level. When the chip select signal is at a high level (chip non-selected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.
[0047]
The RASb, CASb, and WEb signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle to be described later.
[0048]
The clock enable signal CKE is a control signal for the power-down mode and the self-refresh mode. In the power-down mode (which is also a data retention mode in the SDRAM), the clock enable signal CKE is set to a low level.
[0049]
The data mask signals DMU and DML are mask data in units of bytes with respect to the input write data. The high level of the data mask signal DMU instructs to inhibit writing by the upper bytes of the write data, and the high level of the data mask signal DML indicates the write data. Instructs write suppression by the lower byte of.
[0050]
The data strobe signal DQS is supplied from the outside as a write strobe signal during a write operation. That is, when a write operation is instructed in synchronization with the clock signal CLK, the supply of data synchronized with the data strobe signal DQS from the clock signal period after the clock signal period in which the instruction has been issued is defined. . During a read operation, the data strobe signal DQS is output to the outside as a read strobe signal. That is, in the data read operation, the data strobe signal changes in synchronization with the external output of the read data. For this purpose, a DLL (Delayed Lock Loop) circuit 13 and a DQS output buffer 14 are provided. In order to synchronize the clock signal CLK received by the semiconductor device 1 and the data output timing of the data output circuit 4, the DLL circuit 13 controls the data output operation control clock signal (control in phase with the data strobe signal DQS during the read operation). The phase of the clock signal 15 is adjusted. Although not particularly limited, the DLL circuit 13 reproduces the internal clock signal 15 that can compensate the signal propagation delay time characteristic of the internal circuit by the replica circuit technique and the phase synchronization technique. The data output circuit 4 that is operated to output data can output data at a timing that is reliably synchronized with the external clock signal CLK. The DQS buffer 14 outputs the data strobe signal DQS to the outside in phase with the internal clock signal 15.
[0051]
The row address signals (AX0 to AX12) are defined by the levels of address input terminals A0 to A12 in a later-described row address strobe / bank active command (active command) cycle synchronized with the rising edge of the clock signal CLK. In this active command cycle, the signals AX13 and AX14 input from the address input terminals A13 and A14 are regarded as bank selection signals. When A13 = A14 = “0”, the bank BNK0, A13 = “1”, A14 = “ When 0, bank BNK1, A13 = “0”, when A14 = “1”, bank BNK2, and when A13 = “1”, A14 = “1”, bank BNK3 are selected. The memory bank selected in this manner is subjected to data reading by a read command, data writing by a write command, and precharging by a precharge command.
[0052]
The column address signals (AY0 to AY11) are levels of the terminals A0 to A11 in a column address / read command (read command) cycle and a column address / write command (write command) cycle, which will be described later, synchronized with the rising edge of the clock signal CLK. Defined by The column address designated by this is used as the start address of burst access.
[0053]
In the DDR-SDRAM 1, although not particularly limited, the clock signal CLK, the inverted clock signal CLKb, the clock enable signal CKE, the chip selection signal CSb, the RAS signal RASb, the CAS signal CASb, the write enable signal WEb, and the address input signals A0 to A0. A14, an input buffer for receiving the data mask signals DMU and DML and the data strobe signal DQS, an interface for the data input buffer (input first stage buffer) of the data input circuit 3, and the data output buffer (output final stage buffer) of the data output circuit 4 Is based on, for example, the well-known SSTL2 (Class II) standard. In the SSTL2 standard, a level of 1.6 volts or higher which is 0.35 V or higher with respect to a reference potential (VREF) such as 1.25 volts is regarded as H level, and a level of 0.35 V or lower with respect to the reference potential. That is, a level of 0.90 volts or less is regarded as the L level. The external interface specification is not limited to SSTL2, and may be, for example, the SSTL3 standard.
[0054]
The DDR-SDRAM 1 is not particularly limited, but commands such as the following [1] to [9] are defined in advance.
[0055]
[1] The mode register set command is a command for setting the mode register 9. This command is specified by CSb, RASb, CASb, WEb = low level, and data to be set (register set data) is given via A0 to A14. The register set data is not particularly limited, but may be burst length, CAS latency, burst type, or the like. The settable burst length is not particularly limited, but is 2, 4, 8, and the settable CAS latency is not particularly limited, but is 2,2.5.
[0056]
The CAS latency designates how many cycles of the clock signal CLK are spent from the fall of CASb to the output operation of the data output circuit 4 in a read operation instructed by a column address / read command described later. An internal operation time for data reading is required until the read data is determined, and is used for setting it according to the frequency of use of the clock signal CLK. In other words, the CAS latency is set to a relatively large value when the clock signal CLK having a high frequency is used, and the CAS latency is set to a relatively small value when the clock signal CLK having a low frequency is used.
[0057]
[2] The row address strobe / bank active command is a command for validating the instruction of the row address strobe and the selection of the memory bank by A13 and A14. CSb, RASb = low level (“0”), CASb, WEb = Instructed by a high level (“1”), the address supplied to A0 to A12 at this time is used as a row address signal, and the signals supplied to A13 and A14 are taken in as memory bank selection signals. The capturing operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is specified, the word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are respectively conducted to the corresponding complementary data lines.
[0058]
[3] The column address / read command is a command necessary for starting a burst read operation and a command for giving a column address strobe instruction. CSb, CASb, = low level, RASb, WEb = high level At this time, the address supplied to A0 to A11 is taken in as a column address signal. The column address signal thus fetched is preset in the column address counter 10 as a burst start address. In the burst read operation instructed by this, the memory bank and the word line in the row address strobe / bank active command cycle are selected before that, and the memory cell of the selected word line receives the clock signal CLK. In accordance with the address signal output from the column address counter 10 in synchronism with each other, the memory bank sequentially selects, for example, in units of 32 bits, and continuously to the outside in units of 16 bits in synchronization with the rise and fall of the data strobe signal DQS. Is output. The number of data (words) to be read continuously is the number specified by the burst length. Further, data reading from the data output circuit 4 is started after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.
[0059]
[4] The column address / write command is a command necessary for starting the burst write operation when burst write is set in the mode register 9 as a mode of the write operation. Further, this command gives an instruction for column address strobe in burst write. The command is instructed by CSb, CASb, WEb, = low level, and RASb = high level. At this time, the address supplied to A0 to A11 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 10 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency setting in the write operation, and writing of the write data is started in synchronization with the data strobe signal DQS with a delay of one cycle of the clock signal CLK from the column address / write command cycle.
[0060]
[5] The precharge command is a command for starting a precharge operation for the memory bank selected by A13 and A14, and is designated by CSb, RASb, WEb, = low level, and CASb = high level.
[0061]
[6] The auto-refresh command is a command required to start auto-refresh, and is designated by CSb, RASb, CASb = low level, and WEb, CKE = high level. The refresh operation by this is the same as CBR refresh.
[0062]
[7] When the self-refresh entry command is set, the self-refresh function operates while CKE is at the low level, and during that time, refresh operation is automatically performed at a predetermined interval without giving a refresh instruction from the outside. Is done.
[0063]
[8] The burst stop command is a command necessary for stopping the burst read operation, and is ignored in the burst write operation. This command is indicated by CASb, WEb = low level and RASb, CASb = high level.
[0064]
[9] The no operation command is a command for instructing not to perform a substantial operation, and is designated by CSb = low level, RASb, CASb, WEb = high level.
[0065]
In the DDR-SDRAM 1, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle and a row address strobe / bank active command is supplied, The operation of the row address system in the other memory bank is made possible without affecting the operation in the other memory bank. That is, a row address system operation specified by a bank active command or the like and a column address system operation specified by a column address / write command or the like can be performed in parallel between different memory banks. Therefore, as long as data does not collide at the data input / output terminals DQ0 to DQ15, a precharge command for a memory bank different from the memory bank to be processed during execution of a command that has not been processed, It is possible to start the internal operation in advance by issuing a row address strobe / bank active command.
[0066]
As is clear from the above description, the DDR-SDRAM 1 is capable of data input / output synchronized with both rising and falling edges of the data strobe signal DQS synchronized with the clock signal CLK, and synchronized with the clock signal CLK. Since address and control signals can be input / output, a large-capacity memory similar to DRAM can be operated at a high speed comparable to SRAM, and several data can be accessed for one selected word line. By designating whether or not to be performed by the burst length, the built-in column address counter 10 sequentially switches the column system selection state, and a plurality of data can be read or written continuously.
[0067]
<Data input circuit>
FIG. 2 shows an example of the data input circuit 3 of the DDR-SDRAM 1. In the first stage, an input first stage buffer 20 of SSTL specification is arranged. The input first stage buffer 20 inputs write data supplied in synchronization with the rising and falling edges of the data strobe signal DQS. Although not shown, the input first-stage buffer 20 has a current mirror load, a data terminal is connected to the gate of one differential input MOS transistor, and a reference voltage is input to the gate of the other differential input MOS transistor. The active / inactive control is performed via a power switch MOS transistor that is switch-controlled by an enable signal DIEN.
[0068]
In the next stage of the differential input buffer 20, the serial path of the latch circuits 21A to 21C and the serial path of the latch circuits 21D and 21E are connected in parallel, and when the write operation is instructed, a half cycle of the data strobe signal DQS is performed. Data supplied in units is shifted by half a cycle and sequentially latched in the serial path of the latch circuits 21A to 21C and the serial path of the latch circuits 21D and 21E. As a result, the write data supplied in units of half cycles of the data strobe signal DQS is transmitted in parallel in units of one cycle of the data strobe signal DQS and transmitted to the subsequent stage. That is, each of the latch circuits 20A to 20E is configured by the clocked inverters CIV1 and CIV2 and the inverter IV, and is latch-controlled by the complementary clock signals DSCKT and DSCKB having the same edge change timing. Each of the clocked inverters CIV1 and CIV2 is constituted by a series circuit of p-channel MOS transistors Mp1 and Mp2 and n-channel MOS transistors Mn3 and Mn4 as illustrated in FIG. 3, and clock signals are supplied to the control terminals B and T. DSCKT and DSCKB are supplied, and as illustrated in FIG. 4, the latch circuits 21A, 21C, and 21E perform a latch operation in synchronization with the fall of the clock signal DSCKB, and the latch circuits 21B and 21D perform the rise of the clock signal DSCKT. A latch operation is performed in synchronization with the fall.
[0069]
FIG. 5 illustrates a circuit for generating the clock signals DSCKT and DSCKB. The signal generation circuit 22 is configured by mutually connecting input terminals having different polarities of a pair of differential amplifier circuits. That is, one differential amplifier circuit includes a current mirror load composed of p-channel MOS transistors Mp11 and Mp12, n-channel differential input MOS transistors Mn13 and Mn14, and an n-channel power switch MOS transistor Mn15. The gate of the MOS transistor Mn13 serves as an inverting input terminal, and the gate of the MOS transistor Mn14 serves as a non-inverting input terminal. The other differential amplifier circuit includes a current mirror load composed of p-channel MOS transistors Mp21 and Mp22, n-channel differential input MOS transistors Mn23 and Mn24, and an n-channel power switch MOS transistor Mn25. The gate of the MOS transistor Mn23 is an inverting input terminal, and the gate of the MOS transistor Mn24 is a non-inverting input terminal.
[0070]
A data strobe signal DQS is input to the gates of the differential input MOS transistors Mn13 and Mn24, and a reference voltage VREF is input to the gates of the differential input MOS transistors Mn14 and Mn23. The internal clock signals DSCLKT and DSCLKB at a level complementary to the data strobe signal DQS can be obtained from the CMOS inverters 51 and 52 connected to the single-ended output node.
[0071]
DSEN is an enable control signal for the signal generation circuit 22 and is supplied to the gates of the power switch MOS transistors Mn15 and MN25. The signal generation circuit 22 is activated by the high level of the enable control signal DSEN. In this active state, an operating current flows through the differential amplifier circuit, and immediately a minute potential difference from the signal level of the terminal DQS around the reference voltage VREF is amplified. Due to the differential amplification, the signal input operation from the terminal DQS is fast.
[0072]
As can be understood from the description of the data input circuit 3, in the DDR-SDRAM 1, write data is input from the outside in synchronization with both rising and falling of the data strobe signal DQS synchronized with the clock signal CLK. The write operation inside the DDR-SDRAM 1 is performed with the period of the clock signal CLK as a minimum unit.
[0073]
Next, the latch circuit 21A shown in FIG. 6 will be described in detail as a latch circuit controlled by a complementary clock signal having the same edge change timing. In FIG. 7A, when the latch circuit 21A in FIG. 6 latches data having a logical value “1”, in FIG. 7B, the latch circuit 21A similarly latches data having a logical value “0”. The operation timing is shown respectively. As apparent from FIG. 7, when the clock signals IT = 0 and IB = 1, the clocked inverter CIV1 is enabled for input operation, and the clocked inverter CIV2 is disabled for input operation. It goes through. On the other hand, when the clock signals IT = 1 and IB = 0, the clocked inverter CIV1 is disabled for input operation and the clocked inverter CIV2 is enabled for input operation, whereby the latch circuit 21A is in a latched state.
[0074]
7A and 7B, the latch circuit 21A changes from the through state to the latch state at time t3. When the input data D is inverted at time t0, the change is transmitted to the output Q at time t1 (operation delay times td1, td3), and reflected on the output of the inverter IV at time t2 (operation delay times td2, td4). ). Since the clock signals DSCKB and DSCKT (IT, IB) of the latch circuit 21A have the same clock edge, the first and second clocked inverters CIV1 and CIV2 are both deactivated due to a shift in edge change timing. The transient response period is substantially negligibly short, and there is substantially no period during which the change in input is not reflected in the output as in the comparative example described below. . Therefore, the setup time can be considered at the same timing in both cases of “1” data latch and “0” data latch.
[0075]
On the other hand, in the case of the latch circuit using the clock signals IT and IB having different edge change timings as illustrated in FIG. 8, the latch state is changed from the through state as shown in FIGS. When the transition is made, a transient response period of IT = 1 and IB = 1 occurs, and during this period, in the “1” data latch operation of (A), the change in the input D is reflected in the output Q even during the transient response period. However, in the “0” data latch operation in (B), the change in the input D during the transient response period is not reflected in the output Q, and there is a possibility of being missed. Therefore, in the case of (A), the setup time S1 is considered based on the time tI1 at which the latch state of the latch circuit is achieved, and in the case of (B), the time tI0 at which the change of the through state of the latch circuit is started. The setup time S3 must be considered as a reference. In such a case, it is practically impossible to use different setup times according to the logical value of the latch data, and the longer setup time must be adopted uniformly, resulting in high-speed operation. It becomes difficult to respond to. On the other hand, if a latch circuit using complementary clock signals with uniform edge changes as described with reference to FIG. 6 is adopted, it is easy to cope with high-speed operation. The same applies to the other latch circuits shown in FIG.
[0076]
<Data output circuit>
FIG. 10 shows an example of the data output circuit 4 of the DDR-SDRAM 1. Data RDAT and FDAT are read in parallel from the active memory bank in the data read operation. This read operation is performed in cycle units in synchronization with the clock signal CLK. One data RDAT is transmitted to the serial path of the latch circuits 30A, 30B, and the other data FDAT is transmitted to the serial path of the latch circuits 30C, 30D, 30E. One final stage latch circuit 30B is connected to an inverter 32 via an output gate 31A composed of a clocked inverter and reaches the output buffer 33, and the other final stage latch circuit 30E includes an output gate 31B composed of a clocked inverter. To the output buffer 33 through the inverter 32.
[0077]
The latch circuits 30A and 30C latch the input in synchronization with the clock signal L1CK, and the latch circuit 30D latches the output of the latch circuit 30C in synchronization with the clock signal L2CK. The clock signals L1CK and L2CK are internal clock signals synchronized with complementary clock signals ICKT and ICKB, which will be described later, generated based on the clock signals CLK and CLKb. Data RDAT and FDAT read in parallel from the memory bank in synchronization with the cycle of the clock signal CLK are latched in the latch circuits 30A and 30C in synchronization with the clock signal CLK (ICKT), and the latch data of the latch circuit 30C. FL1D is latched by the latch circuit 30D in synchronization with the clock signal CLKb (ICKB).
[0078]
The latch circuits 30A to 30D can adopt the master / slave logic illustrated in FIG. The master stage and the slave stage are constituted by clocked inverters CIV1 and CIV2 and an inverter IV, respectively. The clocked inverters CIV1 and CIV2 have the circuit configuration of FIG.
[0079]
The circuit for generating the clock signals ICKT and ICKB has the same configuration as the input buffer for the data strobe signal DQS in FIG. 5, as illustrated in FIG. However, the inverted clock signal CLKb is used instead of the reference voltage VREF. In FIG. 12, Mp16, Mp17, Mp26, and Mp27 are p-channel MOS transistors. Mn18, Mn19, Mn20, Mn28, Mn29, and Mn30 are n-channel MOS transistors. CKEN is an activation control signal. The L1CK and L2CK are clock signals synchronized with the clock signals ICKT and ICKB.
[0080]
The latch circuits 30B and 30E shown in FIG. 10 are constituted by clocked inverters CIV1 and CIN2 and an inverter IV, and one of them is in a through state and the other is in a latched state in synchronization with clock signals L3CKT and L3CKB. Be controlled. The output gates 31A and 31B are operated in synchronization with the clock signals L3CKT and L3CKB, and those connected to the subsequent stage of the latch circuit 30B or 30E in the latched state are enabled to operate, and connected to the subsequent stage of the latch circuit 30B or 30E in the through state. What is to be controlled is in a high impedance state.
[0081]
The clock signals L3CKT and L3CKB are timing signals generated by the DLL circuit 13 performing a predetermined delay adjustment on the clock signals ICKT and ICKB as shown in FIG. In this delay adjustment, the data output timing which is alternately selected by the output gates 31A and 31B and appears at the data terminal DQj via the inverter 32 and the output buffer 33 in synchronization with the clock signals ICKT and ICKB is changed to the edge of the data strobe signal DQS. This is a process for setting a delay time necessary to synchronize with the change timing.
[0082]
As illustrated in FIG. 13, the output buffer 33 has a CMOS inverter at the final stage using a power supply voltage VDDQ that conforms to the SSTL2 interface specification as an operation power supply. The CMOS inverter is activated and controlled by an output enable signal DOEN via a NAND gate NAND and a NOR gate NOR. When the output enable signal DOEN is at a high level, the output operation is enabled according to data DATA, and when the output enable signal DOEN is at a low level. Controlled to a high output impedance state.
[0083]
FIG. 14 illustrates the output operation timing of the output circuit of FIG. As can be understood from the description of the data output circuit 4, the data read operation in the DDR-SDRAM 1 is performed with the cycle of the clock signal CLK as a minimum unit, and the data read by this operation becomes the clock signal CLK. The data is output from the data terminal DQj in synchronization with both rising and falling of the data strobe signal DQS to be synchronized.
[0084]
Next, the details of the latch circuit 30B of FIG. 15 will be described as an output latch circuit that is latch-controlled by complementary clock signals having the same edge change timing. The locked inverters CIV1 and CIV2 in FIG. 15 have the same circuit configuration as that in FIG.
[0085]
In FIG. 16A, when the latch circuit 30B in FIG. 15 latches data having a logical value “1”, in FIG. 16B, the latch circuit 30B similarly latches data having a logical value “0”. The operation timing is shown respectively. As is apparent from FIG. 16, when the clock signals OT = 0 and OB = 1, the clocked inverter CIV1 is disabled for input operation, and the clocked inverter CIV2 is enabled for input operation. Latched. On the other hand, when the clock signals OT = 1 and OB = 0, the clocked inverter CIV1 is enabled for input operation and the clocked inverter CIV2 is disabled for input operation, whereby the latch circuit 30B enters the through state.
[0086]
In FIGS. 16A and 16B, the latch circuit 30B transitions from the latch state to the through state at time t0. Data I is determined before time t0. Therefore, when the latch circuit 30B is changed from the latched state to the through state at time t0, the output O is determined after the operation delay time tdo1 has elapsed in the case of “1” data output, and in the case of “0” data output. The output O is determined after the operation delay time tdo0 has elapsed. Since the clock signals L3CKT and L3CKB (OT, OB) of the latch circuit 30B have the same clock edge, the transient response period during which the first clocked inverter CIV1 is deactivated due to the shift of the edge change timing is It is substantially negligibly short, and there is substantially no period during which the change in the input is not reflected in the output in such a transient response period as in the comparative example described below. Therefore, the output timing as viewed from t0 is the same for both the output of “1” data and the output of “0” data.
[0087]
In contrast, in the case of a latch circuit using clock signals OT and OB having different edge change timings as illustrated in FIG. 17, as shown in FIGS. 18A and 18B, the latch state is changed to the through state. When the transition is made, a transient response period of IT = 1 and IB = 1 occurs, and during this period, in the “0” data output operation of (B), the change in data I is reflected in the output O even during the transient response period. However, in the “1” data latch operation of (A), the change in the data I during the transient response period is not reflected in the output O. Therefore, the output timing with respect to time t0 is tOd0 + tdo1 in the case of “1” data output, and tdo0 in the case of “0” data output. Thus, if the output timing differs according to the logical value of the output data, the period during which all the bits that are output in parallel are valid is shortened, and as a result, it becomes difficult to cope with high-speed operation. End up. On the other hand, if a latch circuit using complementary clock signals with uniform edge changes is employed as described with reference to FIG. 15, it is easy to cope with high-speed operation. The same applies to the other latch circuits shown in FIG.
[0088]
<Interface circuit layout>
FIG. 19 shows a chip appearance of the DDR-SDRAM 1. A large number of bonding pads 42 are arranged in a control system circuit area 41 assigned to the central portion of the semiconductor chip 40, and a power supply system control circuit 43, an address system control circuit 44, a command system control circuit 45, an input / output control. A circuit 46 and a power supply system control circuit 47 are provided. The memory banks BNK0 to BNK3 are formed outside the control system circuit area 41. The power supply system control circuits 43 and 47 include circuits for forming a word line drive voltage, a substrate bias voltage, and the like based on the power supply voltage VDD. The address system control circuit 44 includes the address latches 6 and 7 and the column address counter 10. The command system control circuit 45 includes logic for controlling the operation mode based on command system signals such as CSb, RASb, CASb, WEb in the control circuit 12. The input / output control circuit 46 includes a signal input / output control circuit represented by the data input circuit 3 and the data output circuit 4. The large number of bonding pads 42 are classified into an address system, a command system, and a data system, and are arranged together.
[0089]
FIG. 20 illustrates the package appearance of the DDR-SDRAM 1, particularly the arrangement of external connection terminals such as lead pins of the package. In FIG. 20, pins indicated by NC are unused terminals. In the figure, the data strobe signal is divided into DQSU and DQSL. In the above description, the data strobe signal DQS has been representatively described. However, in practice, different data strobe signals are allocated to the upper byte data terminals DQ15 to DQ8 and the lower byte data terminals DQ7 to DQ0, respectively. Because it is. Reference numerals of the data terminals DQ15 to DQ10 are also indicated as DQF to DQA.
[0090]
FIG. 21 shows a specific layout configuration of the input / output control circuit 46. A corresponding external terminal name is appended to the bonding pad 42, such as DQ0.
[0091]
The input / output control circuit 46 includes data strobe signal output circuits QSU, QSL formed in the unit region L1 as interface circuits, and data output circuits O8, O7, O9, O6, OA, O5, OB formed in the unit region L2. Column (data output circuit column OAL), mask data input circuits MU, ML formed in the unit region L3, columns of data input circuits I8, I7, I9, I6, IA, I5, IB formed in the unit region L4 ( Data input circuit array IAL), data strobe signal input circuits DSU, DSL formed in the unit region L5, data input circuits I4, IC, I3, ID, I2, IE, I1, IF, I0 formed in the unit region L4 (Data input circuit array IAR), data output circuits O4, OC, O3, OD, O2, OE, O1, OF formed in the unit region L2, Having 0 column (data output circuit array OAR).
[0092]
The data output circuit and the data input circuit are commonly connected to corresponding data terminals. For example, the data output circuit O0 is connected to the corresponding data terminal DQ0 by the data line W5, and the data input circuit I0 is connected to the corresponding data terminal DQ0 by the data line W4. A data strobe signal output circuit and a data strobe signal input circuit are also connected to corresponding data strobe terminals. For example, the data strobe signal output circuit QSU is connected to the corresponding data strobe terminal DQSU via a wiring W2, and the data strobe signal input circuit DSU is connected to the corresponding data strobe terminal DQSU via a wiring W3. In FIG. 21, the mask data input circuit MU is connected to the corresponding terminal DMU via a wiring W1. Other circuits whose wiring is not shown are similarly connected to corresponding terminals.
[0093]
Although not shown in particular, the interface signal wiring such as W5 and W4 for connecting the data output circuit and the data input circuit to the corresponding data terminals, at least the interface circuit such as the data output circuit string and the data input circuit string, respectively. If a common delay component (time constant) that matches the delay time of the path that requires the longest delay time is set for the interface signal wiring in the group, the input data valid window and the It is possible to easily reduce the situation where the output data valid window is adversely affected.
[0094]
The unit area L2 includes a unit bit configuration of the data output circuit 4 shown in FIG. At this time, the final output stage buffer 33 may be disposed in the vicinity of the corresponding bonding pad 42. The unit storage area L4 includes the unit bit configuration of the data input circuit 3 shown in FIG. At this time, the first-stage buffer 20 may be disposed in the vicinity of the corresponding bonding pad 42. The unit storage area L5 includes the unit bit structure of the input buffer 22 shown in FIG.
[0095]
As is apparent from the arrangement of the interface circuit in FIG. 21, the data output circuit for outputting data in parallel is divided into left and right data output circuit rows OAL and OAR, and the data input circuit for inputting data in parallel is data The input circuit arrays IAL and IAR are divided into left and right parts.
[0096]
W7 shown along the data input circuit arrays IAL and IAR is a timing at which the timing signals DSCKT and DSCKB (see FIG. 2) are sequentially transmitted in series to the input circuits formed in the respective unit regions L4. Control wiring. Timing signals DSCKT and DSCKB (see FIG. 2) are propagated from one to the left and right timing control wiring W7 via the clock driver B2. FIG. 22 shows the data input circuit rows IAL and IAR extracted.
[0097]
FIG. 23 shows the data input operation timing by the data input circuit arrays IAL and IAR. After passing through the clock driver B2, the timing control signals DSCKT and DSCKB have different propagation delays on the timing control wiring W7 between the far end and the near end of the clock driver B2. In order for each data input circuit to ensure the necessary setup time ts1 and hold time ht1 with respect to the change points of the timing control signals DSCKT and DSCKB transmitted to the respective data input circuits, the setup of all the input circuits is performed. At least parallel input data must be determined in the time range of the input data valid window tiw1, which is a time range including the time and the hold time. At this time, the data input circuit array is divided into IAL and IAR, and timing control signals DSCKT and DSCKB are propagated for each of the data input circuit arrays IAL and IAR. Further, individual data input circuits are provided in the data input circuit arrays IAL and IAR. The time range of the input data valid window tiw1 is narrower than the case where the data input circuit row is not divided or the case where the data input circuit is arranged next to the data output circuit sequentially, because the data input circuit is not divided. Become.
[0098]
As a comparative example, FIG. 26 shows a layout in which the data input circuit array is not divided as described above and the data input circuits in the region L4 are sequentially arranged adjacent to the data output circuits in the region L2. In this case, as apparent from FIG. 27 in which the data input circuit row portion is extracted, the timing control wiring W7 becomes long. Therefore, as shown in FIG. 28 showing the data input operation timing of the data input circuit row, the propagation delay at the far end and the near end of the clock driver B2 on the timing control wiring W7 becomes large, and the input is made accordingly. The time range of the data valid window tiw2 is also expanded.
[0099]
Therefore, by adopting the layout of FIG. 21, the input data valid window becomes small, and it becomes easy to cope with the increase in the operation speed of the DDR-SDRAM 1.
[0100]
In FIG. 21, W6 shown along the data output circuit rows OAL and OAR is sequentially connected to the output circuit formed in each unit region L2 in series with the timing signals L3CKT and L3CKB (see FIG. 10). Is a timing control wiring for transmitting. Timing signals L3CKT and L3CKB are propagated from one side to the left and right timing control wiring W6 via the clock driver B1. In FIG. 24, the data output circuit rows OAL and OAR are extracted and shown. The path lengths for transmitting the timing signals L3CKT and L3CKB to the clock drivers B1 of the data output circuit arrays OAL and OAR are different. The driver CD1 assigned to the wiring LN1 with a long propagation path has a larger driving capability than the driver CD2 assigned to the wiring LN2 with a short propagation path, and the timing signals L3CKT and L3CKB supplied to the respective clock drivers B1 are large. There is no skew.
[0101]
FIG. 25 shows data output operation timings by the data output circuit arrays OAL and OAR. The timing control signals L3CKT and L3CKB are different in signal propagation delay between the wirings LN1 and LN2, and after passing through the clock driver B1, signals are transmitted at the far and near ends of the clock driver B1 on the timing control wiring W6. There is a difference in propagation delay. In FIG. 25, the difference in delay time is represented by tcd0, tcd1, tcd2, and tcd3. Output data appears at the data terminal after a time to2 with respect to the change point of the timing control signals L3CKT and L3CKB propagated to the respective data output circuits. The time range in which the output data from the data output circuit is determined at all data terminals is the time range of the output data valid window tow1. At this time, the data output circuit array is divided into OAL and OAR, and timing control signals L3CKT and L3CKB are propagated for each of the data output circuit arrays OAL and OAR. Further, individual data output circuits are provided in the data output circuit arrays OAL and OAR. Since the data output circuit train is not divided, the time range of the output data valid window tow1 is wider than when the data output circuit array is not divided or when the data output circuit is sequentially arranged adjacent to the data input circuit. Become.
[0102]
FIG. 26 shows, as a comparative example, a layout in which the data output circuit array is not divided as described above and the data input circuits in the region L4 are sequentially arranged adjacent to the data output circuits in the region L2. In this case, as is clear from FIG. 29 in which the portion of the data output circuit row is extracted, the timing control wiring W6 becomes long. Therefore, as apparent from FIG. 30 showing the data output operation timing of the data output circuit array, the propagation delay at the far end and the near end of the clock driver B1 on the timing control wiring W6 becomes large, and the output data is accordingly increased. The time range of the valid window tow2 is also narrowed.
[0103]
Therefore, by adopting the layout of FIG. 21, the output data valid window is widened, and it is easy to cope with the increase in the operation speed of the DDR-SDRAM 1.
[0104]
31 to 38 illustrate other layout configurations such as a data input circuit row and a data output circuit row. As shown in FIG. 31, the data output circuit rows OAL and OAR may be arranged in the center of the area of the input / output control circuit 46. As shown in FIG. 32, the clock drivers B1 of the data output circuit arrays OAL and OAR may be arranged close to the center. As shown in FIGS. 33 and 34, the data input circuit arrays IAL and IAR may be adjacent to each other, and the data output circuit arrays OAL and OAR may be adjacent to each other. Further, as illustrated in FIGS. 35 and 36, in the area of the input / output control circuit 46, the data output circuit arrays 100 to 104 and the data input circuit arrays 105 to 108 are arranged separately in the vertical direction. Is also possible. Furthermore, as illustrated in FIG. 37, the data output circuit array OAL and the data input circuit array IAL may be adjacent to each other, and the data output circuit array OAR and the data input circuit array IAR may be adjacent to each other. Similarly, as illustrated in FIG. 38, the data output circuit array OAL and the data input circuit array IALa may be adjacent to each other, and the data output circuit array OAR and the data input circuit array IARa may be adjacent to each other.
[0105]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0106]
For example, the grouping for the interface circuits that are operated in parallel output operation or parallel input operation is not limited to the two divisions described above, and may be more than that. The number of data input / output terminals of the SDRAM is not limited to 16 bits, and may be 8 bits, 4 bits, or the like. Also, the number of memory banks of the SDRAM, the memory mats of the memory banks, and the configuration of the memory array are not limited to the above and can be changed as appropriate.
[0107]
Further, the data output circuit and the data input circuit constituting the interface circuit are not limited to the above configuration. In addition, when the interface circuit includes a buffer circuit and a latch circuit, the buffer circuit and the latch circuit may be arranged separately. In this case, at least the latch circuit is a target of grouping.
[0108]
In the above description, the case where the invention made mainly by the inventor is applied to the DDR-SDRAM, which is the field of use behind the present invention, has been described. The present invention can be widely applied to a semiconductor device called a microcomputer, a system LSI, an accelerator, or the like on-chip a memory, a DDR-SDRAM or the like.
[0109]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0110]
That is, a plurality of interface circuits that are interfaced with the outside in parallel are divided into a plurality of groups, and timing signals for controlling the interface operation are supplied in series from the timing control lines to the interface circuits of each group in units of groups. Compared to the case where a plurality of interface circuits used for parallel interface with the outside are not grouped together and the timing signal is supplied in series with a common timing control wiring, the timing at the base end and end of the timing control wiring The difference (skew) in signal propagation delay can be reduced. As a result, variation in data input timing in a plurality of data input circuits to which data is input in parallel and variation in data output timing in a plurality of data output circuits that output data in parallel are Can be distributed. In short, the skew of the timing signal can be reduced for each group. As a result, the input data valid window can be made smaller and the output data valid window can be made larger than when no grouping is performed.
[0111]
As the interface circuits of each group are concentrated and arranged for each group, the difference in the propagation delay of the timing signal between the base end and the end of the timing control wiring in the group becomes smaller, and the timing signal skew in the group becomes smaller. can do.
[0112]
The clocked inverter constituting the latch circuit on the interface circuit operated in parallel is activated / deactivated using a complementary clock signal having the same edge change timing. By adopting such a clocked inverter in the input stage and latch stage of the data input latch circuit, a transient response period in which both clocked inverters are deactivated due to a shift in edge change timing. And the period during which the input change is not reflected in the output during such a transient response period can be shortened. As a result, it is possible to prevent the input data valid window from undesirably spreading.
[0113]
If the clocked inverter is used as the input gate of the data output latch circuit, a complementary clock signal having the same edge change timing is used, so that the transient response period in which the clocked inverter is changed from the inactive state to the active state is short. Thus, it is possible to suppress the situation where the output data valid window becomes undesirably narrow.
[Brief description of the drawings]
FIG. 1 is a block diagram of a DDR-SDRAM which is an example of a semiconductor device according to the present invention.
FIG. 2 is a circuit diagram showing an example of a data input circuit of a DDR-SDRAM.
FIG. 3 is a circuit diagram illustrating a clocked inverter.
FIG. 4 is a timing chart illustrating the operation timing of the data input circuit.
FIG. 5 is a circuit diagram illustrating a circuit for generating clock signals DSCKT and DSCKB.
FIG. 6 is a circuit diagram illustrating an input latch circuit that is latch-controlled by a complementary clock signal in which edge change timings are aligned.
7A shows an operation when the latch circuit of FIG. 6 latches data having a logical value “1”, and FIG. 7 similarly shows an operation when the latch circuit of FIG. 6 latches data having a logical value “0”. It is a timing chart respectively shown in B).
FIG. 8 is a circuit diagram showing, as a comparative example, a latch circuit using clock signals IT and IB having different edge change timings.
9A shows an operation when the latch circuit of FIG. 8 latches data having a logical value “1”, and FIG. 9 similarly shows an operation when the latch circuit of FIG. 8 latches data having a logical value “0”. It is a timing chart respectively shown in B).
FIG. 10 is a circuit diagram showing an example of a data output circuit of a DDR-SDRAM.
FIG. 11 is a circuit diagram illustrating a master / slave latch circuit included in the data output circuit;
FIG. 12 is a circuit diagram illustrating a circuit for generating clock signals ICKT and ICKB.
FIG. 13 is a logic circuit diagram illustrating an output buffer of a data output circuit.
FIG. 14 is a timing chart showing output operation timing of the data output circuit.
FIG. 15 is a circuit diagram illustrating an output latch circuit that is latch-controlled by a complementary clock signal in which edge change timings are aligned.
16A shows an operation when the latch circuit of FIG. 15 latches data having a logical value “1”, and FIG. 16 similarly shows an operation when the latch circuit of FIG. 15 latches data having a logical value “0”. It is a timing chart respectively shown in B).
FIG. 17 is an explanatory diagram showing a latch circuit using clock signals OT and OB having different edge change timings as a comparative example;
18A shows an operation when the latch circuit of FIG. 17 latches data having a logical value “1”, and FIG. 18 similarly shows an operation when the latch circuit of FIG. 17 latches data having a logical value “0”. It is a timing chart respectively shown in B).
FIG. 19 is a plan view showing a chip appearance of the DDR-SDRAM 1;
20 is a plan view illustrating the arrangement of external connection terminals such as lead pins of a package of DDR-SDRAM 1; FIG.
FIG. 21 is a plan view illustrating a first layout configuration of an input / output control circuit of a DDR-SDRAM;
22 is an explanatory view showing a portion of the data input circuit row extracted from FIG. 21. FIG.
FIG. 23 is a timing chart illustrating the data input operation timing by the data input circuit array in FIG. 22;
24 is an explanatory diagram showing a portion of the data output circuit row extracted from FIG. 21. FIG.
25 is a timing chart illustrating the data output operation timing by the data output circuit array of FIG. 24. FIG.
FIG. 26 is a plan view illustrating a layout in which a data input circuit array is not divided and sequentially arranged adjacent to a data output circuit as a comparative example;
FIG. 27 is an explanatory diagram in which a portion of a data input circuit row is extracted from FIG.
28 is a timing chart illustrating the data input operation timing of the data input circuit array in FIG. 27;
29 is an explanatory diagram in which a portion of a data output circuit array is extracted from FIG.
30 is a timing chart showing data output operation timing of the data output circuit array in FIG. 29;
FIG. 31 is a plan view illustrating a second layout configuration of the input / output control circuit of the DDR-SDRAM;
FIG. 32 is a plan view illustrating a third layout configuration of the input / output control circuit of the DDR-SDRAM;
FIG. 33 is a plan view illustrating a fourth layout configuration of the input / output control circuit of the DDR-SDRAM;
FIG. 34 is a plan view illustrating a fifth layout configuration of an input / output control circuit of a DDR-SDRAM;
FIG. 35 is a plan view illustrating a sixth layout configuration of an input / output control circuit of a DDR-SDRAM;
FIG. 36 is a plan view illustrating a seventh layout configuration of the input / output control circuit of the DDR-SDRAM;
FIG. 37 is a plan view illustrating an eighth layout configuration of an input / output control circuit of a DDR-SDRAM;
FIG. 38 is a plan view illustrating a ninth layout configuration of the input / output control circuit of the DDR-SDRAM;
[Explanation of symbols]
1 DDR-SDRAM
BNK0 to BNK3 memory bank
MC memory cell
WL Word line
BL bit line
DIO0 to DIO3 data input / output circuit
RDEC0 to RDEC3 row decoder
CDEC0 to CDEC3 column decoder
2 I / O bus
3 Data input circuit
4 Data output circuit
DQ0 to DQ15 Data input / output terminals
A0 to A14 Address input terminal
5 Address buffer
6 Row address latch
7 Column address latch
8 Bank selector
9 Mode register
10 column address counter
12 Control circuit
20 input first stage buffer
21A-21E Latch circuit
CLK, CLKb Clock signal
DQS data strobe signal
CIV1, CIV2 clocked inverter
IV inverter
DSCKT, DSCKB Complementary clock signal
30A-30E Latch circuit
L3CKT, L3CKB Complementary clock signal
33 Output final stage buffer
41 Control system circuit area
46 I / O control circuit
OAL, OAR data output circuit line
IAL, IAR data input circuit line
W6, W7 Timing control line
B1, B2 driver

Claims (6)

A plurality of first interface terminals for interfacing a plurality of bits of information in parallel with the outside, wherein a plurality of first interface terminals through which the corresponding information is input / output via the first interface terminals 1 interface terminal;
A plurality of interface circuits provided corresponding to each of the plurality of first interface terminals, each having a plurality of first interface circuits each having an input circuit and an output circuit;
A plurality of second interface terminals for interfacing a plurality of bits of information to the outside in parallel, wherein a plurality of second interface terminals through which the corresponding information is input / output via the second interface terminals; Two interface terminals;
A plurality of second interface circuits provided corresponding to each of the plurality of second interface terminals, each including a plurality of second interface circuits each having an input circuit and an output circuit. only contains the chip,
The plurality of first interface circuits are arranged separately in a first input circuit group in which the input circuits are grouped and a first output circuit group in which the output circuits are grouped. A group is connected to a first timing control wiring that supplies a timing signal for controlling an interface operation in series in a group unit.
The plurality of second interface circuits are arranged separately in a second input circuit group in which the respective input circuits are grouped and a second output circuit group in which the respective output circuits are grouped. The group is connected to a second timing control wiring that supplies a timing signal for controlling the interface operation in series in a group unit.
The first and second output circuit (or input circuit) groups are arranged between the first input circuit (or output circuit) group and the second input circuit (or output circuit) group. , semi-conductor device you wherein a. A plurality of first interface terminals for interfacing a plurality of bits of information in parallel with the outside, wherein a plurality of first interface terminals through which the corresponding information is input / output via the first interface terminals 1 interface terminal;
A plurality of interface circuits provided corresponding to each of the plurality of first interface terminals, each having a plurality of first interface circuits each having an input circuit and an output circuit;
A plurality of second interface terminals for interfacing a plurality of bits of information to the outside in parallel, wherein a plurality of second interface terminals through which the corresponding information is input / output via the second interface terminals; Two interface terminals;
A plurality of second interface circuits provided corresponding to each of the plurality of second interface terminals, each including a plurality of second interface circuits each having an input circuit and an output circuit. only contains the chip,
The plurality of first interface circuits are arranged separately in a first input circuit group in which the input circuits are grouped and a first output circuit group in which the output circuits are grouped. A group is connected to a first timing control wiring that supplies a timing signal for controlling an interface operation in series in a group unit.
The plurality of second interface circuits are arranged separately in a second input circuit group in which the respective input circuits are grouped and a second output circuit group in which the respective output circuits are grouped. The group is connected to a second timing control wiring that supplies a timing signal for controlling the interface operation in series in a group unit.
The first and the second input circuit group is arranged close, and the first to the near and the second output circuit group are disposed close, semiconductors devices you wherein a. The first interface circuit includes a buffer circuit connected to the corresponding first interface terminal;
A latch circuit connected to the corresponding buffer circuit and performing a latching operation of information to be interfaced,
3. The semiconductor device according to claim 2, wherein the timing signal is a latch control signal of the latch circuit. 4. The semiconductor device according to claim 3 , wherein the interface signal wiring connecting the buffer circuit and the interface terminal has a delay component substantially equal in at least each of the groups. A plurality of memory cells for storing data input from the first interface terminal and enabling the stored data to be output from the first interface terminal;
In a data read operation, data read from a memory cell selected from the plurality of memory cells is latched by a latch circuit of the output circuit and applied to the first interface terminal,
In the data write operation, data latched in the latch circuit of the input circuit from the plurality of first interface terminals is written into a memory cell selected from the plurality of memory cells. The semiconductor device according to claim 3 . In response to a data read operation, a data strobe signal is output in synchronization with a timing signal for latching the output circuit.
An external signal terminal for inputting a data strobe signal for synchronizing a timing signal for latching the latch circuit of the input circuit in response to a data write operation is further provided as the interface terminal. Item 6. A semiconductor device according to Item 5 .

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