JPH05102812A - Complementary signal generating circuit - Google Patents

Abstract

PURPOSE:To output a complementary signal in the same timing with respect to an input signal by inputting the input signal to input terminals of two differential amplifiers having the same configuration whose input terminals have mutally opposite phases. CONSTITUTION:An input signal 13 is inputted to the positive input of a 1st differential amplifier 11 and the negative input terminal of a 2nd differential amplifier 12 and an intermediate voltage between the input signal 13 is applied as a reference voltage 14. When the gain of the differential amplifier is considered to be infinite and the voltage at the positive input terminal is higher than the voltage at the negative input terminal, a high level is outputted and when lower, a low level is outputted. When the input signal 13 is changed from a voltage lower than the reference voltage 14 to a high voltage, the output of the 1st differential amplifier 11 is changed from a low level to a high level and the output of the 2nd differential amplifier is changed from the high level to the low level. When the input signal 13 is changed from the high to the low level with respect to the reference voltage 14, the outputs of the differential amplifiers 11, 12 are changed reversely to it. Thus, a complementary signal is outputted in the same timing with respect to one input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital LSI such as a microprocessor and an analog LS such as an AD converter.
It is a complementary signal generating circuit used in I.

[0002]

2. Description of the Related Art In a CMOS logic circuit, one signal may be used as it is as an output or as an inverted output. For example, it is a control signal of a transfer gate composed of an N-channel transistor and a P-channel transistor. As an example, FIG. 4 shows a circuit for sampling the input voltage before AD conversion. In FIG. 4, 41 is an N-channel transistor, 42 is a P-channel transistor, 43 is a capacitor, 44 is an input signal, 45 is a first control signal, 4 is a
6 is a second control signal. A high voltage is input to the first control signal 45, and a low voltage is input to the second control signal 46 to capture the input signal 44 in the capacitor 43. Next, a low voltage is input to the gate of the N-channel transistor 41, a high voltage is input to the gate of the P-channel transistor 42, the input voltage and the capacitor 43 are separated, and with respect to the voltage stored in the capacitor 43, AD
Do the conversion. In this way, the complementary control signals that are mutually inverted are input as the first control signal 45 and the second control signal 46 to control the operation.

Conventionally, complementary signals have been generated as shown in FIG. In FIG. 5, reference numeral 51 is a first inverter, 52 is a second inverter, and 53 is a third inverter. The input signal 54 is input to the first inverter 51, and the output of the first inverter 51 is input to the second inverter 52. In addition, the input signal is
Input to the inverter 53. The output of the second inverter 52 is the positive signal 55, and the output of the third inverter 53 is the negative signal 56.
That is, the complementary signal is generated by using the result obtained through the two-stage inverter as the positive signal 55 and the result obtained through the one-stage inverter as the negative signal 56.

[0004]

However, in the method as shown in FIG. 5, a two-stage inverter is used to obtain the complementary positive signal 55 and a one-stage inverter is used to obtain the negative signal 56. Therefore, a difference occurs in the delay time. As a result,
In the case of the above example, an error occurs in the data when the input signal 44 is taken into the capacitor 43, and an electric charge leaks when the input signal 44 and the capacitor 43 are separated, causing an error in the signal value.

In order to suppress such a phenomenon, the present invention provides
An object of the present invention is to provide a complementary signal generation circuit that outputs complementary signals at the same timing with respect to one input signal.

[0006]

A complementary signal generating circuit of the present invention is a complementary signal generating circuit for generating a positive output and a negative output with respect to one input signal, wherein the input signal is referred to as a positive input. A first differential amplifier for inputting a voltage to the negative input,
A second differential amplifier for inputting the input signal to a negative input and the reference voltage to a positive input, wherein an output of the first differential amplifier is a positive signal, and an output of the second differential amplifier Is a negative signal.

[0007]

According to the present invention, since the input signals are input to the mutually opposite input terminals of two identical differential amplifiers, complementary signals are output at the same timing with respect to the input signals.

[0008]

1 is a block diagram of a complementary signal generating circuit according to an embodiment. In FIG. 1, 11 is a first differential amplifier, 12 is a second differential amplifier, 13 is an input signal, 14
Is a reference voltage, 15 is a positive signal, and 16 is a negative signal.

The operation will be described below with reference to FIG. The input signal 13 is input to the positive input of the first differential amplifier 11 and the negative input of the second differential amplifier 12, and a voltage intermediate the amplitude of the input signal 13 is applied as the reference voltage 14. Considering the gain of the differential amplifier as infinite, it outputs a high level when the positive input voltage is higher than the negative input voltage, and outputs a low level when the positive input voltage is lower than the negative input voltage. To do. At this time, depending on the voltage values of the input signal 13 and the reference signal 14, the first differential amplifier 11 and the second differential amplifier 1
The output value of 2 is as shown in FIG. Therefore, when the input signal 13 changes from a voltage lower than the reference voltage 14 to a high voltage, the output of the first differential amplifier 11 changes from low level to high level, and the output of the second differential amplifier 12 changes to high. Change from level to low level. When the input signal 13 changes from a voltage higher than the reference voltage 14 to a lower voltage,
The output of the first differential amplifier 11 changes from high level to low level, and the output of the second differential amplifier 12 changes from low level to high level.

An example of the differential amplifier is shown in FIG. Figure 3
In (a), 21 to 23 are N-channel transistors, 24 and 25 are P-channel transistors,
26 is a positive input, 27 is a negative input, and 28 is an output of the differential amplifier. In FIG. 3B, 29 to 31 are N-channel transistors, 32 and 33 are P-channel transistors, 34 is a positive input, 35 is a negative input, 36 is an inverter, and 37 is a differential amplifier. Is the output of.
FIG. 3 (a) shows a current mirror type differential amplifier, and FIG. 3 (b) has an inverter as a buffer in the output section of the current mirror type differential amplifier. These differential amplifiers can be used as the differential amplifiers 11 and 12 in FIG.

[0011]

As described above, according to the present invention, a complementary signal can be produced at the same timing with respect to an input signal, and the practical effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a complementary signal generating circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing output signals of two differential amplifiers.

FIG. 3 is a diagram showing an example of a differential amplifier.

FIG. 4 is a circuit diagram for sampling an input voltage before AD conversion.

FIG. 5 is a block diagram of a conventional complementary signal generation circuit.

[Explanation of symbols]

 11 First Differential Amplifier 12 Second Differential Amplifier 13 Input Signal 14 Reference Voltage 15 Positive Signal 16 Negative Signal

Claims (1)

[Claims] 1. A complementary signal generating circuit for generating a positive output and a negative output for one input signal, the first differential amplifier inputting the input signal to a positive input and a reference voltage to a negative input. And a second differential amplifier for inputting the input signal to a negative input and the reference voltage to a positive input, wherein an output of the first differential amplifier is a positive signal, and a second differential amplifier Complementary signal generation circuit that makes the output of the negative signal.