JPH1040074A - High speed comparator circuit system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high speed comparator circuit which is small in circuit scale by simultaneously operating size comparison and equality detection for an input signal. SOLUTION: A difference between the impedance of transistors T18-T21 and that of transistors T22-T25 are amplified as a potential difference between a node S and a node U by transistors T28-T30 operating as constant current sources, and allowed to appear at an input node S of transistors T26, T27, T31, and T32 being output invertors. The gain of a CMOS invertor is made the maximum in the neighborhood of the inversion point(Vtrip) of an output voltage so that a little potential difference at the node S can be sharply amplified by the output invertors. Therefore, an output signal is changed at a high speed from the change of an input signal, and the Vtrip of the output voltages of two output invertors are made different so that the potential at the node S can be 1/2 Vdd when the input values are the same, and the outputs of the two invertors can be made different. Thus, not only size discrimination but also coincidence detection can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit and, more particularly, to a circuit system of a high-speed comparator which is suitable for improving the processing performance of a central processing unit.

[0002]

2. Description of the Related Art Conventionally, in a high-speed comparator circuit system of this kind, in order to compare various inputs and perform data processing in an arithmetic processing unit or the like in an information processing apparatus such as a computer, it is necessary to detect large and small operands at high speed. Used.

For example, Japanese Patent Application Laid-Open No. Sho 62-73330 discloses that a comparison logic operation is processed at high speed by detecting the coincidence / mismatch of two operands, sending necessary data to an arithmetic unit, and determining the magnitude. For example, Japanese Patent Application Laid-Open No. 5-158657 discloses a first multiplexer which receives an output of a magnitude relation detection circuit as an input in a magnitude comparator composed of a data comparison circuit and a decision circuit. And a second multiplexer that receives the output of the match detection circuit as an input. The gate group that receives the outputs of the first and second multiplexers as inputs and outputs a magnitude relationship, and outputs a higher-order output of the match detection circuit. An AND gate as an input, an AND gate as an input to a low-order output of the match detection circuit, and an output as an input from these AND gates, perform match detection. Constitute a determination circuit in a force to the gate, magnitude comparator propagation delay time has reduced less circuit elements is proposed.

In these prior arts, a digital logic circuit is used, and magnitude comparison and coincidence are detected by another circuit.

[0005] In addition, a content addressable memory (Content Ad
dressable Memory) and associative memory (Associative Memor)
In the technical field of y), even higher-speed circuits have been proposed. For example, Japanese Patent Application Laid-Open No. 5-151785 discloses a small-sized function for determining the magnitude relationship between input search data and each stored word memory. A configuration of a content addressable memory realized on a circuit scale has been proposed.

A conventional high-speed comparator circuit proposed in the above-mentioned Japanese Patent Application Laid-Open No. 5-151785 will be described with reference to FIGS. 7 (A) and 7 (B)
Compares the bit data I to be compared with the bit data M to be compared, and when M> I and M = I, respectively,
This is a circuit that outputs an “H” level. Where I ′,
M 'represents inverted data (complementary data) of the bit data I and M, respectively. FIG. 7C shows the truth table.

FIG. 6 is a diagram showing an example of a circuit configuration for comparing 4-bit data. In FIG. 6, f0 and g0 represent output signals of the circuits shown in FIGS. 7A and 7B for comparing the most significant bits (MSBs) of the 4-bit data to be compared, respectively. Signal names f1, g1; f2, g2; f3, g3 are assigned to the bits (LBS).

Next, the operation of the comparator circuit shown in FIG. 6 will be described. The signal input terminal of the transmission gate switch network is connected to a power supply Vdd, and this voltage signal is transmitted to one of two signal output terminals O ₀ and O ₁ .

When the voltage signal at the signal input terminal IN is transmitted to the signal output terminal O ₀ , one of f 0, f 1, f 2, and f 3 is “H” (High level), indicating M> I.

[0010] When the voltage signal of the signal input terminal IN is transmitted to the signal output terminal O _1, it is all g0, g1, g2, g3 is "H", shows the M = I.

When the voltage signal at the signal input terminal IN is not transmitted to either of the signal output terminals, M <I is indicated and 02 is output.

[0012]

The above-described prior art has the following problems.

(1) The first problem is that high-speed operation is difficult.

The reason is that f0, g0; f1, g1; f
2, g2; signals such as f3 and g3 rise only to Vdd-Vtn, that is, a voltage obtained by subtracting the threshold voltage Vtn of the N-channel transistor from the power supply voltage.
It depends. Moreover, since the N-channel transistors are connected in series on the path from the power supply voltage Vdd to the output terminal, the voltage of each node rises only up to Vdd-2Vtn.

Therefore, the transistor of the transmission gate network shown in FIG. 6 cannot sufficiently flow a drain-source current, so that it is difficult to operate at high speed.

(2) The second problem is that the operation speed decreases as the layout area increases.

The reason is that the output terminal is configured as a voltage divider, so that when the number of transistors is large, the resistance value at the output near end must be sufficiently increased.

(3) The third problem is that the operation speed decreases as the number of bits increases.

[0019] This is because the capacitance of the node of the signal output terminal O ₁ is, to increase the influence of the source capacitance of the transistor, because charge time is increased.

(4) The fourth problem is that the circuit scale is large because an inverter is required for each input.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a high-speed comparator circuit having a small circuit scale.

[0022]

In order to achieve the above object, a high-speed comparator circuit system according to the present invention is characterized in that a magnitude comparison and the same detection are simultaneously performed on an input signal.

In the present invention, a minute voltage difference generated by an input signal can be detected, amplified, and the output can be determined at high speed.

Further, the present invention is characterized in that signals having different weights can be simultaneously compared by optimizing the size of the transistor.

Further, the present invention is characterized in that a plurality of voltage levels are converted to a normal CMOS level by optimizing the size of the transistor of the output inverter.

The comparator according to the present invention has one or more bits of data on one side to be compared in magnitude and a comparison result signal in the preceding stage as gate inputs, and has a drain connected in common and a first current control circuit. A first transistor group connected to the higher power supply via the first transistor group, one or more bits of data on the other side to be compared in magnitude, and a comparison result signal in the preceding stage, respectively, as a gate input; A second group of transistors connected to a power supply through a circuit;
Wherein the first and second transistor groups have their sources commonly connected and are connected to a lower power supply via a third current control circuit, and one of the first and second transistor groups is provided. From the group of commonly connected drain nodes,
A signal indicating a comparison result is output via first and second output inverters having different logic threshold voltages.

In the comparator according to the present invention, the first transistor group includes a plurality of bits of input data, each having a gate input, a drain commonly connected, and a first current control circuit connected to a higher power supply. And a second transistor group having a plurality of bits of complementary data of the input data as gate inputs and connected to a power supply via a second current control circuit, wherein the first and second transistors are provided. In the group, the sources are connected in common and connected to the lower power supply via a third current control circuit, and the first and second groups are connected to each other.
The majority data of the input data is output to a commonly connected drain node of one of the transistor groups through an output inverter.

The outline of the present invention will be described below. In the present invention, by optimizing the size of a transistor, a small circuit, that is, a high-speed circuit can be achieved by simultaneously comparing signals having different weights. A function of detecting a minute voltage difference generated by an input signal, amplifying the difference, and determining the output at a high speed enables a CMOS as an output inverter.
Since the gain of the inverter becomes maximum around Vtrip,
The slight potential difference at the node is greatly amplified by the output inverter. Therefore, the output signal changes at a high speed from the change of the input signal. By optimizing the size of the output inverter, a plurality of voltage levels are converted to normal CMOS levels, so that it is possible to detect not only the magnitude but also the same level.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention is configured as a cascaded multi-bit word comparator. Comparator circuit (CM
P) 1 receives as input the bit words A1 and B1 to be compared and the A> B signal and A <B signal which are the comparison output results of the previous stage
It outputs comparison result signals P and Q. This comparison result signal P,
Q is decoded and the next comparator circuit (CMP)
Used as input. Assume that each signal is asserted at the time of the High level.

FIG. 3 shows a truth table when the number of bit words input to the comparator circuit 1 is 4 bits.

FIG. 2 shows an example showing a specific circuit configuration of the comparator circuit 1 according to the embodiment of the present invention.

Referring to FIG. 2, Nch transistor T2
8. Pch transistors T29 and T30 are current supply circuits. The Nch transistors T18 to T25 are load circuits based on input signals. Nch transistor T26
And the Pch transistor T31 constitute an inverter. In particular, by optimizing the sizes of the Pch transistor and the Nch transistor, the point of inversion of the output voltage (V
(trip) is set higher than 1/2 Vdd. That is, in the case of an inverter, a High level is output if the input voltage is equal to or lower than Vtrip, and Lo is set if the input voltage is equal to or higher than Vtrip.
Output w level.

Conversely, the Nch transistor T27 and the Pch transistor T32 are connected to the output voltage inversion point (Vtr
ip) is set lower than 1/2 Vdd.

When laying out, care should be taken to minimize the influence of the following process variations of the transistor group.

(1) Transistors T30, T18-21
And transistors T29 and T22-25.

(2) Transistors T31 and T26 and transistors T32 and T27.

The operation of the embodiment of the present invention will be described in detail with reference to FIG.

The comparator circuit (CMP) 1 shown in FIG.
Since the input bit word and the comparison output result of the previous stage are output as shown in the truth table of FIG. 3, a desired multi-bit comparator can be configured by cascading completely the same circuit configuration.

Next, the operation of the comparator circuit 1 as shown in the truth table of FIG. 3 will be described with reference to FIG. The W / L ratio indicates the ratio between the channel width and the channel length of a transistor. In a normal case, the channel length is often set to be the shortest in the process in terms of speed. However, a self-bias circuit such as the transistors T28 to T30 increases the channel length in order to make the process less susceptible to process variations and short channel effects. Sometimes. The device parameters such as the W / L ratio shown in FIG. 2 are merely examples, and need to be optimized by a process.

Transistors T18-25, T28-30
Has a source connected in common and a current source transistor T28
And operates like a differential amplifier. The difference in impedance between the transistors T18 to T21 and the transistors T22 to T25 is amplified by the transistors T28 to T30 operating as constant current sources as the potential difference between the node S and the node U, and the output inverters T26, T27, T31, Appears at 32 input nodes S.

Since the gain of the CMOS inverter becomes maximum near the inversion point (Vtrip) of the output voltage, a slight potential difference at the node S is greatly amplified by the output inverter. Therefore, the output signal changes at a high speed from the change of the input signal.

Since the inversion points (Vtrip) of the output voltages of the two output inverters are different from each other, the potential of the node S becomes 1/2 Vdd when the input values are the same.
The outputs of the two inverters are different, and it is possible to detect not only the magnitude, but also the same time.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 4 shows a circuit configuration for taking a majority decision of a 5-bit input signal. Using input signals B0 to B4 and their inverted inputs B0 'to B4', a large number of inputs among B0 to B4 are output from output terminal P of the output inverter. In FIG. 4, the transistors T33 to T4
An example of the W / L ratio of 7 is shown. FIG. 5 shows a truth table.

As an application range of the present invention, in addition to the above-described embodiment, the present invention can be applied to correction of a signal level by high-speed differential logic. That is, even if the differential signal is used and its amplitude level is small, it can be detected at high speed and restored to the power supply voltage Vdd full swing by the output inverter. As a result, a circuit that can operate at a very high speed can be connected to a normal external circuit or separated in terms of noise, so that the application of the high-speed circuit can be expanded.

The present invention can be applied to a circuit for converting a dynamic logic to a static logic, and has the same effects as described above.

[0048]

As described above, according to the present invention, the following effects can be obtained.

(1) The first effect is that the circuit scale of the comparator circuit can be reduced.

The reason is that, when the circuit of FIG. 2 is compared with the circuit of FIG. 6, the comparison logic for each bit becomes unnecessary,
It can be seen that the number of transistors is reduced.

(2) The second effect is that the operation speed is improved.

The reason is that the comparator of the present invention can detect a minute level difference of the input signal and can operate in a high gain region of the output inverter.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of the present invention, illustrating a connection method when configuring a multi-bit comparator.

FIG. 2 is a diagram showing a circuit configuration of a comparator according to one embodiment of the present invention.

FIG. 3 is a diagram showing a truth table of a circuit of a comparator according to one embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a majority decision circuit according to another embodiment of the present invention.

FIG. 5 is a diagram showing a truth table of a majority circuit according to another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional comparator circuit.

FIG. 7 is a diagram illustrating a configuration and a truth table of a conventional comparator circuit.

[Explanation of symbols]

 1 Comparator circuit 2 AND logic gate T6-T17 N-channel transistor T18-T28 N-channel transistor T29-T32 P-channel transistor T33-T43, T46 N-channel transistor T44-T45, T47 P-channel transistor R Load resistance

Claims (7)

[Claims] 2. A high-speed comparator circuit system according to claim 1, wherein a magnitude comparison and an identical detection are simultaneously performed on an input signal. And detecting a small voltage difference generated by the input signal.
A high-speed comparator circuit system characterized by being able to amplify it and determine the output at high speed. 3. A high-speed comparator circuit system wherein signals having different weights can be simultaneously compared by optimizing the size of the transistor. 4. A method of optimizing the size of a transistor of an output inverter to reduce a plurality of voltage levels to a normal CM.
A high-speed comparator circuit method characterized by conversion to an OS level. 5. A high-potential power supply via a first current control circuit having one or more bits of one-side data to be compared in magnitude and a comparison result signal in a preceding stage as gate inputs, and having a drain connected in common and a first current control circuit. A first transistor group connected to the first input terminal, one or more bits of data on the other side to be compared in magnitude, and a comparison result signal in the preceding stage as gate inputs, respectively.
A second transistor group connected to a power supply through a current control circuit of the first and second transistors, wherein the first and second transistor groups have a common source connected to a lower side through a third current control circuit. Connected to a power supply, from a commonly connected drain node of one of the first and second transistor groups via first and second output inverters having different logic threshold voltages from each other A comparator which outputs a signal indicating a comparison result. 6. A first transistor group having a plurality of bits of input data as gate inputs, a drain connected in common, and connected to a higher power supply via a first current control circuit; And a second transistor group connected to a power supply via a second current control circuit, each of the first and second transistor groups having a source connected in common. Connected to a lower power supply via a third current control circuit, and connected to a common connected drain node of one of the first and second transistor groups via an output inverter. A comparator which outputs majority data of the comparator. 7. A drain node commonly connected to said first transistor is connected to a gate of a constant current source transistor constituting said third current control circuit, and said first and second current control circuits are connected to each other. 7. The semiconductor device according to claim 5, wherein the transistor is connected to a gate of the transistor.
The described comparator.