JP2849222B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATD (Address Transit) for detecting a change in an address signal and supplying an internal synchronizing signal to constituent circuits of a semiconductor memory device, in particular, an asynchronous peripheral circuit.
ion Detect) circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an address transition detection (ATD) circuit of a conventional internal synchronous SRAM. In FIG. 3, reference numeral 1 denotes a local ATD circuit for detecting a change in each address signal from the outside. Reference numeral 2 denotes a wired OR circuit for generating a logical sum of an output signal (local ATD signal) of the local ATD circuit 1 from each address input;
Is a load resistance provided between the power supply potential, 12 is a global ATD signal for detecting that at least one of the external address signals has changed, 7 is an external address input signal, 8 is an external address input circuit, 9 is a delay circuit,
10 is an exclusive OR circuit, and 13 is an NMOS transistor.

Next, the operation will be described. When the external address input signal 7 changes in FIG. 3, the external address input circuit 8 in FIG.
At the output point a and the output point b of the delay circuit 9 change. As a result, the waveform of the output point c indicating the output signal of the local ATD circuit 1 changes as shown in FIG. As a result, a change in the external address input signal 7 is detected.

The local ATD signal output c is
A logical OR operation is performed by a wired OR circuit 2 for generating a logical sum of a local ATD signal output from each address input, and a global ATD signal 12 is generated. The wired OR circuit 2 is formed by an open drain circuit of an NMOS transistor 13, and the signal amplitude of the global ATD circuit is the same as the signal amplitude of the CMOS circuit forming the circuit and other peripheral circuits.

[0005]

Since the conventional semiconductor memory device having the ATD circuit is configured as described above, the signal amplitude of the wired OR circuit for generating the global ATD signal is equal to the signal amplitude of the CMOS circuit. In order to operate the signals generated by the local ATD circuits distributed in the chip at a high speed, it is necessary to use an NMOS transistor having a large load driving force. Therefore, there has been a problem that noise generated at the time of switching becomes large or a malfunction occurs due to the noise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a semiconductor memory device which operates at high speed and is resistant to noise.

[0007]

Means for Solving the Problems A semiconductor memory device having an ATD circuit according to the present invention, global ATD signal onset
The raw input stage is connected to an emitter consisting of a pair of transistors.
A local ATD signal composed of a couple logic circuit
The emitter-coupled logic circuit is configured in the output stage of the generator.
Including one of a pair of transistors
And a pair of transistors constituting the emitter couple logic circuit.
The differential signal of the transistor is transferred to the global A of the ATD circuit.
This is output as a TD signal .

[0008]

According to the present invention, the local ATD signal is transmitted to the subsequent wired OR circuit by using the ECL circuit, so that the signal becomes a differential signal having a small signal amplitude, the operation speed is improved, and malfunction is strong against noise. Does not wake up.

[0009]

FIG. 1 is a circuit diagram showing an ATD circuit according to an embodiment of the present invention. The same reference numerals as those in FIG. 3 denote the same or corresponding parts, and 3 denotes an NPN bipolar transistor.
Is a current source, 6 is a global ATD signal pair, 11 is a reference voltage, and the two NPN bipolar transistors 3
Are paired, and the emitters are connected to each other to form an ECL logic circuit.

Next, the operation will be described. When the external address input signal 7 changes in FIG. 1, as shown in the operation timing diagram of FIG.
And the waveform at the output point b of the delay circuit 9 changes. As a result, the waveform at the point c of the global ATD signal pair 6 changes as shown in FIG. From this signal, a change in the external address input signal 7 is detected. The local ATD signal output is subjected to a logical OR operation by a wired OR circuit 2 for generating a logical OR of the local ATD signal outputs from the respective address inputs, and is output as a global ATD signal pair 6. The wired OR circuit 2 according to the present invention includes an NPN
It is created by an emitter couple logic circuit (ECL circuit) of the transistor 3. The logic amplitude of this ECL circuit is smaller than that of a conventional CMOS circuit as shown in FIG. 2c. Also, this global ATD signal pair 6
Are differential signals as shown in FIG. 2c.

As described above, according to the present embodiment, the local A
The output stage of the TD circuit 1 and the input stage of the wired OR circuit 2 are composed of an ECL circuit composed of NPN bipolar transistors 3 whose emitters are connected to each other, and a local AT
Since the D signal is transmitted to the wired OR circuit 2, the local ATD signal becomes smaller than the signal amplitude of the CMOS circuit, and the delay time at the rise and fall is reduced, so that a circuit with a high operation speed can be obtained. .

When the logic threshold value of the device is set to, for example, 1/2 Vcc which is half of the power supply potential Vcc, for example, if Vcc is 2 to 3 V, the threshold value is 1 to 1.5 V
Therefore, a malfunction may occur if the ground potential is different depending on the location. However, in the present invention, since the differential signal is used, even when the power supply potential Vcc is low, the operation can be reliably performed, and the noise can be reduced. It is less affected.

[0013]

As described above, in the semiconductor memory device provided with the ATD circuit according to the present invention, the ATD signal transmitted in the chip of the semiconductor memory device is operated by the ECL circuit. It is possible to obtain a semiconductor memory device which is small, can be operated at high speed, and is less affected by noise because of a differential signal, has excellent operation accuracy, and has a high operation speed. is there.

[Brief description of the drawings]

FIG. 1 illustrates an AT of a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a circuit configuration of a D circuit.

FIG. 2 shows an AT of a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating operation timing of a D circuit.

FIG. 3 is a diagram showing a circuit configuration of an ATD circuit in a conventional semiconductor memory device.

FIG. 4 is a diagram showing an operation timing of an ATD circuit in a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Local ATD circuit 2 Wired OR circuit 3 NPN bipolar transistor 4 Current source 5 Load resistance 6 Global ATD signal pair 7 External address input signal 8 External address input circuit 9 Delay circuit 10 Exclusive OR circuit 11 Reference voltage 12 Global ATD signal 13 NMOS transistor

Claims (1)

(57) [Claims] 1. A provided for each address signal, and a plurality of local ATD signal generator for outputting a local ATD signal is exclusive OR signal and the delay signal of the predetermined address signal and said address signal, a plurality of local It receives the ATD signal, comprising a global ATD signal generator consisting of an address transition detection (ATD) circuit that outputs a global ATD signals from these ORs upper Kigu global ATD signal generator has an input stage, one
An emitter-coupled logic circuit consisting of a pair of transistors ?
Wherein the local ATD signal generation section comprises:
The above-mentioned emitter-coupled logic circuit is formed at the output stage.
A pair of transistors including one of the pair of transistors and constituting the emitter-coupled logic circuit.
The differential signal of the register is converted to the global ATD of the ATD circuit.
A semiconductor memory device characterized by outputting as a signal .