JPH05322984A - Test input circuit - Google Patents

Abstract

PURPOSE:To maintain normal operation state without causing erroneous operation such as outputting test signal at an active level even with sudden variation in power source voltage in normal operation state by generating a test signal only when a high voltage for test signal is input. CONSTITUTION:An inverter 9 having small logical threshold value compared with inverters 10, 11 and having a slow transition velocity of logical level is provided. As soon as the voltage at a contact point A exceeds the threshold value of the inverter 10, the inverter 10 reverses, the output of the inverter 11 becomes 'H' level and a test level detection signal is generated from an AND gate 12 and a latch constituted of NOR gates 13, 14 is set. Then, as soon as the voltage at a contact point B exceeds the threshold value of the inverter 9, the output of the inverter 9 becomes 'L' level. As the output of the NOR gate 14 is set at 'L' level, a test signal at an active level is generated out of the NOR gate 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a test input circuit,
In particular, the present invention relates to a test input circuit for inputting both a normal signal and a test signal with a single terminal.

[0002]

2. Description of the Related Art Conventionally, as a test input circuit for inputting a test signal also as a normal signal, a test signal is input as a test signal when a high voltage higher than a power supply voltage level is input.
Some use a value level detection circuit. FIG. 4 shows a circuit diagram, and FIGS. 5, 6 and 7 show timing charts. First, when the GND level is input to the dual-purpose terminal 21, the N-type transistors 22 and 23 are off and the N-type transistor 24 is on. Therefore, as shown in the period T1 of FIG.
Since the output of the inverter 26 is "H" level, the output of the inverter 27 is "L" level, the test signal is not generated and the output of the buffer 25 is "L" level, the normal signal is "L" level. It Next, when the power supply voltage VDD level is input to the dual-purpose terminal 21, the N-type transistors 22, 23 and 24 are turned on, so that the potential of the contact A is of the N-type transistors 22 and 23 as shown in the period T2 of FIG. Threshold and N-type transistors 22 and 23
And the ON resistance of the N-type transistor 24. For example, as the ON resistance of the N-type transistor 24 is smaller than the sum of the ON resistances of the N-type transistors 22 and 23, the potential of the contact A shifts downward. Now, the dimension of each transistor is determined so that the potential of the contact A becomes 1/2 of the voltage input to the dual-purpose terminal 21, and the threshold value Vth1 of the inverter 27 is set to 3/4 of the power supply voltage. The output of the inverter 26 is "H" level, the output of the inverter 27 is "L" level, and no test signal is generated. The output of the buffer 25 becomes "H" level and the "H" level is input as a normal signal. When a voltage higher than the power supply voltage (for example, 1.6 times the power supply voltage) is applied to the dual-purpose terminal 21, the potential of the contact A becomes higher than the threshold value Vth1 of the inverter 27 as shown in FIG.
Output is "L" level, output of inverter 27 is "H"
It becomes a level and a test signal is generated. As described above, when used as a normal terminal, a voltage lower than the power supply voltage level is input, and when a normal signal is taken out from the buffer 25 and used as a test terminal, a voltage higher than the power supply voltage is applied.
A test signal is generated from the inverter 27, and two types of signals, a normal signal and a test signal, can be input at one terminal.

[0003]

In the above-described conventional test circuit, the N-type transistors 22 and 23 are turned on and the contact A
The rising speed of the potential of the contact A is fast because it raises the potential of the N type transistor 24 because it is a ratio input circuit.
The on-resistance of is increased and the fall of the potential of the contact A is discharged by the N-type transistor 24 and falls, so that the fall speed becomes relatively slow. Considering the case where the power supply voltage sharply drops to 1/2 while applying the power supply voltage level to the dual-purpose terminal 21, the threshold value Vt of the inverter 27 is considered.
Since h1 is designed to be 3/4 of the power supply voltage, it falls at the same speed as the power supply voltage drops as shown in FIG. 7, but the potential of the contact A is the parasitic capacitance C of the contact A of the N-type transistor 24. Since the electric charge stored in is discharged, a time delay td
After a, it chills to 1/4 of the original power supply voltage. Here, since the potential of the contact A slowly drops below the threshold value Vth1 of the inverter 27, there is a period during which the potential of the contact A becomes larger than the threshold value Vth1 of the inverter 27, and the output of the inverter 27 is at the "H" level during that period. Then, a test signal is generated and the normal operation state cannot be maintained, so that there is a drawback that it cannot be applied to applications in which the power supply voltage fluctuates rapidly.

An object of the present invention is to provide a test input circuit which can maintain a normal operation state without causing a malfunction of outputting a test signal of an active level even when a power supply voltage fluctuates rapidly in a normal operation state. is there.

[0005]

A test input circuit according to the present invention includes an input terminal for inputting a test signal and a normal signal, a first gate circuit connected to the input terminal for generating a normal signal, and the input terminal. An input circuit that is connected and has first and second input levels, a second gate circuit that generates a set signal by the outputs of the first and second input circuits, and a second gate circuit that sets And a third gate for generating a test signal according to the output of the latch and the output of the second input circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
The test signal shared terminal 1 is a shared input terminal for inputting a normal signal and a test signal, N-type transistors 2 to 7 are transistors forming a ratio input circuit for detecting a test signal, and inverters 9 and 10 are inverters having different input levels. The AND gate 12 is an AND gate for generating a test level detection signal, and the NOR gates 13 and 14 are N latches set by the test level detection signal.
It is an OR gate. The NOR gate 15 generates a test signal by matching the output of the latch with the test level N.
It is an OR gate. FIG. 2 shows a timing chart of each part when a high voltage level is applied as the test signal voltage from the power supply voltage to the dual-purpose terminal 1. First, in the period of T1, the power supply voltage VDD level is applied to the dual-purpose terminal 1. The dimensions of the N-type transistors 2 to 7 are determined so that the contacts A and B have a potential of 1/2 of the voltage Vin input to the dual-purpose terminal 1 and have a value of 1/2 of the power supply voltage VDD. Thresholds Vth1 and Vth of the inverters 10 and 9
Since 2 is set higher than 1/2 of the power supply voltage, the outputs of the inverters 9 and 10 are both "H" level, the output of the NOR gate 15 is "L" level, and the active level test signal is Does not occur. Buffer 8
Is at "H" level, and "H" level is input as a normal signal. Next, when a voltage higher than the power supply voltage is applied to the dual-purpose terminal 1 as the test signal voltage during the period T2, the potentials of the contacts A and B rise as shown by the broken line in FIG.
The reason why the potential of the contact B rises slowly is that extra time is required to charge the load capacitance C1. At the moment when the potential of the contact A exceeds the threshold value Vth1 of the inverter 10, the inverter 10 is inverted and the output of the inverter 11 becomes "H" level. At this time, a test level detection signal is generated from the AND gate 12 and the NOR gate 13 is generated. , 14 are set. Next, at the moment when the potential of the contact point B exceeds the threshold value Vth2 of the inverter 9, the output of the inverter 9 becomes the "L" level and the output of the NOR gate 14 is set to the "L" level.
Generates a test signal of active level. NO
The latch formed by the R gates 13 and 14 is reset by a reset signal as an initial state, and the output of the NOR gate 13 is at "L" level and the output of the NOR gate 14 is at "H" level.

Next, the operation will be described with reference to the timing chart shown in FIG. 3 when the power supply voltage is drastically lowered during the normal operation. First, during the T1 period, the voltage applied to the dual-purpose terminal 1 is the power supply voltage level, and as described above, the "H" level is input as the normal signal and the test signal is not generated. Next, when the power supply voltage sharply drops during the period T2, the potentials of the contacts A and B are as shown by the broken line in FIG. 3 because the N-type transistors 6 and 7 discharge the charges of the parasitic capacitance C and the load capacitance C1, respectively. Inverters 10, 9
Since the threshold values Vth1 and Vth2 are determined only by the power supply voltage, the one-dot chain line Vth1 and the two-dot chain line Vth2, respectively.
As shown by, changes at the same speed as the power supply voltage. Time t1
Since the threshold value Vth2 of the inverter 9 becomes lower than the potential of the contact B, the output of the inverter 9 is inverted and becomes "L" level. Similarly, at time t2, the threshold value V of the inverter 10
Since th1 becomes lower than the potential of the contact A, the inverter 10
Is inverted, and the output of the inverter 11 becomes "H" level. At time t3, the potential of the contact A becomes lower than the threshold value Vth1 of the inverter 10, so that the inverter 10 is inverted again, and the output of the inverter 11 becomes "L" level. At time t4, the potential of the contact B is the threshold value Vt of the inverter 9
Since it becomes lower than h2, the inverter 9 is inverted and the output becomes "H" level. With the above series of operations, the inverter 11
Since the inverter 9 is at "L" level when is at "H" level, the output of the AND gate 12 is always at "L" level, the test level detection signal is not generated, and the test signal is always at "L" level. No active level test signal is generated.

[0009]

As described above, according to the present invention, since the test signal is generated only when the high voltage for the test signal is input, there is no possibility that the test signal is erroneously generated by the fluctuation of the power supply voltage and malfunctions. This has the effect of configuring a test input circuit with a wide operating range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a test input circuit according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the test input circuit of FIG.

FIG. 3 is an operation timing chart of the test input circuit of FIG.

FIG. 4 is a circuit diagram of a conventional test input circuit.

5 is a timing chart of the test input circuit of FIG.

6 is a timing chart of the test input circuit of FIG.

FIG. 7 is a timing chart of the test input circuit of FIG.

[Explanation of symbols]

 1 Dual-purpose input terminal for test signal and normal signal 2-7 N-type transistor 8 Input buffer for normal signal 9-11 Inverter 12 AND circuit 13-15 NOR circuit

Claims (1)

[Claims] 1. An input terminal for receiving a test signal and a normal signal, a means for connecting the input terminal and a circuit for supplying a normal signal, and a serial connection between the input terminal and a reference voltage terminal. A plurality of first voltage drop means, a plurality of second voltage drop means whose inputs are connected to one connection point of the plurality of first voltage drop means, and one connection point of the second voltage drop means. A second gate circuit having an input connected to it and having a logic function opposite to that of the first gate circuit, a logic threshold value less than a logic threshold value of the first gate circuit; A third gate circuit connected to an output terminal of the second gate circuit and outputting an active level when both of the two outputs are at an active level; latch means connected to an output of the third gate circuit; Second gate circuit and And a fourth gate circuit connected to the outputs of the latch means and outputting an active level test signal when the two outputs are both inactive level.