JPH0636571A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent increase in the chip size of a circuit provided with an intermediate level in an output level for operating an output buffer circuit at high speed and to suppress stray capacitance in an output terminal. CONSTITUTION:When an address signal 101 is changed, one shot pulse signals 104, 105 become an 'H' level only for the interval of a time T1. Since an output signal 107 when an input signal 106 is in the 'H' level is in the state of the 'L' level, a PMOS transisor 13 forming a main output transistor is turned on, and the output signal 107 is changed from the 'L' level to the 'H' level. Nevertheless, when the level of the output signal exceeds the threshold value voltage of a NOR circuit 25, the level of a node A is changed from the 'L' level to the 'H' level, and the PMOS transistor 13 forming the main output transistor is turned off, and the level of the output signal 107 is held to the intermediate level. For the interval of a time T1, a memory cell is selected by an internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device forming an output buffer circuit.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit of this type has NOR circuits 57 and 67, NA as shown in FIG.
ND circuits 58 and 68, inverters 59, 60, 65
And 66, PMOS transistors 61 and 62, N
It is configured to include MOS transistors 63 and 64 and a one-shot pulse generation circuit 69.

In FIG. 6, in the one-shot pulse generation circuit 69, address signals (A ₀ , A ₁ , A ₂ ,
.., A _n−1 , A _n ) 117 are sensed to generate one-shot pulses 118 and 119. These one-shot pulses 118 and 119 are NO.
It is input to the R circuit 57 and the NAND circuit 58. The input signal 120 is also input to the NOR circuit 57 and the NAND circuit 58. When the input signal 120 is at “H” level and any one of A ₀ , A ₁ , A ₂ , ..., A _n−1 , A _n included in the address signal 117 is changed, One-shot pulse 118 is “L” level, one-shot pulse 11
9 is "H" level, input signal 120 is "H" level, and the levels at node A, node B and node C are "H".
The level of the node D is "L" level, and the level of the output signal 121 is "L" level.

In this level state, the address signal 1
When any one of 17 changes, the change is sensed in the one-shot pulse generation circuit 69, and one-shot pulses 118 and 119 are generated and output. FIG. 7 shows the address signal 117, the one-shot pulses 118 and 119, and the input signal 12 in the conventional example.
9 is a diagram showing the level relationship between 0, the output signal 121, and each node. As is clear from FIG. 7, the one-shot pulse 118 is at the “H” level and the one-shot pulse 119 is at the “T” level during the time T _1. L level. As a result, the level of the node B changes from "H" level to "L" level, and the NMOS transistor 63 is turned off. At this time, both the main output transistors are turned off. On the other hand, the NOR circuit 67 and the NAND
In the circuit 68, the potential level of the output signal 121 is determined during that period, the level of the node C changes from the “H” level to the “L” level, and the PMOS transistor 62 is turned on. As a result, the output signal 121 changes from the “L” level to the “H” level, and the output signal 12
When the potential of 1 exceeds the threshold potential of the NOR circuit 67,
The NOR circuit 62 outputs the “L” level again,
The PMOS transistor 62 is turned off. As a result, the level of the output signal 121 changes to the intermediate level (NOR
The threshold voltage of the circuit 67).

On the other hand, in the NAND circuit 68, since the threshold voltage is set to a potential higher than that of the NOR circuit 67, the NMOS transistor 64 cannot be turned on in this case, but the output signal 121 When the potential level rises excessively or is in the "H" level state, the NMOS transistor 64 is turned on to keep the output signal 121 at the intermediate level. In this way, the output signal 121 is fixed at the intermediate level during the time T ₁ . On the other hand, during the time T ₁ , the memory cell is selected in the internal circuit and the input signal 12
0 is changed from "H" to "L". When the one-shot pulse 118 changes from “H” level to “L” level and the one-shot pulse 119 changes from “L” level to “H” level, the PMOS transistor 61 is turned on and the level of the output signal 121 is changed. Changes from the intermediate level to the "H" level at once.

As described above, in the conventional output buffer circuit, in comparison with the case where the output signal 121 changes from the "L" level to the "H" level during operation, the output signal 121 changes from the intermediate level to the "H" level. One of the features is that it can be operated at high speed because it changes to the H "level. This is the same when changing from the "H" level to the "L" level.

[0007]

In the above-described semiconductor device forming the conventional output buffer circuit, a dedicated PM is used to set the level of the output signal 121 to the intermediate level.
OS transistor 62 and NMOS transistor 64
Is required to be connected to the output terminal as a sub-output transistor, which tends to increase the chip size of the semiconductor device, and also increases parasitic capacitance at the output terminal to deteriorate the characteristics. .

[0008]

A semiconductor device according to a first aspect of the present invention is a one-shot device which receives an address signal, generates a first one-shot pulse and a second one-shot pulse in response to a change in the address signal. A pulse generation circuit, a first NOR circuit that receives a first activation signal and an input signal from an internal circuit, and a first NAND circuit that receives a second activation signal and the input signal. And a positive logic output that changes according to the potential of a predetermined output terminal only when the output of the first NOR circuit and the first and second one-shot pulses are input. Output,
In other cases, the first clocked inverter whose output side has a high impedance, the output of the first NAND circuit, and the first and second one-shot pulses are input, and the one-shot pulse A second clocked inverter that outputs a positive logic output that changes according to the potential of a predetermined output terminal only when it occurs, and the output side becomes high impedance in other cases, the source is connected to the power supply, and the gate is A PMOS transistor connected to the output terminal of the first clocked inverter and having a drain connected to the output terminal; and a drain connected to the output terminal and a gate connected to the output terminal of the second clocked inverter. N connected with the source connected to ground potential
A MOS transistor, a second NOR circuit in which the second one-shot pulse is input to one input terminal, and the first one-shot pulse in one input terminal,
A second NAND circuit in which the other input end of the second NOR circuit is connected to the other input end, and an output end is the P input
The second N connected to the gate of the MOS transistor.
The output of the OR circuit and the first and second one-shot pulses are input, and a positive logic output that changes according to the potential of the output terminal is output only when the one-shot pulse is generated. In other cases Has a third clocked inverter whose output side has a high impedance, and whose output end is the N-type.
The second N connected to the gate of the MOS transistor.
The output of the AND circuit and the first and second one-shot pulses are input, and a positive logic output that changes according to the potential of the output terminal is output only when the one-shot pulse is generated. In other cases Is equipped with a fourth clocked inverter whose output side has a high impedance, and operates as an output buffer circuit.

The semiconductor device of the second invention inputs an address signal, receives the change of the address signal, and generates and outputs the first, second, third and fourth one-shot pulses. A one-shot pulse generating circuit, a first activation signal and a first input signal from an internal circuit
NOR circuit, a first NAND circuit that receives a second activation signal and the input signal, an output of the first NOR circuit, and the first and second one-shot pulses. And outputs a positive logic output that changes according to the potential of a predetermined output terminal only when the one-shot pulse is generated, and in other cases, a first clocked inverter whose output side has a high impedance, NAN of 1
The output of the D circuit and the first and second one-shot pulses are input, and a positive logic output that changes according to the potential of a predetermined output terminal is output only when the one-shot pulse is generated. In this case, a second clocked inverter whose output side has high impedance, a source is connected to a power supply, a gate is connected to an output terminal of the first clocked inverter, and a drain is connected to the output terminal. A PMOS transistor, a drain of which is connected to the output terminal, a gate of which is connected to an output terminal of the second clocked inverter, and a source of which is connected to a ground potential, and an NMOS transistor which has one input terminal of the fourth transistor. Second NOR circuit to which the one-shot pulse is input, and the third one-shot pulse to one input terminal and the other input terminal A second NAND circuit other input terminal of the serial second NOR circuit is connected an output terminal connected to the gate of the PMOS transistor, the second
Of the NOR circuit and the third and fourth one-shot pulses are input, and a positive logic output that changes according to the potential of the output terminal is output only when the one-shot pulse is generated. In this case, a third clocked inverter whose output side has a high impedance, and an output end of which is connected to the gate of the NMOS transistor,
The output of the NAND circuit and the third and fourth one-shot pulses are input, and a positive logic output that changes according to the potential of the output terminal is output only when the one-shot pulse is generated. In this case, a fourth clocked inverter whose output side has a high impedance, and the PM
To have a first capacitor connected between the gate of the OS transistor and the ground potential and a second capacitor connected between the gate of the NMOS transistor and the ground potential, and to operate as an output buffer circuit. Is characterized by.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment is NO
R circuits 1 and 25, NAND circuits 2 and 26,
A clocked inverter 3 including PMOS transistors 4 and 5 and NMOS transistors 6 and 7, PMOS transistors 9 and 10 and an NMOS transistor 11,
Clocked inverter 8 including 12 and PMOS transistors 16 and 17 and NMOS transistors 18 and 1
9 and a clocked inverter 15, PMOS transistors 21, 22 and NMOS transistors 23, 2
4 and a clocked inverter 20, a PMOS transistor 13, and an NMOS transistor 14. 2 (a), (b), (c), (d)
FIGS. 3E and 3E are timing charts of main signals in this embodiment, and FIG. 3 shows the address signal 101, activation signals 102 and 103, one-shot pulses 104 and 105, and input signal in this embodiment. 10
FIG. 6 is a diagram showing the level relationship between the output signal 107 and the nodes (A and B).

In FIG. 1, the operation of this embodiment when the address signal 101 changes and the input signal 106 changes from "H" level to "L" level will be described.

When the address signal 101 changes, the one-shot pulse signals 104 and 105 receive it,
Each only during the time T ₁ becomes "H" level. As a result, the outputs of the clocked inverters 3 and 8 are in a high impedance state. On the other hand, the NOR circuit 25 and the NAND circuit 26, and the clocked inverters 15 and 20 are activated, and the PMOS transistor 13 forming the main output transistor is activated according to the potential level of the output signal.
Alternatively, the NMOS transistor 14 is turned on. Output signal 107 when input signal 106 is at "H" level
Is in the state of "L" level, in this case, the PMOS transistor 13 forming the main output transistor is turned on, and the output signal 107 changes from "L" level to "H" level. However, when the level of the output signal exceeds the threshold voltage of the NOR circuit 25, the level of the node A changes from "L" level to "H" level, turning off the PMOS transistor 13 forming the main output transistor. As a state, the level of the output signal 107 is held at the intermediate level. Further, during the time T _1, the memory cell is selected by the internal circuit, and the input signal 106 changes from the “H” level to the “L” level, whereby the output signal 107 suddenly changes from the intermediate level to the “H” level. Change to a level.

On the other hand, even when the address signal 101 changes and the input signal 106 changes from "L" level to "H" level, as shown in FIG.
The operation is performed in the same manner as when 06 changes from the "H" level to the "L" level.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, in this embodiment, NOR circuits 28 and 54, NAND circuits 29 and 55,
A clocked inverter 30 including PMOS transistors 31, 32 and NMOS transistors 33, 34;
A clocked inverter 35 including PMOS transistors 36, 37 and NMOS transistors 38, 39;
A clocked inverter 44 including PMOS transistors 45 and 46 and NMOS transistors 47 and 48;
A clocked inverter 49 including PMOS transistors 50 and 51 and NMOS transistors 52 and 53;
PMOS transistor 42 and NMOS transistor 4
3 and capacitors 40 and 41. 5 (a), (b), (c), (d), (e),
Shown in (f) and (g) are timing diagrams of the main signals in this embodiment.

In FIG. 4, the difference between the present embodiment and the first embodiment is that in the second embodiment, the one-shot pulse 11 is supplied from the one-shot pulse generating circuit 56.
1 and 112 and two sets of one-shot pulses 113 and 114 are output and individually supplied to the clocked inverters 30 and 35 and the clocked inverters 44 and 49, respectively. The gates of the PMOS transistor 42 and the NMOS transistor 43 forming the output transistor are connected to the ground potential via the capacitors 40 and 41, respectively. One-shot pulses 111 and 112 and one-shot pulses 113 and 114
As shown in FIGS. 5D, 5E, 5F and 5G, the one-shot pulse 111
Includes one-shot pulse 112 in time, and one-shot pulse 113 is also set to include one-shot pulse 114 in time. This is
The off state of the clocked inverters 30 and 35 and the on state of the clocked inverters 44 and 49 occur at the same timing, so that a through current flowing through the PMOS transistor 42 and the NMOS transistor 43 forming the main output transistor is generated. This is to prevent it.

The capacitors 40 and 41 connected to the nodes A and B are connected to the one-shot pulse 111.
And 112 and one-shot pulses 113 and 11
4 is a capacitor provided in order to avoid a floating state at nodes A and B caused by the timing shift of No. 4, and by this capacitor, the PMOS transistors 42 and N forming the main output transistor are formed.
The gate potential of the MOS transistor 43 is guaranteed.

The operation of the output buffer circuit of this embodiment is exactly the same as that of the first embodiment described above, and the explanation of the operation is omitted to avoid duplication.

[0019]

As described above, according to the present invention, the main output transistor connected to the output terminal is formed by the PMOS transistor and the NMOS transistor, and the main transistor and the output terminal act to have an intermediate level. By sharing the sub output transistor, it is possible to prevent the chip area of the semiconductor device forming the output buffer circuit from increasing and to suppress the parasitic capacitance at the output terminal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of main signals in the first embodiment.

FIG. 3 is a diagram showing a main signal and a level relationship at each node in the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a timing diagram of main signals in the second embodiment.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a diagram showing a main signal and a level relationship at each node in a conventional example.

[Explanation of symbols]

1, 25, 28, 54, 57, 67 NOR circuit 2, 26, 29, 55, 58, 68 NAND circuit 3, 8, 15, 20, 30, 35, 44, 49 Clocked inverter 4, 5, 9, 10, 13, 16, 17, 21, 22, 3
1, 32, 36, 37, 42, 45, 46, 50, 5
1, 61, 62 PMOS transistors 6, 7, 11, 12, 14, 18, 19, 23, 24,
33, 34, 38, 39, 43, 47, 48, 52, 5
3, 63, 64 NMOS transistors 40, 41 capacitors 59, 60, 65, 66 inverters

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 19/0175 19/017 8941-5J 8941-5J H03K 19/00 101 F

Claims (2)

[Claims] 1. A one-shot pulse generation circuit for inputting an address signal, generating and outputting first and second one-shot pulses in response to a change in the address signal, a first activation signal and an internal circuit. A first NOR circuit which receives an input signal from a circuit, a first NAND circuit which receives a second activation signal and the input signal, an output of the first NOR circuit and the first NOR circuit The first and second one-shot pulses are input, and a positive logic output that changes according to the potential of a predetermined output terminal is output only when the one-shot pulse is generated. In other cases, the output side has high impedance. A first clocked inverter, the output of the first NAND circuit, and the first and second one-shot pulses are input, and a predetermined output is generated only when the one-shot pulse is generated. A second clocked inverter that outputs a positive logic output that changes according to the potential of the terminal, and that otherwise has a high impedance on the output side, a source connected to the power supply, and a gate connected to the first clocked inverter. A PMOS transistor connected to the output terminal of the inverter and having a drain connected to the output terminal; and a drain connected to the output terminal and a gate connected to the second terminal.
An NMOS transistor connected to the output terminal of the clocked inverter and having a source connected to the ground potential, a second NOR circuit receiving the second one-shot pulse at one input terminal, and one input terminal A second NAND circuit having the first one-shot pulse input to its end and the other input end of the second NOR circuit connected to the other input end, and an output end connected to the gate of the PMOS transistor. Connected to the output of the second NOR circuit and the first and second
And a positive logic output that changes in accordance with the potential of the output terminal only when the one shot pulse is generated. In other cases, the output side becomes high impedance. A clocked inverter, the output end of which is connected to the gate of the NMOS transistor, the output of the second NAND circuit and the first and second one-shot pulses are input, and only when the one-shot pulse is generated. A fourth clocked inverter that outputs a positive logic output that changes according to the potential of the output terminal and that has a high impedance on the output side in other cases, and operates as an output buffer circuit. Semiconductor device. 2. A one-shot pulse generation circuit which inputs an address signal, receives the change of the address signal, and generates and outputs first, second, third and fourth one-shot pulses, and First NOR circuit that receives the activation signal of the second activation signal and the input signal from the internal circuit, a first NAND circuit that receives the second activation signal and the input signal, and the first NOR circuit. The output of the circuit and the first and second one-shot pulses are input, and a positive logic output that changes according to the potential of a predetermined output terminal is output only when the one-shot pulse is generated, and in other cases A first clocked inverter whose output side has a high impedance, an output of the first NAND circuit, and the first and second one-shot pulses are input to Only a second clocked inverter that outputs a positive logic output that changes according to the potential of a predetermined output terminal and that has high impedance on the output side in other cases is connected to the power source at the source, and the gate is at the first terminal. A PMOS transistor connected to the output terminal of the first clocked inverter and having a drain connected to the output terminal; and a drain connected to the output terminal and a gate connected to the second terminal.
An NMOS transistor connected to the output terminal of the clocked inverter and having a source connected to the ground potential, a second NOR circuit to which the fourth one-shot pulse is input to one input terminal, and one input terminal A second NAND circuit having the third one-shot pulse input to its end and the other input end of the second NOR circuit connected to the other input end, and an output end connected to the gate of the PMOS transistor. Connected to the output of the second NOR circuit and the third and fourth
And a positive logic output that changes in accordance with the potential of the output terminal only when the one shot pulse is generated. In other cases, the output side becomes high impedance. A clocked inverter, an output terminal of which is connected to the gate of the NMOS transistor, inputs the output of the second NAND circuit and the third and fourth one-shot pulses, and only when the one-shot pulse is generated Connected between a fourth clocked inverter that outputs a positive logic output that changes according to the potential of the output terminal, and has a high impedance on the output side otherwise, and the gate of the PMOS transistor and the ground potential. And a second capacitor connected between the gate of the NMOS transistor and the ground potential, And a semiconductor device which operates as an output buffer circuit.