JPH02118991A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in a characteristic of tDH due to a difference in the changing timing from a low to a high level of a control signal WEP and a change timing of a write signal by outputting a data externally from a memory cell via a readout circuit such as a sense amplifier when a storage device reaches from the write to a readout state without fail. CONSTITUTION:An address transition detection circuit 1 of a semiconductor device detects a logical change in one address input or over and outputs a pulse signal. Each pulse signal is inputted to transistors (TRs) 21 - 23 of an internal control circuit 2 and synthesized. A timer circuit 3 measures the time from a point of time when the logical change in the address is detected and outputs the result of measurement to the circuit 2. Moreover, a write control signal the inverse of control signal WE is inputted to an inverter 201 of the write control circuit 20 to process it at a delay circuit comprising an inverter and a capacitor, a timing the inverse of WEC when the inverse of We Pad changes from a low to a high level is inputted to the circuit 2, from which an internal control signal is outputted.

Description

[Detailed description of the invention] [Industrial use 1! F1 The present invention relates to a semiconductor memory device, and particularly to an internally identical 11J1 type random access memory having an auto power down function.

[Prior Art] Conventionally, in order to achieve low current consumption by cutting off the DC current flowing in memory cells, sense amplifiers, etc. during reading after a predetermined period of time has passed while the address input changes, and to prepare for the next cycle, data lines have been cut off. Random access memory with an internal equal amount of memory having an auto power-down function has been proposed for the purpose of achieving high-speed access times by equalizing the memory in advance.

Conventional semiconductor devices of this type include those shown in FIGS. 4 and 5. FIG. 4 is a diagram showing a circuit configuration of a conventional internal concave random access memory having an odd power down function, and FIG. 5 is a diagram showing the detailed circuit of FIG. 4.

In FIG. 4, An Pad is an address input signal, and after passing through an address buffer 5, an address decoder 6 selects a memory cell and a column selection gate corresponding to the address input signal An Pad from a memory cell array 7 and a column selection gate array 8. WS for selection
and column selection signal CT are output.

At the time of reading, the data of the selected memory cell passes through BL, BL, column selection gate, and DB-DB, is amplified by the sense amplifier 9, and is output to Ilo and Ilo. After passing through the latch circuit 10, the data amplified by the sense amplifier 9 is sent to the output terminal I/OPa via the output buffer 11.
It is output to d.

When writing, the write data input to I/OP ad (data buffer 13-10-I10-write circuit 12-DB-DB-column selection gate 1--BL
-BL path and written into one selected memory cell. Here, the data buses DB and DB and the I10 bus I10
- Ilo is a common pass line for write data and read data, and write data is output during writing, and read data is output during read.

In FIG. 5, the address transition detection circuit 1 receives the output of the address buffer 5, and receives the address input signal AnPa.
A pulse signal is generated by detecting a logic change in d. The internal circuit (circuit 2') uses the pulse signal as a basic pulse to generate a control signal SC' for controlling the circuit inside the two-failure device, and outputs it to the address decoder 6, sense amplifier 9, and latch circuit 10. The circuit 3 is a timer that receives a signal from the internal control circuit 2' and measures the time from when the address input signal An Pad changes until the automatic power down state is reached.

FIG. 5 is a diagram showing detailed circuits of the address transition detection circuit 1, internal control circuit 2', and timer circuit 3 in the circuit configuration of FIG. 4. In FIG. 5, the address transition detection circuit 1 outputs the address buffer output A1. It consists of delay circuits 11, 12, and 13 that receive A2 and An and delay signals, and exclusive OR gates 14, 15, and 16 that take the exclusive OR of the output of each address buffer and its delayed signal. The transition of the output of the buffer is detected and the pulse signal ATD1. Outputs ATD2 and ATDn. In FIG. 5, the output of the address buffer is A1. Although three A2 and 80 are shown, the number may be more than three or less than three depending on the capacity of the storage device.

The internal control circuit 2' has ATDl, ATD2 . Nch transistors 21°22.23 and P receiving ATDn respectively
ch) It is composed of a transistor 24, an impeller 25, an inverter 27 for inverting the write control signal W EP a d, a negative AND gate 28, and a NOR gate 26.

Pulse signals ATD 1, ATD 2, AT are generated by Nch transistors 21, 22, 23 and Pch transistor 24.
An OR circuit for synthesizing Dn is configured, and a negative AND gate 28 and a NOR gate 26 take the logic of the output of the OR circuit, the internal write signal WE, and the output signal of the quemer circuit 3, and output an internal control signal SC'. .

The timer circuit 3 includes a capacitance C31 for generating a delay,
C32, C33 and Pch for charging the capacitance - transistor 3638 and Nch
It is composed of transistors 37, 39, inverters 32, 33, 34 for discharging the charge of the capacitance, inverters 31 and 35, and a Nant gate 310. Timer circuit 3 receives pulse signal ATD1. When Nl, which is the composite signal of ATD2 and ATDn, is at a low level, the capacitance C
31, C32, and C33 are charged, and the inverters 32, 33, and 34 start discharging the capacitance from the time when N1 changes to High level.
Transistor size and capacitance C constituting 34
After a time constant determined by the sizes of C31, C32, and C33 has elapsed, a signal TIME informing the internal control circuit 2' of entering the auto power down state is sent from the chin 1ζ game h310. Here, the time constant of the timer circuit is set to be longer than the time from when the address changes until the output of the sense amplifier is determined.

Since the conventional semiconductor memory/jQ device is configured as described above, it performs the following operations during reading and writing.

As shown in FIG. 6(a), consider a case in which the address input signal An Pad changes at time t1 and N2 when WEPadlJ5 is fixed at High level, that is, when the storage device is in the read mode.At time 0 tl, the address input signal An is
Pad changes, and upon detecting the change, the address transition detection circuit 1 sends out a pulse signal ATDn that changes to Low-+High-+Low, and the synthesis circuit of the internal control circuit 2' obtains the synthesized inverted signal N1. In the timer circuit 3, N1 is Low, and the inverter 3 is the inverse of that.
When the output N2 of 1 is High, the Pch transistor 36, Nch) transistor 37, and Pch transistor 38 are turned on, and the capacitances C31, C32, and C33 are turned on.
In order to charge each of them, N3 and N5 become High level, and N4 to N6 become Low level. This N1 and N6
Due to the change in the negative AND gate 310 output TI
ME changes from LOW to HIGH. After that, N1 becomes H
When changing to high level, N constitutes impark 32.
ch! - The transistor begins to discharge the charge stored in the capacitance 31, and N3 begins to change to Low level. Thereafter, when N3 falls to the logic level of the inverter 33, the potential of N4, which was at a low level, begins to rise due to the P c h transistor forming the inverter 33. When the potential of N4 rises to the logic level of the impark 34, the Nch constituting the impark 34
N5, which was at a high level due to the transistor, begins to drop. However, before N5 changes to Low level, the address input signal An Pad changes at time t2, and the pulse signal ATDn is sent from the address transition detection circuit 1, so N3 and N5 become It as in the case of time tl.
N4 and N6 are reset to i g h level and low level. After that, when N1 changes to the I''i g h level, N3, N4 . N5 changes as shown in FIG. 6(a). Here, unlike the case at time tl, N5 is not reset and changes to the Low level, so the output N6 of the inverter 35 changes from Low to High.
Changes to In response to this change in N6, the output TIME of the NAND gate 310 that takes the AND of N1 and N6 becomes High.
It changes from to Low. In the internal control circuit 2', W E
Since P a d is High, the output WE of the inverter 27 is fixed at Low, and the negative AND gate 28
The output APD' is a signal obtained by inverting the output N7 of the timer circuit.

On the other hand, the output ATD of the inverter 25 is the output N of the combining circuit.
It is an inverted signal of l and is an address input signal l\n Pad
Same here! LOW-4High-+L in January.

This becomes a W pulse signal. The ATD and the AP are ATD
and APD' are at High level, Lo
The signal becomes w, as shown in FIG. 6(a). When the control signal SC' is Low, the storage device is in an equalized state, and when it is High, a read circuit such as a sense amplifier operates.

In the control signal SC' shown in FIG. 6(a), the address changes at time t1. The period from t2 until the next rise of SC' is an equalization period, during which the data lines are equalized. The time t from when the address input signal △n Pad changes until the output TIME of the timer circuit 3 changes to Low: If the next address input signal AnP)1 d does not change even after A, PD has elapsed, When the control signal SC falls, the A position becomes equalized. At the same time, the word line WL and column selection signal CT, which select the memory cell shown in FIG. 4, fall, turning off the sense amplifier 96. Time: Selling data is recorded in the latch circuit 10 and passed through the output buffer 11 to 1/
It is output to OP a d. This is the auto power down state.

Next, as shown in FIG. 6(b), W E P a d is l=
.

When the W level is fixed, that is, the memory device is in write mode, the address input signal An Pad is at time t1.
．． Consider the case where the change occurs at t2. The address transition detection circuit 1 and the synthesis circuit and timer circuit 3 in the internal control circuit 2' operate in the same manner as in the read operation shown in FIG. 6(a), and the output ATD of the impark 25 also It is the same as the ATD shown in a). However, WEPad is L
ow is fixed and the output WE of impark 27 is )light
Since it is fixed, the output A of the negative AND gate 28
PD' is fixed to Low, and the output S of internal control circuit 2
C' becomes the inversion of the output ATD of the impark 25. The control signal SC' during the write operation is as shown in FIG. 6(b). In the write state, the storage device does not enter the auto power down state, and the control signal SC' is the address manual signal A.
Used to equalize the data lines in synchronization with n Pad.

[Problem to be Solved by the Invention 1] The conventional semiconductor memory device as described above has the following problems because it is configured as described above.

At time t4, the WEPad shown in FIG. 7 is in the low state.
The time from when the address input signal An Pad changes to when the timer circuit 3 enters the auto power down state is t.
After measuring APD, I/OP a d at time t5.
The write data given to t changes, and it may be time t5.
At time t6, when s has elapsed, WIE P a d goes low.
Let us consider the internal operation of the device in terms of the timing of the change from High to High. As stated in ii'fi, W E P a d
When is at a low level, the output APD' of the negative AND gate shown in FIG. 5 is fixed at low, so the storage device does not enter the auto power down state.
At time t6, when WEPad changes from Low to High (i.e., from writing to reading), APD' changes from Low to High in response to the change of the output WE of the inverter 27 from High to Low, and the control sum signal SC becomes I
It becomes Low from I i g h. Therefore, the storage device enters the auto power town state. At this time, the latch circuit 10 shown in FIG. 4 latches the data appearing in Ilo and Ilo, and the latched data is transferred to the output buffer
1 to I/OP ad.

That is, the data D2 of I/OP a d changed at time t5 passes through the data buffer 13 and is transferred to Ilo·l.
101. If m is reached, write circuit 12 after l1O-r10 → DB -DB → Callum selection game 1-8-B
Even if it is not written into the memory cell in the process of L-B L→memory cell, it is output as data at address At in the read section after time t6. Here, the change timing of l10Pad and W E P a d in order not to write the data of l10Pad after changing to a fixed address
Considering the data hold time (tDH), which is the timing margin for the rise timing of 1, originally I/OP
The time required to transfer the write data from the I/OP ad to the memory cell is tDH, but in the conventional circuit system, the write data transfer time required from the I/OP ad to the output of the data buffer 13 is This has caused a problem in that the tDH characteristics deteriorate.

The present invention was made to solve such problems, and is a conventional auto power Gran 11! that realizes low current consumption and high speed access time. An object of the present invention is to obtain a semiconductor memory device which prevents deterioration of tDH characteristics without overriding the advantage of tIF.

[Means for Solving the Problems 1] A semiconductor memory device of the present invention includes an address transition detection circuit that detects a logic change in at least one address input and generates a pulse signal, and a logic change in at least one address input. In a semiconductor memory device having a timer circuit that starts time measurement from the time when a change occurs and a data latch circuit that latches read data from one selected memory cell, at least a change from a low level to a high level of a write control signal a write control circuit that outputs a signal that changes with a predetermined time delay with respect to the timing;
It is characterized by comprising an internal control circuit that generates an internal control sum signal based on at least the output signal of the address transition detection circuit, the output signal of the timer circuit, and the output signal of the write control circuit.

(Function 1) The semiconductor memory device according to the present invention has W E P a d
When only the signal changes from Low to l-1-1i, the read circuit such as the sense amplifier starts operating and outputs the data of the memo cell to the I/OP ad. Thereafter, the output signal of the write control circuit changes, and the storage device enters an auto power down state in accordance with the change.

[Embodiment 1] FIG. 1 is a diagram showing an embodiment of the present invention, and the address transition detection circuit 1 is completely the same as the conventional device described above.

3 is a timer circuit, which is also the same as the conventional device described above. 2 is an internal control circuit, and pulse signal AT
D1. NCh transistors 21, 22, 23 and Pch transistor 24 for synthesizing ATD2 and ATDn, impark 25 for inverting and waveform shaping the output and outputting ATD, output TIME of timer circuit 3 and write control circuit 20. It consists of a negative AND gate 29 which receives the output WEC, and a NOR gate 26 which receives the output APD of the negative AND 29 and the output ATD of the inverter 25 and outputs an internal control signal SC. Of the internal control circuit 2, Nch l-transistor 21, 22, 23 and Pc
The configurations of the ht-run disk 24 and impark 25 are exactly the same as those of the conventional device, so the output A of the inverter 25
The TD waveform is exactly the same as that of the conventional device. 20 is a write control circuit, which outputs a write control 1lfn signal WEPad.
Impark 201 and Impark 202, which receive , and capacitance C201, C202, C203 and Impark 203.204.205.206 and Nandoge-1 and 2.
Consists of 07. In the write-control circuit 20, the capacitances C201, C202, and C203 and the inverters 203, 204, 205, and 206 are delay circuits that delay the output signal of the inverter 202.

The semiconductor storage device of the present invention constructed as described above operates as follows during reading and writing.

W E P a d shown in FIG. 2(a) is t-Ii g
Address input signal An is fixed at h level at time t1. t
2, the change is detected and the pulse signal ATDn is output from the address transition detection circuit l. The impark 25 in the internal control circuit 2 operates in accordance with the movement of this pulse signal ATDn, and its output ATD is the same as that of the conventional device, and is the same as the ATD shown in FIG. 6(a). Further, the output TIME of the timer circuit 3 is also the same as that of the conventional device, and is the same as the TIME shown in FIG. 6(a). Also, since W E P a d is fixed, the output of the inverter 202 of the write control wholesale circuit 20 is [-fig
h, the output of the inverter 206 that delayed this signal is also H.
Therefore, the output of the Nant gate 207 W E
CIi is fixed at Low. At this time, the output APD of the negative AND gate 29 of the internal control circuit 2 becomes the inverse of the timer circuit TIME. Here, in FIG. 6 showing the circuit of the conventional device, when WEPad is fixed to High, the output of the inverter 27 is fixed to W E I'iLow, and the output APD' of the negative AND gate 28 is the inversion of the output TIME of the timer circuit 310. Therefore,
The APD shown in Figure 2(a) is the APD shown in Figure 6(a).
It is exactly the same as PD'. The output SC of the NOR gate 26 which takes the logical sum of APD and ATD in IJr is the same as that of the conventional device. However, the IQ of the present invention in the read operation is '! The operation in the i position is the same as the operation in the ff next device.

On the other hand, WEPad is fixed at a low level and the address input signal An is at time t1. When there is a change at t2, ATDn and ATl] generated in response to the change and the output TIME of the timer circuit 3 are the same as in the conventional device. Also, W E
When P a d is fixed at Low, the output of the inverter 202 of the write control circuit 20 is fixed at Low, so the output WEC of the Nant gate 2o7 is! (i is fixed to gh, and the output APD of the negative AND gate of the internal control circuit 2 is fixed to Low. Therefore, in the internal i output signal D, the output ATD of the impark 25 is inverted, and the waveform shown in FIG. 2 (b) Here, SC in Fig. 2(b) is as shown in Fig. 6(
sc' shown in b), and the operation of the storage device of the present invention in the write operation is the same as that of the conventional device.

Next, consider the case where there is a timing difference of only ts between the change in I/OP a d and the change in W E P a d as shown in Fig. 3.W E P before time 0 t6
During the adLow period, the write control circuit 2
The output WEC of 0 is fixed to High, and the output APD of the negative AND gate 29 is fixed to Low. ATDn generated by a change in the address input signal An in the 0 time meter 4 is synthesized 1 and inverted in the internal control circuit 2 to become ATD. The Noah Gate 26 is manually powered, but since APD, which is the human power used, is fixed at Low, the internal control signal SC is A.
It is sent as an inverted signal of TD. During the low period of this SC movement, the storage device is in an equalized state, the data bus etc. are equalized, and during the high period, the I /
The write data Di given to OP a d is sent to the data buffer → I10/l10 - write circuit → DB -
The data is written into the memory cell via the path DB-column selection gate→BL-Bt.

On the other hand, the output TIME of the timer circuit 3 is reset to High due to the generation of ATDn by the address input signal An changed at time t4, but becomes Low after the delay time tAPD set in the timer circuit has elapsed. However, at this time, since the output WEC of the storage control circuit ii'i'i20 is fixed at High, the APD is Low.
It remains as it is. Then at &l t 6 W E P
When ad changes from Low to High, inverters 201 and 202 of the write control circuit operate, and the output of the inverter 202 changes from Low to High. Then, the output of this impark 202 changes from low to high, and the capacitances C201 and C20
2, C203 and Impark 203, 204.205.
The output of the inverter 206 becomes Lo after the delay time determined by the circuit constant of the delay circuit configured by the inverter 206 has elapsed.
w to t-1i g h, and this inverter 20
According to the change in the output of NAND 207, the output WEC of NAND 207 becomes H.
From high to low. At this time, since the output TIME of the timer circuit and the output ATD of the impark 25 are Low, the change in WEC causes the APD to become High and the other to Low, and the storage device enters the auto power down state. Here, at time t5, W E P a d becomes L
The time it takes for SC to change from low to high (from low to high) is mainly due to the delay time t in the write control circuit 20.
During this period, which is determined by WEC, the storage device is in a read state that does not enter odd power down. If this tWEC delay time is set to be longer than the time required to output the memory cell data to the I/O Pad via the sense amplifier, latch circuit, and output buffer, the memory cell data will be transferred to the W E Pad. When it changes from Low to High, it will be output to I/OP ad. Therefore, I/OP changed at time t5
Data D2 of a and d passes through the data buffer and becomes Il.
Even if the address A1 has reached oIlo, if it has not been written to the memory cell via the path l1O-Ilo-write circuit → DB・DB → column selection gate → BL-BL, the address A1 will be written in the read period after clock 6. Dl is I as data
/ OP a d.

In the above-mentioned embodiment, a circuit that combines capacitance and a gate that charges and discharges the 11 lines is used for the timer circuit 3 and the delay circuit of the write control circuit. Rough adjustment or other delay means may also be used.

[Effects of the Invention] As described above, according to the present invention, when a storage device changes from a write state to a read state, the data in the memory cell is outputted to the outside via a read circuit such as a sense amplifier. , write signal change timing and W E
It is possible to prevent deterioration of the characteristics of tDI (which is the timing difference in the timing of change of P ad from Low to High).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor device/failure device showing an embodiment of the present invention, and FIGS. 2(a), 3(b) and 3 are timing charts showing operating waveforms of the above embodiment. Fig. 4 is a block diagram of a conventional semiconductor storage device, Fig. 5 is a circuit diagram of a conventional semiconductor memory device, and Figs. 6 (a) and (b).
and FIG. 7 is a timing chart showing the operation of the device shown in FIG. In the figure, 1 is an address transition detection circuit, 2 is an internal control circuit, 3 is a timer circuit, and 20 is a write control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Applicant: Seiko Epson Corporation

Claims (1)

[Claims] (1) an address transition detection circuit that detects a logical change in at least one address input and generates a pulse signal;
In a semiconductor memory device having a timer circuit that starts time measurement from the time when a logical change of at least one address input occurs, and a data latch circuit that latches read data from a selected memory cell, at least a write control signal is detected. a write control circuit that outputs a signal that changes with a predetermined time delay with respect to the change timing from Low level to High level; at least an output signal of the address transition detection circuit; an output signal of the timer circuit; A semiconductor memory device comprising an internal control circuit that generates an internal control signal based on an output signal.