KR20040038126A - Data comparator for decreasing current consumption - Google Patents

Abstract

PURPOSE: A data comparator for reducing a current consumption is provided to prevent DC current(DC) consumption which is required for generating the analog voltage and a reference voltage in response to the input data. CONSTITUTION: A data comparator for reducing a current consumption includes a data input block(310), a reference signal input block(320) and a load block. The data input block(310) is connected to the first nodes and the common node in parallel and is provided with a plurality of first input transistors connected to a plurality of input bits. The reference signal input block(320) is connected to the second nodes and the common node in parallel and is provided with a plurality of input transistors turned on and off by the first power voltage. The load block is connected to the first node, the second node and the first power voltage for making the current to flow into the data input block(310) and the reference signal input block(320). And, the load block generates the output voltage in response to the difference between the current amount flowing into the data input block(310) and the current amount flowing into the reference signal input block(320).

Description

Data comparator for decreasing current consumption

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor circuit that determines whether or not a predetermined number of bits of a specific level is included in input data.

A circuit for receiving digital data consisting of a plurality of bits and determining whether the number of bits having a specific level (for example, a high level) is a predetermined number or more is called a data comparator. For example, the data comparator outputs an output signal of '1' if the number of bits having a high level ('1') is greater than 4 among input data consisting of 8 bits, and an output signal of '0' if it is less than 4, for example. .

Such data comparators are frequently used in data inversion circuits of semiconductor devices.

1 is a circuit diagram showing a data comparator according to the prior art. Referring to this, the data comparator 100 according to the prior art includes a comparison voltage generator 110, a reference voltage generator 120, and an amplifier 130.

The comparison voltage generator 110 includes eight NMOS transistors WN connected in parallel with a PMOS transistor WP. The PMOS transistor WP has its source connected to a power supply voltage, its gate connected to ground, and its drain connected to a comparison voltage VCOM terminal. Each of the NMOS transistors WN is connected to a drain thereof at a comparison voltage VCOM terminal and a source thereof to ground. The gate receives input data XO1 to XO8, respectively. Therefore, the NMOS transistor WN is turned on / off according to the level of the data XO1 to XO8 input to the gate. The larger the turn-on number of the NMOS transistor WN, the lower the level of the comparison voltage VCOM.

The reference voltage generator 120 has the same configuration as the comparison voltage generator 110. However, the size of one of the eight NMOS transistors WN and WN ′ is different from that of the other NMOS transistor WN. Small compared to the size of). In addition, the gates of the four NMOS transistors including the small NMOS transistor WN 'are connected to a power supply voltage, and the gates of the remaining four NMOS transistors are connected to ground. Thus, the NMOS transistors whose gates are connected to the power supply voltages are turned on to determine the level of the reference voltage VREF.

The amplifier 130 receives the comparison voltage VCOM output from the comparison voltage generator 110 and the reference voltage VREF output from the reference voltage generator 120, so that the comparison voltage VCOM is the reference voltage VREF. If greater than), output signal VOUT of high level is output, and if output voltage VCOM is less than reference voltage VREF, output signal VOUT of low level is output.

However, as shown in FIG. 1, since the PMOS transistor WP and the NMOS transistor connected to the power supply voltage of the reference voltage generator 120 are always turned on while the power supply voltage is supplied, the DC voltage from the power supply voltage to ground may be reduced. DC) a current path is formed. In addition, if one bit of the input data is high level in the comparison voltage generator 110, a direct current (DC) current path is formed from the power supply voltage to the ground similarly to the reference voltage generator 120. The current consumed by the comparison voltage generator 110 increases as the number of bits of the high level in the input data increases.

As described above, in the data comparator 130 according to the related art, DC current consumption is generated to generate the comparison voltage VCOM and the reference voltage VREF, which are analog voltages.

2A and 2B show examples of the amplifier 130 shown in FIG. 1. The amplifier 130A shown in FIG. 2A is called a latch-type amplifier or a cross-couple differential amplifier. Referring to this, the latch sense amplifier 130A includes a cross-coupled load unit PL1, PL2, NL1, NL2, an input transistor NI1, NI2, an equalizer PE1, PE2, PE3, PE4, and an operation control transistor ( NC).

The comparison voltage VCOM generated by the comparison voltage generator 110 (in FIG. 1) is input to the gate of one input transistor NI1, and the reference voltage VREF generated by the reference voltage generator 120 (FIG. 1). This is input to the gate of the other input transistor NI2.

At this time, when the comparison voltage, which is analog voltages, and the level of the reference voltage are different, this causes a voltage difference between the nodes D1 and D2 and also a voltage difference between the output nodes DO and DOB. The small voltage difference between the output nodes DO, DOB is further amplified by the cross-coupled load parts PL1, PL2, NL1, NL2. The voltage at the output node DO becomes the output signal VOUT.

The equalizers PE1, PE2, PE3, PE4, in response to the operation control signal PCOMP, equalize the nodes D1, D2 to the same voltage level, and also output nodes DO, DOB to the same voltage. Equalizes to level. The operation control signal PCOMP is a signal for controlling the operation of the amplifier 130A. When the operation control signal is activated at a high level, the amplifier 130A performs an amplification operation.

The operation control transistor NC is disposed between the node D3 and the ground. When the operation control signal PCOMP is activated to a high level, the operation control transistor NC is turned on to operate the amplifier 130A.

On the other hand, the amplifier shown in Fig. 2B is a current-mirror type differential amplifier. Referring to this, the current-mirror differential amplifier 130B includes load parts PL3 and PL4, input transistors NI1 and NI2, and an operation control transistor NC.

The comparison voltage VCOM generated by the comparison voltage generator 110 (in FIG. 1) is input to the gate of one input transistor NI1, and the reference voltage VREF generated by the reference voltage generator 120 (FIG. 1). This is input to the gate of the other input transistor NI2.

In this case, when the comparison voltages, which are analog voltages, and the levels of the reference voltages are different, this causes a voltage difference between the output nodes DO and DOB. The voltage at the output node DO becomes the output signal VOUT.

The operation control transistor NC is disposed between the node D3 and the ground. When the operation control signal PCOMP is activated to a high level, the operation control transistor NC is turned on to operate the amplifier 130B.

As described above, the data comparator 100 according to the related art generates a reference voltage VCOM having a predetermined analog voltage level, and further, compares the comparison voltage VREF which is an analog voltage according to the input data XO1 to XO8. Make and compare and amplify both voltages (reference voltage and comparison voltage). Therefore, not only current consumption occurs in the process of comparing and amplifying both voltages (reference voltage and comparison voltage), but also DC current path is formed in the process of making analog voltage (reference voltage and comparison voltage), thereby causing unnecessary current consumption. .

Accordingly, the technical problem to be achieved by the present invention is to provide a data comparator that eliminates unnecessary DC current consumption and performs a stable data comparison.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a data comparator according to the prior art.

2A and 2B are circuit diagrams illustrating examples of the amplifier illustrated in FIG. 1.

3 is a circuit diagram illustrating a data comparator according to a first embodiment of the present invention.

4 is a circuit diagram illustrating a data comparator according to a second embodiment of the present invention.

5 is a circuit diagram illustrating a data comparator according to a third embodiment of the present invention.

6 is a circuit diagram illustrating a data comparator according to a fourth embodiment of the present invention.

7A and 7B are diagrams showing examples of using the data comparator of the present invention in a data inversion circuit.

According to an aspect of the present invention, a data comparator includes a plurality of first input transistors connected in parallel between a predetermined first node and a common node and turned on / off each of a plurality of input bits. A data input unit; A reference signal input unit including a plurality of second input transistors connected in parallel between a predetermined second node and the common node and turned on / off at a predetermined first power supply voltage; And a current connected to the first node, the second node, and the first power supply voltage and flowing a current from the first power supply voltage to the data input unit and the reference signal input unit, respectively, the amount of current flowing through the data input unit and the reference signal. And a load unit generating an output voltage in response to a difference in the amount of current flowing in the input unit.

Preferably, the data input unit includes the M first input transistors that are turned on / off in response to each of the M (M is a natural number of two or more) input bits, and the reference signal input unit includes the first input transistors. And N (North natural numbers) second input transistors gated in response to a power supply voltage, respectively, and further include MN third input transistors gated in response to a second power supply voltage, respectively.

According to another aspect of the present invention, a data comparator is connected in parallel between a predetermined first node and a common node in response to each bit of input data consisting of M (M is a natural number of two or more) bits. A data input unit including the M first input transistors turned on / off; A reference signal input section including the M second input transistors connected in parallel between a predetermined second node and the common node and turned on / off in response to each inversion bit of the input data; And a current connected to the first node, the second node, and the first power supply voltage to flow current from the first power supply voltage to the data input unit and the reference signal input unit, respectively, and the current flowing through the data input unit and the reference signal input unit. And a load unit for generating an output voltage in response to the difference in the amount of current flowing through the.

Preferably, the data input unit further includes a third input transistor turned on / off in response to the first power supply voltage, and the reference signal input unit is turned on / turned off in response to a second power supply voltage. It further includes a transistor.

A data comparator according to another aspect of the present invention for achieving the technical problem is a circuit for determining whether the number of bits having a first logic level among the input data consisting of a plurality of bits is more than a predetermined number, each of the input data A first differential input receiving a bit and a second differential input receiving an inverted bit of each bit of the input data, the difference between the amount of current flowing through the first differential input and the amount of current flowing through the second differential input A differential amplifier for generating a differential output signal in response to said first differential input, said first differential input section comprising a plurality of first input transistors connected in parallel and turned on / off in response to each bit of said input data, A plurality of second differential inputs connected in parallel and each turned on / off in response to the inversion bits; Two input transistors.

Preferably, the first differential input unit further comprises a third input transistor turned on / off in response to a predetermined first power supply voltage, and the second differential input unit is turned on / off in response to a predetermined second power supply voltage. And further comprising a fourth input transistor turned off.

A data comparator according to another aspect of the present invention for achieving the technical problem is a circuit for determining whether the number of bits having a first logic level among the input data consisting of a plurality of bits is more than a predetermined number, each of the input data A first differential input receiving a bit and a second differential input receiving a predetermined first power supply voltage, the second differential input receiving a bit, in response to a difference between the amount of current flowing through the first differential input and the amount of current flowing through the second differential input; A differential amplifier for generating a differential output signal, wherein the first differential input section includes a plurality of first input transistors connected in parallel and turned on / off in response to each bit of the input data, and wherein the second differential A plurality of second input transistors connected in parallel and turned on / off in response to the first power voltage, respectively. Includes sites.

Preferably, the second differential input unit further includes a third input transistor turned on / off in response to a predetermined second power supply voltage.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a circuit diagram illustrating a data comparator 300 according to a first embodiment of the present invention.

Referring to this, the data comparator 300 is implemented in the form of one differential amplifier. In this embodiment, the data comparator 300 is implemented in the form of a latch-type differential amplifier. In detail, the data comparator 300 includes a data input unit 310, a reference signal input unit 320, a load unit, an equalizer, and an operation control transistor NC.

The data input unit 310 includes a plurality of NMOS transistors WN connected in parallel. The number of NMOS transistors WN is determined according to the number of bits of the input data XO1 to XO8. In the present embodiment, it is assumed that the number of bits of the input data XO1 to XO8 is eight. Therefore, the data input unit 310 is composed of eight NMOS transistors WN. Each of the NMOS transistors WN has a drain connected to the first node D1 and a source thereof connected to the common node D3. The gate receives the bits XO1 to XO8 of the input data. Therefore, the NMOS transistor WN is turned on / off according to the level of the data XO1 to XO8 input to the gate.

The reference signal input unit 320 has the same configuration as the data input unit 310. However, the size of one of the eight NMOS transistors WN and WN 'is about 1/2 of the size of the other NMOS transistors WN. The gates of the four NMOS transistors including the NMOS transistors WN 'having a size 1/2 are connected to a power supply voltage, and the gates of the remaining four NMOS transistors are connected to ground. Each of the NMOS transistors WN and WN 'is connected to a drain thereof to the second node D2 and a source thereof to the common node D3.

The load unit includes cross-coupled first and second load PMOS transistors PL1 and PL2 and first and second load NMOS transistors NL1 and NL2.

The first load PMOS transistor PL1 is between the power supply voltage VDD and the inverted output node DOB, and the second load PMOS transistor PL2 is between the power supply voltage VDD and the non-inverting output node DO. The gate and its drain are cross-coupled with each other. The first load NMOS transistor NL1 is between the inverted output node DOB and the first node D1, and the second load NMOS transistor NL2 is the non-inverted output node DO and the second node D2. Formed between the gate and its drain are mutually cross-coupled.

When the operation control transistor NC, which will be described later, is turned on, a load causes a current to flow from the power supply voltage VDD to the ground through each of the data input unit 310 and the reference signal input unit 320. The output voltage VOUT, which is an analog signal, is generated in response to the difference between the amount of current flowing through the data input unit 310 and the amount of current flowing through the reference signal input unit 320.

The equalizer includes a plurality of PMOS transistors PE1, PE2, PE3, PE4. The PMOS transistor PE1 is between an inverted output node DOB and a non-inverted output node DO and a PMOS transistor (PMOS transistor). PE2 is between the first node D1 and the second node D2, PMOS transistor PE3 is between the power supply voltage VDD and the inverted output node DOB, and PMOS transistor PE4 is It is formed between the power supply voltage VDD and the non-inverting output node DO. Each PMOS transistor PE1, PE2, PE3, PE4 is turned on in response to an operation control signal PCOMP to equalize the first and second nodes D1 and D2 to the same voltage level, and also to invert the output node. It equalizes DOB and non-inverting output node DO to the same voltage level. The operation control signal PCOMP is a signal for controlling the overall operation of the data comparator 300. When the operation control signal is activated at a predetermined level (high level in this embodiment), the data comparator 300 performs a comparison operation. .

The PMOS transistors PE1, PE2, PE3, and PE4 are turned on when the operation control signal PCOMP is at a low level to perform an equalizing operation.

It is preferable that the operation control transistor NC is an NMOS transistor whose drain is connected to the common node D3, its source is connected to ground, and receives the operation control signal PCOMP as its gate. Therefore, the operation control transistor NC is turned on when the operation control signal PCOMP is activated to a high level, so that the data comparator 300 operates.

The operation of the data comparator 300 shown in FIG. 3 will now be described.

First, it is assumed that the number of bits having a high level '1' among the bits of the input data XO1 to XO8 is four. When the number of bits having a high level among the input data XO1 to XO8 is 4, the number of transistors turned on in the data input unit 310 and the number of transistors turned on in the reference signal input unit 320 are the same. However, since the size of one of the four transistors turned on in the reference signal input unit 320 is 1/2 the size of the other transistor, the effective turn-on resistance of the data input unit 310 is the reference signal input unit 320. It is smaller than the effective turn-on resistance of. That is, the conductance of the data input unit 310 is larger than the conductance of the reference signal input unit 320. Accordingly, a relatively large amount of current flows toward the data input unit 310 compared to the reference signal input unit 320, so that the voltage of the first node D1 is relatively lower than that of the second node D2, and also inverted. The voltage of the output node DOB is relatively lower than the output voltage VOUT, which is the voltage of the non-inverting output node DO. As such, when a slight voltage difference occurs between the non-inverting output node DO and the inverting output node DOB, the voltage difference is further increased by the load transistors PL1, PL2, NL1, and NL2. As a result, the output voltage VOUT becomes high level.

If the number of bits having a high level among the input data XO1 to XO8 is greater than four, the number of transistors turned on in the data input unit 310 is greater than the number of transistors turned on in the reference signal input unit 320. Therefore, the effective turn-on resistance of the data input unit 310 is smaller than the effective turn-on resistance of the reference signal input unit 320. Therefore, the amount of current flowing through the data input unit 310 increases compared to the amount of current flowing through the reference signal input unit 320. Accordingly, the voltage of the inverted output node DOB is relatively lower than the output voltage VOUT, which is the voltage of the non-inverted output node DO, so that the output voltage VOUT becomes a high level.

On the other hand, when the number of bits having a high level among the input data XO1 to XO8 is less than four, the number of transistors turned on in the data input unit 310 is smaller than the number of transistors turned on in the reference signal input unit 320. Therefore, the effective turn-on resistance of the data input unit 310 is larger than the effective turn-on resistance of the reference signal input unit 320. Accordingly, the voltage of the inverted output node DOB becomes relatively high compared to the output voltage VOUT, which is the voltage of the non-inverted output node DO, so that the output voltage VOUT becomes low level.

As described above, according to the present invention, the data comparator 300 operates only when the operation control signal PCOMP is activated at a high level, and current consumption occurs only while the data comparator 300 operates.

4 is a circuit diagram illustrating a data comparator 400 according to a second embodiment of the present invention. The data comparator 400 according to the second embodiment of the present invention is implemented in the form of a latch type differential amplifier similarly to the data comparator 300 according to the first embodiment of the present invention. Thus, the data comparator 400 has a configuration similar to that of the data comparator 300 shown in FIG. 3. The difference lies in the data input unit 410 and the reference signal input unit 420.

The data input unit 410 and the reference signal input unit 420 are each composed of nine NMOS transistors WN. Each NMOS transistor WN has the same size. Each of the NMOS transistors WN of the data input unit 410 has a drain connected to the first node D1 and a source thereof connected to the common node D3. One gate of the nine NMOS transistors WN of the data input unit 410 is connected to a power supply voltage, and the remaining eight NMOS transistors receive input data XO1 to XO8 through the gate, respectively.

Each of the NMOS transistors WN of the reference signal input unit 420 has a drain connected to the second node D2 and a source connected to the common node D3. One gate of the nine NMOS transistors WN of the reference signal input unit 320 is connected to the ground, and the remaining eight NMOS transistors receive the inversion signals XO1B to XO8B of the input data, respectively. .

Therefore, if the number of bits having a high level among the input data XO1 to XO8 is 4 or more, the conductance of the data input unit 410 is larger than the conductance of the reference signal input unit 420. In this case, the output voltage VOUT becomes high level.

On the other hand, if the number of bits having a high level among the input data XO1 to XO8 is less than 4, that is, 3 or less, the conductance of the data input unit 310 is smaller than the conductance of the reference signal input unit 420. In this case, the output voltage VOUT goes low.

5 is a circuit diagram illustrating a data comparator 500 according to a third embodiment of the present invention. Referring to this, the data comparator 500 is implemented in the form of a current-mirror type differential amplifier. In detail, the data comparator 500 includes a data input unit 310, a reference signal input unit 320, a load unit, and an operation control transistor NC.

Since the data input unit 310 and the reference signal input unit 320 are the same as the data input unit 310 and the reference signal input unit 320 illustrated in FIG. 3, the detailed description thereof will be omitted.

The rod part includes third and fourth load PMOS transistors PL3 and PL4 configured as current mirrors.

The third load PMOS transistor PL3 is formed between the power supply voltage VDD and the inverted output node DOB, and the fourth load PMOS transistor PL4 is formed between the power supply voltage VDD and the non-inverting output node DO. Formed between, the gates of which are interconnected. In addition, the gate and the drain of the fourth load PMOS transistor PL4 are connected.

When the operation control transistor NC is turned on, the load causes a current to flow from the power supply voltage VDD to the ground through each of the data input unit 310 and the reference signal input unit 320. The output voltage VOUT, which is an analog signal, is generated in response to the difference between the amount of current flowing through the data input unit 310 and the amount of current flowing through the reference signal input unit 320.

Since the configuration and function of the operation control transistor NC are the same as those of the operation control transistor NC shown in FIGS. 3 and 4, a detailed description thereof will be omitted.

The operation of the data comparator 500 shown in FIG. 5 is also similar to the operation of the data comparator shown in FIG. 3.

First, it is assumed that the number of bits having a high level ('1') among the bits of the input data is four or more. In this case, the effective turn-on resistance of the data input unit 310 is smaller than the effective turn-on resistance of the reference signal input unit 320. That is, the conductance of the data input unit 310 is larger than the conductance of the reference signal input unit 320. Accordingly, a large amount of current flows toward the data input unit 310 compared to the reference signal input unit 320, so that the voltage of the inverted output node DOB is relatively compared to the output voltage VOUT, which is the voltage of the output node DO. Lowers. As a result, the output voltage VOUT becomes high level.

6 is a circuit diagram illustrating a data comparator 600 according to a fourth embodiment of the present invention. The data comparator 600 according to the fourth embodiment of the present invention is implemented in the form of a current mirror type differential amplifier similarly to the data comparator 500 according to the third embodiment of the present invention. Thus, the data comparator 600 has a configuration similar to that of the data comparator 500 shown in FIG. 5. The difference lies in the data input unit 410 and the reference signal input unit 420.

However, since the data input unit 410 and the reference signal input unit 420 of the data comparator 600 are the same as the data input unit 410 and the reference signal input unit 420 illustrated in FIG. 4, the detailed description thereof will be omitted. Also, like the rod shown in FIG. 5, the rod includes the third and fourth load PMOS transistors PL3 and PL4 configured as current mirrors.

As described above, the data comparator of the present invention implements the data comparator in the form of an amplifier by configuring the part receiving the input data as an input part of the amplifier. Therefore, the present invention does not generate and compare / amplify analog voltages and reference voltages according to input data as in the data comparator according to the prior art, but instead inputs the input data and its inverted data (or a predetermined power supply voltage) into the input of the amplifier. Receive and compare them. Therefore, according to the present invention, it is possible to prevent the DC current that is unnecessarily consumed to generate the analog voltage and the reference voltage according to the input data.

The data comparator of the present invention can be used in various devices including data inversion circuits of semiconductor devices.

One method of data inversion is to compare the data of a predetermined number of bits (typically 8 bits) to be outputted from the semiconductor device with the data previously output bit by bit, so that the number of toggled bits is more than half. In this case, the current output data is inverted and output. In this method, the number of bits toggled compared to the previous data is less than half of the total number of bits, which has the advantage of reducing simultaneous switching noise (hereinafter referred to as SSN).

Another method of data inversion is to invert all of the currently output data when the number of bits having a specific level (for example, a low level) among the data of a predetermined number of bits (generally 8 bits) to be output is half or more. In this method, the number of bits having a specific level is less than half of the total number of bits, which has the advantage of reducing the current consumption generated only at the output of the data of a specific level.

A circuit for performing the data inversion method as described above is a data inversion circuit.

7A and 7B are diagrams showing examples of using the data comparator of the present invention in a data inversion circuit. The data inversion circuit 700 illustrated in FIG. 7A includes a comparator 710, a data comparator 300 or 500 and an inverter 720 according to the first or third embodiment of the present invention. In this example, it is assumed that inversion / non-inversion is performed on 8-bit data FDO1 to FDO8 output to eight data output pads.

The comparator 710 is implemented with eight exclusive ORs (hereinafter referred to as XOR) gates. The comparator 710 corresponds to previously output data D01 to D08 of the current data FDO1 to FDO8 read from the memory cell. Compare bit by bit.

The XOR gate of the comparator 710 determines whether the two bits are the same by exclusively ORing the current data FDO1 to FDO8 and the previous data DO1 to DO8 for each corresponding bit. Output signals XO1 to XO8 are outputted, output signal XO1 to XO8 of '1' is not equal.

The data comparator 300 or 500 receives the output signals XO1 to XO8 of the comparator 110 as input data, and determines whether the number of '1's is 4 or more. If 4 or more, the high level output voltage VOUT is output, otherwise the low level output voltage VOUT is output. Since the output voltage VOUT is an analog signal, a buffer 730 may be further provided at the output terminal of the data comparator 300 or 500 in order to convert the output voltage VOUT into a digital signal having a CMOS level.

The signal converted to the CMOS level through the buffer 730 is referred to as a parity bit (S).

The inverter 120 is implemented with eight XOR gates. The XOR gate of the inverter 120 outputs the current data FDO1 to FDO8 by performing an exclusive OR on each of the parity bits S. FIG. Therefore, if the parity bit S is '1', the current data FDO1 to FDO8 are inverted and output. If the parity bit S is '0', the current data FDO1 to FDO8 is not inverted.

The data inversion circuit 800 shown in FIG. 7B includes a comparator 810, a data comparator 400 or 600 and an inverter 720 according to a second or fourth embodiment of the present invention. Here, it is also assumed that inversion / non-inversion of the 8-bit data FDO1 to FDO8 outputted to the eight data output pads is performed.

The comparator 810 is implemented with eight XOR gates and eight inverters. The XOR gate of the comparator 810 determines whether the two bits are the same by exclusively ORing the current data FDO1 to FDO8 and the previous data DO1 to DO8 for each corresponding bit. Output signals XO1 to XO8 are outputted, output signal XO1 to XO8 of '1' is not equal. The eight inverters output the inverted signals XO1B to XO8B of the respective output signals XO1 to XO8.

The data comparator 400 or 600 receives the output signals XO1 to XO8 and the inverted output signals XO1B to XO8B of the comparator 810, so that the number of '1' of the output signals XO1 to XO8 is received. Determine if is 4 or more. If 4 or more, the high level output voltage VOUT is output, otherwise the low level output voltage VOUT is output. Since the output voltage VOUT is an analog signal, a buffer 730 is further provided at an output terminal of the data comparator 400 or 600 in order to convert the output voltage VOUT into a digital signal having a CMOS level. The buffer 730 converts the output voltage VOUT into a CMOS signal and outputs the parity bit S. FIG.

The inverter 120 outputs the current data FDO1 to FDO8 by performing an exclusive OR on the parity bits S, respectively.

Since the current consumption of the data comparator according to the present invention is reduced as compared with the prior art, when the present invention is used in the data inversion circuit, the overall current consumption of the data inversion circuit is reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, in embodiments of the present invention, the number of transistors constituting the reference signal input unit is the same as the number of transistors constituting the data input unit. However, the number / size of transistors constituting the reference signal input unit may be configured differently from the number / size of transistors constituting the data input unit. The number of transistors constituting the data input unit may also vary according to the number of bits of the input data. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, input data and its inverted data (or a predetermined power supply voltage) are directly received at an input of an amplifier and in response thereto generate an output signal. Therefore, according to the present invention, it is possible to prevent the DC current that is unnecessarily consumed to generate the analog voltage and the reference voltage according to the input data. Therefore, the current consumption of the data comparator is reduced.

Claims (24)

A data input unit including a plurality of first input transistors connected in parallel between a predetermined first node and a common node, each of the first input transistors being turned on / off in a plurality of input bits; A reference signal input unit including a plurality of second input transistors connected in parallel between a predetermined second node and the common node and turned on / off at a predetermined first power supply voltage; And A current connected to the first node, the second node, and the first power supply voltage and flowing a current from the first power supply voltage to the data input unit and the reference signal input unit, respectively, and an amount of current flowing in the data input unit and the reference signal input unit; And a load section for generating an output voltage in response to a difference in the amount of current flowing in the stream. The method of claim 1, The data input unit includes the M first input transistors turned on / off in response to each of the M (M is a natural number of two or more) input bits, The reference signal input unit includes N (one or more natural numbers) second input transistors gated in response to the first power supply voltage, respectively, and further includes MN third input transistors gated in response to the second power supply voltage, respectively. Data comparator, characterized in that it comprises. The method of claim 2, M is 8, N is 4, Except for one of the first and third input transistors and the second input transistor, the second input transistor has substantially the same size, and one of the second input transistors has a smaller size than the remaining transistors. Data comparator. The method of claim 1, wherein the rod portion A first PMOS load transistor disposed between the first power supply voltage and an inverted output node; A first NMOS load transistor disposed between the inverted output node and the first node; A second PMOS load transistor disposed between the first power supply voltage and a non-inverting output node; And A second NMOS load transistor disposed between the non-inverting output node and the second node, The gate and the drain of the first and second PMOS load transistors are cross-coupled to each other, the gate and the drain of the first and second NMOS load transistors are mutually coupled to each other, And the output voltage is output to the non-inverting output node and / or the inverting output node. The data comparator of claim 4, wherein the data comparator And in response to the operation control signal, further comprising an equalizer that substantially equalizes the voltages of the inverted output node and the non-inverted output node, and substantially equals the first node and the second node. Characteristic data comparator. The method of claim 5, wherein the data comparator A first equalizing transistor disposed between the inverted output node and the non-inverted output node and turned on / off in response to the operation control signal; A second equalizing transistor disposed between the first node and the second node and turned on / off in response to the operation control signal; A third equalizing transistor disposed between the inverted output node and the first power supply voltage and turned on / off in response to the operation control signal; And And a fourth equalizing transistor disposed between the non-inverting output node and the first power voltage and turned on / off in response to the operation control signal. The method of claim 1, wherein the rod portion A first load transistor disposed between the first power supply voltage and the first node; And A second load transistor disposed between the first power supply voltage and the second node, The first and second load transistors are configured in a current mirror type, And the output voltage is output to the first node and / or the second node. The method of claim 1, wherein the data comparator And an operation control transistor disposed between the common node and the second power supply voltage and turned on / off in response to a predetermined operation control signal. A data input unit comprising the M first input transistors connected in parallel between a predetermined first node and a common node and turned on / off in response to each bit of input data consisting of M (M is two or more natural numbers) bits ; A reference signal input section including the M second input transistors connected in parallel between a predetermined second node and the common node and turned on / off in response to each inversion bit of the input data; And A current connected to the first node, the second node, and a first power supply voltage and flowing a current from the first power supply voltage to the data input unit and the reference signal input unit, respectively, and an amount of current flowing in the data input unit and the reference signal input unit; And a load comparator for generating an output voltage in response to a difference in the amount of current flowing. The method of claim 9, The data input unit further includes a third input transistor turned on / off in response to the first power supply voltage. The reference signal input unit further comprises a fourth input transistor turned on / off in response to a second power supply voltage. The method of claim 10, M is 8, N is 4, and the first, second, third and fourth input transistors have substantially the same size. The method of claim 9, wherein the rod portion A first PMOS load transistor disposed between the first power supply voltage and an inverted output node; A first NMOS load transistor disposed between the inverted output node and the first node; A second PMOS load transistor disposed between the first power supply voltage and a non-inverting output node; And A second NMOS load transistor disposed between the non-inverting output node and the second node, The gate and the drain of the first and second PMOS load transistors are cross-coupled to each other, the gate and the drain of the first and second NMOS load transistors are mutually coupled to each other, And the output voltage is output to the non-inverting output node and / or the inverting output node. 13. The apparatus of claim 12, wherein the data comparator And in response to the operation control signal, further comprising an equalizer that substantially equalizes the voltages of the inverted output node and the non-inverted output node, and substantially equals the first node and the second node. Characteristic data comparator. The data comparator of claim 13, wherein the data comparator A first equalizing transistor disposed between the inverted output node and the non-inverted output node and turned on / off in response to the operation control signal; A second equalizing transistor disposed between the first node and the second node and turned on / off in response to the operation control signal; A third equalizing transistor disposed between the inverted output node and the first power supply voltage and turned on / off in response to the operation control signal; And And a fourth equalizing transistor disposed between the non-inverting output node and the first power voltage and turned on / off in response to the operation control signal. The method of claim 9, wherein the rod portion A first load transistor disposed between the first power supply voltage and the first node; And A second load transistor disposed between the first power supply voltage and the second node, The first and second load transistors are configured in a current mirror type, And the output voltage is output to the first node and / or the second node. 10. The apparatus of claim 9, wherein the data comparator And an operation control transistor disposed between the common node and the second power supply voltage and turned on / off in response to a predetermined operation control signal. In the data comparator for determining whether the number of bits having a first logic level among the input data consisting of a plurality of bits is more than a predetermined number, A first differential input unit configured to receive each bit of the input data and a second differential input unit configured to receive inverted bits of each bit of the input data, the current amount flowing through the first differential input unit and the second differential input unit And a differential amplifier for generating a differential output signal in response to a difference in the amount of current flowing through the The first differential input unit includes a plurality of first input transistors connected in parallel and turned on / off in response to each bit of the input data, And the second differential input unit includes a plurality of second input transistors connected in parallel and turned on / off each in response to the inversion bit. The method of claim 17, The first differential input unit further includes a third input transistor turned on / off in response to a predetermined first power supply voltage. And the second differential input unit further comprises a fourth input transistor turned on / off in response to a predetermined second power supply voltage. 18. The apparatus of claim 17, wherein the differential amplifier is A data comparator characterized by a latch-type. 18. The apparatus of claim 17, wherein the differential amplifier is A data comparator, characterized in that the current-mirror type. In the data comparator for determining whether the number of bits having a first logic level among the input data consisting of a plurality of bits is more than a predetermined number, A first differential input unit for receiving each bit of the input data and a second differential input unit for receiving a predetermined first power supply voltage, the amount of current flowing through the first differential input unit and the amount of current flowing through the second differential input unit A differential amplifier generating a differential output signal in response to a difference of The first differential input unit includes a plurality of first input transistors connected in parallel and turned on / off in response to each bit of the input data, And the second differential input unit includes a plurality of second input transistors connected in parallel and turned on / off in response to the first power supply voltage, respectively. The method of claim 21, wherein the second differential input unit And a third input transistor turned on / off in response to a predetermined second power supply voltage. The method of claim 21, wherein the differential amplifier A data comparator characterized by a latch-type. The method of claim 22, wherein the differential amplifier A data comparator, characterized in that the current-mirror type.