KR20000059994A - Output driving circuit - Google Patents

Abstract

PURPOSE: An output driving circuit is provided to improve operating characteristics of a semiconductor memory device and to increase speed of outputting data. CONSTITUTION: An output driving circuit comprises an output buffer part(25), output driving part(26), and a regulator part(29). The output buffer part(25) stores output data from a sense amplifier and outputs the stored output data in response to an enable signal applied through an inverter(24). The output driving part(26) outputs data transferred from the output buffer part(25) to the exterior. The regulator part(29) sets voltage of an output terminal of the output driving part(26) to a tri-state voltage, and maintains the voltage of the output terminal at a constant level forcibly in a case when the output buffer part(25) and the output driving part(26) are not operated.

Description

Output driving circuit {OUTPUT DRIVING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an output driving circuit suitable for improving the operation speed of an output driver for outputting data sensed by a sense amplifier to the outside.

Hereinafter, an output driving circuit according to the prior art will be described with reference to the accompanying drawings.

In general, an output driving circuit can be classified into an output buffer unit and an output driving unit.

1 is a block diagram of an output driving circuit according to the prior art.

As shown in FIG. 1, the output buffer 11 and the output driver 13 are largely configured as follows.

A first inverter 10 for inverting the output buffer enable signal Benable, a first logic gate 11a for performing logic operation on the output of the sense amplifier and the output of the first inverter 10 as an input, A second inverter for inverting the output of the first inverter 10

11b, between the second logic gate 11c for performing a logical operation by inputting the output of the second inverter 11b and the output of the sense amplifier, between the power supply voltage terminal VDD and the ground voltage terminal VSS. A PMOS transistor 13a connected in series and controlled by an output of the second logic gate 11c, and connected in series with the PMOS transistor 13a, and connected to an output of the first logic gate 11a. It consists of the NMOS transistor 13b controlled by.

Referring to the operation of the conventional output drive circuit configured as described above is as follows.

As shown in FIG. 1, when the output buffer 11 is enabled by an output buffer enable signal (Benable), data output from the sense amplifier is transferred to the output driver 13 through the output buffer 11. do.

When the output buffer enable signal transitions from low to high, the node N5 goes low and the node N6 goes high so that the output data of the sense amplifier is connected to the first logic gate 11a. It is transmitted to the output driver 13 through the second logic gate 11c.

If the output buffer enable signal transitions from the enabled state to the disabled state, that is, from the high level to the low level, the node N5 transitions to the high level, and the node N6 transitions to the low level so that the sense amplifier Regardless of the output signal, the node N7 goes high and the node N8 goes low to disable the output buffer 11 and the output driver 13.

As described above, the conventional output driver circuit controls the enable and disable of the output buffer 11 and the output driver 13 by the output buffer enable signal (Benable) to determine whether to output the sense amplifier output data.

However, in the conventional output driver circuit as described above, since the output Dout of the output driver is always full swing between the ground voltage and the power supply voltage, the ground bouncing is increased, thereby degrading the device characteristics. In addition, the output speed will be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide an output driving circuit suitable for improving the output speed of the output driving unit and improving the characteristics of the device.

1 is a block diagram of an output driving circuit according to the prior art

2 is a block diagram of an output driving circuit of the present invention

3 is an operation timing diagram of an output driving circuit according to the present invention.

Explanation of symbols for main parts of the drawings

25: output buffer 26: output driver

29 regulator unit

The output driving circuit of the present invention for achieving the above object is an output buffer unit for storing the output data of the sense amplifier and operating by the enable signal, and outputs the data transmitted from the output buffer unit to the outside A regulator for setting an output driver and a voltage of an output terminal of the output driver as a tri-state voltage and forcibly maintaining a voltage at the output terminal of the output driver when the output buffer unit and the output driver are not operated. Characterized in that it comprises a.

Hereinafter, the output drive circuit of the present invention will be described.

First, the output driving circuit of the present invention attempts to improve the output speed of the output driving unit by setting the tri-state voltage of the output data.

In addition, when the output buffer and the output driver do not operate, the output buffer and the output driver are forcibly kept at the output voltage state by separate control voltages (regulator voltages).

Here, the present invention uses a differential amplifier to set the voltage of the output data to a tri-state voltage.

2 is a block diagram of an output driving circuit according to an embodiment of the present invention.

One embodiment of the present invention is largely composed of the output buffer 25, the output driver 26, the regulator (Regulater) unit 29 will be described in more detail as follows.

As shown in FIG. 2, a first inverter 21 for inverting a regulator enable signal Renable, a first logic for logically computing an output buffer enable signal Benable and an output of the first inverter 21. A second inverter 23 for inverting the output of the gate 22, the first logic gate 22, a third inverter 24 for inverting the output buffer enable signal Benable, and the third inverter 24. Of the fourth inverter 25a for inverting the output of the second inverter 25a and the second logic gate 25b and the third inverter 24 for performing logical operation with the output of the fourth inverter 25a and the output of the sense amplifier as inputs. An output buffer unit 25 including a third logic gate 25c for performing a logic operation on the output and the output of the sense amplifier as an input, and is connected in series between a power supply voltage terminal VDD and a ground voltage terminal VSS. The first transistor 26a controlled by the output of the second logic gate 25b and the An output driver 26 comprising a second transistor 26b connected in series with the first transistor 26a and controlled by the output of the third logic gate 25c, a power supply voltage terminal VDD and a ground voltage terminal ( A third transistor 27 connected between VSS and controlled by an output signal of the second inverter 23, a fifth inverter 28 for inverting the output of the second inverter 23, and the third transistor. The differential amplifier 29a is connected in series with the differential amplifier 29a and the third transistor 27 to compare the output voltage of the 27 and the output voltage of the fifth inverter 28 and amplify and output the difference. A regulator part 29 made up of a fourth transistor 29b controlled by an output voltage of 29a, a fourth part connected in series with the fourth transistor 29b and controlled by an output of the fifth inverter 28; 5 transistors 30 are configured.

Here, the output Dout of the output driver 26 is a node N1 voltage between the fourth transistor 29b and the fifth transistor 30 and a node between the first transistor 26a and the second transistor 26b. Affected by N2 voltage.

The operation of the output driving circuit according to the present invention configured as described above will be described with reference to FIGS. 2 and 3.

3 is an operation timing diagram of the output driving circuit according to the present invention, in which the regulator enable signal Ren is high and the output buffer enable signal is low. The node N3, which is an output terminal, is at a low level, and the node N4, which is an output terminal of the fifth inverter 28, is at a high level.

Therefore, the level of the output terminal Dout of the output driver 26 is maintained at a level of 0.5 x VDD.

At this time, since the output terminal of the second logic gate 25b is high level and the output terminal of the third logic gate 25c is low level, both the first transistor 26a and the second transistor 26b are off. Therefore, the output driver 26 does not operate.

This behavior is represented by the truth table:

Renable Benable Regulator part Output buffer Low Low Disable Disable Low High Disable Enable High Low Enable Disable High High Disable Enable

As can be seen from the truth table, when the output buffer is enabled by the output buffer enable signal (Benable) and data is output through the output terminal Dout of the output driver 26, the regulator unit 29 is in a disabled state. Since the output buffer enable signal Benable is high level, the regulator unit 29 must be disabled.

When the regulator unit 29 is enabled, the device is in an active state, the output buffer enable signal Benable is low level, and the regulator enable signal Renable operates only in the high state.

As described above, the output driving circuit of the present invention can not only improve the output speed of the data but also minimize the ground bounce due to the output data, thereby stably operating the chip, thereby improving operating characteristics. .

Claims (6)

An output buffer unit for storing the output data of the sense amplifier and operating by an enable signal and outputting the same; An output driver for outputting data transmitted from the output buffer to the outside; And a regulator configured to set the voltage at the output terminal of the output driver as a tri-state voltage and forcibly maintain the voltage at the output terminal of the output driver when the output buffer unit and the output driver do not operate. Output drive circuit, characterized in that. A first inverter for inverting the regulator enable signal, A first logic gate for logic operation of an output buffer enable signal and an output of the first inverter, A second inverter for inverting the output of the first logic gate, A third inverter for inverting the output buffer enable signal, A fourth inverter for inverting the output of the third inverter, a second logic gate for performing logic operation on the output of the fourth inverter and the output of the sense amplifier, and the output of the third inverter and the output of the sense amplifier. An output buffer section consisting of a third logic gate for performing logical operation as an input, A first transistor connected in series between a power supply voltage terminal and a ground voltage terminal and controlled by the output of the second logic gate, and a second connected in series with the first transistor and controlled by the output of the third logic gate An output driver consisting of a transistor, A third transistor connected between a power supply voltage terminal and a ground voltage terminal and controlled by an output signal of the second inverter, A fifth inverter for inverting the output of the second inverter, A differential amplifier which compares the output voltage of the third transistor with the output voltage of the fifth inverter and amplifies and outputs the difference by a difference, and a third amplifier connected in series with the third transistor and controlled by the output voltage of the differential amplifier. Regulator part consisting of four transistors, And a fifth transistor connected in series with the fourth transistor and controlled by the output of the fifth inverter. 3. The output drive circuit according to claim 2, wherein the first transistor and the third transistor are PMOS transistors, and the second, fourth, and fifth transistors are NMOS transistors. 3. The output driving circuit according to claim 2, wherein the first logic gate and the third logic gate are noah gates, and the second logic gate is a NAND gate. 3. The output drive circuit according to claim 2, wherein an output end of the output driver is connected in parallel with an output end of the regulator. The output driving circuit of claim 2, wherein the differential amplifier receives a voltage of 1/2 of the power supply voltage as a reference voltage.