JP3561103B2

JP3561103B2 - Overflow detection circuit

Info

Publication number: JP3561103B2
Application number: JP31780196A
Authority: JP
Inventors: 幹雄白石
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1996-11-28
Filing date: 1996-11-28
Publication date: 2004-09-02
Anticipated expiration: 2016-11-28
Also published as: JPH10161849A

Description

【０００１】
【発明の属する技術分野】
本発明は、演算装置のオーバーフロー検出回路に関し、特にマイクロプロセッサ、信号処理プロセッサ、ビットスライスＡＬＵのオーバーフロー検出に使用されるものである。
【０００２】
【従来の技術】
電子計算機内部の算術演算は、複数ビットの二進数を用いて実行される。この際、演算精度が有限のビット長であることから、オーバーフローが発生することがある。オーバーフローは、演算の結果を利用すると比較的簡単に検出することができる。
【０００３】
例えば、２の補数表現で表された４ビットの２進数データの加算演算を行う場合を考える。例えば、＋５＋（−７）の演算を行うと、０１０１＋１００１＝１１１０（＝−２）となり、オーバーフローは起こらない。しかし、例えば−７＋（−６）の演算をすると、１００１＋１０１０＝００１１（＝３）となり、オーバーフローが起こる。例えば＋７＋（＋６）の演算についても、０１１１＋０１１０＝１１０１（＝−３）となり、オーバーフローが発生する。
【０００４】
このように、２つの入力データの符号ビットすなわち最上位ビット（以下ＭＳＢと呼ぶ）が同じであり、かつ出力データのＭＳＢが入力データのＭＳＢと異なる場合に、オーバーフローが生じることが分かる。
【０００５】
図５は、この場合のオーバーフロー検出回路を示す。図示せぬ複数ビット加算回路に入力される２つの入力データのＭＳＢをそれぞれＡ，Ｂとし、加算回路の出力データのＭＳＢをＳと表すことにする。
【０００６】
図５において、エクスクルシブノアゲート１の第１及び第２の入力端子には、それぞれ信号Ａ，Ｂが供給され、エクスクルシブオアゲート２の第１及び第２の入力端子には、それぞれ信号Ｂ、Ｓが供給される。ナンドゲート３の第１及び第２の入力端子には、それぞれエクスクルシブノアゲート１の出力信号とエクスクルシブオアゲート２の出力信号が供給される。ナンドゲート３は、オーバーフロー信号Ｖの反転信号／Ｖ（以下、／は反転信号を表すものとする）を出力する。
【０００７】
【発明が解決しようとする課題】
図５に示した回路には以下の２つの欠点がある。第１の欠点は、素子数が２４素子と比較的多いことである。第２の欠点は、信号が論理ゲートを２段通過するため、オーバーフローの検出時間が大きくなることである。演算結果を利用してオーバーフローか否かを検出するため、検出は高速に行わなければならない。
本発明は、上記課題に鑑みてなされたもので、素子数が少なく検出時間の短いオーバーフロー検出回路を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記課題を解決するため、本発明のオーバーフロー検出回路は、第１の端子が第１の電源電位に接続され、制御端子に第１の信号が供給される第１のスイッチ手段と、第１の端子が第１の電源電位に接続され、制御端子に第２の信号が供給される第２のスイッチ手段と、第１の端子が第１の電源電位に接続され、制御端子に第１の信号の反転信号が供給される第３のスイッチ手段と、第１の端子が第１の電源電位に接続され、制御端子に第２の信号の反転信号が供給される第４のスイッチ手段と、第１の端子が第１のスイッチ手段の第２の端子及び第２のスイッチ手段の第２の端子に接続され、制御端子に第３の信号が供給され、第２の端子がオーバーフロー信号を出力する第５のスイッチ手段と、第１の端子が第３のスイッチ手段の第２の端子及び第４のスイッチ手段の第２の端子に接続され、制御端子に第３の信号の反転信号が供給される第６のスイッチ手段と、第１の端子が第２の電源電位に接続され、制御端子に第１の信号が供給される第７のスイッチ手段と、第１の端子が第２の電源電位に接続され、制御端子に第１の信号の反転信号が供給される第８のスイッチ手段と、第１の端子が第７のスイッチ手段の第２の端子に接続され、制御端子に第２の信号が供給される第９のスイッチ手段と、第１の端子が第８のスイッチ手段の第２の端子に接続され、制御端子に第２の信号の反転信号が供給される第１０のスイッチ手段と、第１の端子が第９のスイッチ手段の第２の端子に接続され、制御端子に第３の信号の反転信号が供給され、第２の端子が第５のスイッチ手段の第２の端子に接続される第１１のスイッチ手段と、第１の端子が第１０のスイッチ手段の第２の端子に接続され、制御端子に第３の信号が供給され、第２の端子が第５のスイッチ手段の第２の端子に接続される第１２のスイッチ手段とを具備する。
【０００９】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を説明する。
図１は、本発明のオーバーフロー検出回路の第１の実施例を示す。
図１に示すように、信号Ａは第１のトランジスタ１１及び第７のトランジスタ１７のゲートに供給され、信号／Ａは第３のトランジスタ１３及び第１１のトランジスタ２１のゲートに供給される。また、信号Ｂは第２のトランジスタ１２及び第９のトランジスタ１９のゲートに供給され、信号／Ｂは第４のトランジスタ１４及び第１０のトランジスタ２０のゲートに供給される。さらに、信号Ｓは第５のトランジスタ１５及び第１２のトランジスタ２２のゲートに供給され、信号／Ｓは第６のトランジスタ１６及び第１１のトランジスタ２１のゲートに供給される。
【００１０】
第１のトランジスタ１１、第２のトランジスタ１２、第３のトランジスタ１３及び第４のトランジスタ１４の電流経路の第１の端子は、いずれも電源電位に接続される。第１のトランジスタ１１及び第２のトランジスタ１２の電流経路の第２の端子は、第５のトランジスタ１５の電流経路の第１の端子に接続される。第３のトランジスタ１３及び第４のトランジスタ１４の電流経路の第２の端子は、第６のトランジスタ１６の電流経路の第１の端子に接続される。第５のトランジスタ１５の電流経路の第２の端子は、第６のトランジスタ１６の電流経路の第２の端子、第１１のトランジスタ２１及び第１２のトランジスタ２２の電流経路の第２の端子に接続される。
【００１１】
第７のトランジスタ１７の電流経路の第２の端子は、第９のトランジスタ１９の電流経路の第１の端子に接続される。第９のトランジスタ１９の電流経路の第２の端子は、第１１のトランジスタ２１の電流経路の第１の端子に接続される。第７のトランジスタ１７の電流経路の第１の端子は接地される。また、第８のトランジスタ１８の電流経路の第２の端子は、第１０のトランジスタ２０の電流経路の第１の端子に接続される。第１０のトランジスタ２０の電流経路の第２の端子は、第１２のトランジスタ２２の電流経路の第１の端子に接続される。第８のトランジスタ１８の電流経路の第１の端子は接地される。
【００１２】
第５のトランジスタ１５の電流経路の第２の端子、第６のトランジスタ１６の電流経路の第２の端子、第１１のトランジスタ２１の電流経路の第２の端子及び第１２のトランジスタ２２の電流経路の第２の端子の接続点が出力端子となり、オーバーフロー信号／Ｖを出力する。
【００１３】
本実施例では、信号Ａ，Ｂ，Ｓ及びそれらの反転信号／Ａ、／Ｂ、／Ｓを用いている。他の回路で信号／Ａ，／Ｂ，／Ｓが生成されている場合は、それらの信号を本回路の入力信号に用いることができる。その場合、本実施例において、素子数は１２素子であり、ゲート段数は１段となる。よって、素子数と遅延時間を従来例よりも減らすことができる。
【００１４】
また、反転信号／Ａ，／Ｂ，／Ｓが他の回路で生成されていない場合は、信号Ａ，Ｂ，Ｓから２個のトランジスタよりなるインバータを３個用いてこれらの信号を生成しなければならない。この場合、素子数は１８素子となるものの、従来例より素子数を減らすことが可能となる。
【００１５】
なお、図１において、第１ないし第６のトランジスタはＰチャネルトランジスタであり、第７ないし第１２のトランジスタはＮチャネルトランジスタである。
図２は、本発明のオーバーフロー検出回路の第２の実施例を示す。
【００１６】
図２に示すように、信号Ａ，Ｂ，Ｓはそれぞれ第１のトランジスタ３１、第２のトランジスタ３２、第５のトランジスタ３５のゲートに供給される。信号／Ａ，／Ｂ，／Ｓはそれぞれ第３のトランジスタ３３、第４のトランジスタ３４、第６のトランジスタ３６のゲートに供給される。また、クロック信号ＣＫは、第７のトランジスタ３７及び第８のトランジスタ３８のゲートに供給される。
【００１７】
第７のトランジスタ３７の電流経路の第１の端子は、例えば電源電位に接続され、第７のトランジスタ３７の電流経路の第２の端子は、第５のトランジスタ３５及び第６のトランジスタ３６の電流経路の第２の端子に接続される。第５のトランジスタ３５の電流経路の第１の端子は、第１のトランジスタ３１及び第２のトランジスタ３２の電流経路の第２の端子に接続される。第６のトランジスタ３６の電流経路の第１の端子は、第３のトランジスタ３３及び第４のトランジスタ３４の電流経路の第２の端子に接続される。第１ないし第４のトランジスタ３１〜３４の電流経路の第１の端子は、第８のトランジスタ３８の電流経路の第２の端子に接続される。第８のトランジスタ３８の電流経路の第１の端子は、例えば接地される。
【００１８】
また、第７のトランジスタ３７の電流経路の第２の端子、第５のトランジスタ３５の電流経路の第２の端子及び第６のトランジスタ３６の電流経路の第２の端子の接続点は出力端子となり、オーバーフロー信号Ｖを出力する。
【００１９】
また、第７のトランジスタ３７は、ＰチャネルＭＯＳトランジスタであり、第８のトランジスタ３８は、ＮチャネルＭＯＳトランジスタである。第１ないし第６のトランジスタ３１〜３６は、例えばＮチャネルＭＯＳトランジスタである。
【００２０】
この回路は、ダイナミック動作をするオーバーフロー検出回路である。クロック信号ＣＫがローレベルのときは、プリチャージ期間であり、出力信号Ｖは入力信号によらず常にハイレベルである。この後、クロック信号ＣＫがハイレベルになると、オーバーフロー検出回路として動作する。
【００２１】
本実施例では、８素子でオーバーフロー検出回路を構成することができるので、図１に示した実施例よりも素子数をさらに減らすことが可能となる。
図３は、本発明のオーバーフロー検出回路の第３の実施例を示す。
【００２２】
図３に示すように、信号Ａ，Ｂ，Ｓはそれぞれ第１のトランジスタ４１、第２のトランジスタ４２、第５のトランジスタ４５のゲートに供給される。信号／Ａ，／Ｂ，／Ｓはそれぞれ第３のトランジスタ４３、第４のトランジスタ４４、第６のトランジスタ４６のゲートに供給される。また、クロック信号ＣＫは、第７のトランジスタ４７及び第８のトランジスタ４８のゲートに供給される。
【００２３】
第７のトランジスタ４７の電流経路の第１の端子は、例えば電源電位に接続され、第７のトランジスタ４７の電流経路の第２の端子は、第１ないし第４のトランジスタ４１〜４４の電流経路の第１の端子に接続される。第１及び第２のトランジスタ４１、４２の電流経路の第２の端子は、第５のトランジスタ４５の電流経路の第１の端子に接続される。第３及び第４のトランジスタ４３、４４の電流経路の第２の端子は、第６のトランジスタ４６の電流経路の第１の端子に接続される。第５及び第６のトランジスタ４５、４６の電流経路の第２の端子は、第８のトランジスタ４８の電流経路の第１の端子に接続される。第８のトランジスタ４８の電流経路の第２の端子は、例えば接地される。
【００２４】
また、第７のトランジスタ４７の電流経路の第２の端子と、第１ないし第４のトランジスタ４１〜４４の電流経路の第１の端子の接続点は出力端子となり、オーバーフロー信号Ｖを出力する。
【００２５】
また、第７のトランジスタ４７は、ＰチャネルＭＯＳトランジスタであり、第８のトランジスタ４８は、ＮチャネルＭＯＳトランジスタである。第１ないし第６のトランジスタ４１〜４６は、例えばＮチャネルＭＯＳトランジスタである。
【００２６】
この回路は、図２に示した回路と同様に、ダイナミック動作をするオーバーフロー検出回路である。クロック信号ＣＫがローレベルのときは、プリチャージ期間であり、出力信号Ｖは入力信号によらず常にハイレベルである。この後、クロック信号ＣＫがハイレベルになると、オーバーフロー検出回路として動作する。
【００２７】
本実施例では、８素子でオーバーフロー検出回路を構成しているので、従来例よりも素子数を減らすことができる。
図４は、本発明のオーバーフロー検出回路の第４の実施例を示す。
【００２８】
図４に示した実施例において、信号Ａ，Ｂ，Ｓはそれぞれ第１のトランジスタ５１、第３のトランジスタ５３、第６のトランジスタ５６のゲートに供給される。信号／Ａ，／Ｂ，／Ｓはそれぞれ第２のトランジスタ５２、第４のトランジスタ５４、第５のトランジスタ５５のゲートに供給される。また、クロック信号ＣＫは、第７のトランジスタ５７及び第８のトランジスタ５８のゲートに供給される。
【００２９】
また、第７のトランジスタ５７の電流経路の第１の端子は電源電位に接続され、第７のトランジスタ５７の電流経路の第２の端子は第５のトランジスタ５５及び第６のトランジスタ５６の電流経路の第２の端子に接続される。第６のトランジスタ５６の電流経路の第１の端子は第４のトランジスタ５４の電流経路の第２の端子に接続され、第４のトランジスタ５４の電流経路の第１の端子は第２のトランジスタ５２の電流経路の第２の端子に接続される。第２のトランジスタ５２の電流経路の第１の端子は第８のトランジスタ５８の第２の端子に接続される。また、第５のトランジスタ５５の電流経路の第１の端子は第３のトランジスタ５３の電流経路の第２の端子に接続され、第３のトランジスタ５３の電流経路の第１の端子は第１のトランジスタ５１の電流経路の第２の端子に接続される。第１のトランジスタ５１の電流経路の第１の端子は第８のトランジスタ５８の電流経路の第２の端子に接続される。第８のトランジスタ５８の電流経路の第１の端子は接地される。
【００３０】
第７のトランジスタ５７の電流経路の第２の端子と、第５及び第６のトランジスタ５５、５６の電流経路の第２の端子との接続点は出力端子となり、オーバーフロー信号／Ｖを出力する。
【００３１】
また、第７のトランジスタ５７は、ＰチャネルＭＯＳトランジスタであり、第８のトランジスタ５８は、ＮチャネルＭＯＳトランジスタである。第１ないし第６のトランジスタ５１〜５６は、例えばＮチャネルＭＯＳトランジスタである。
【００３２】
この回路は、図２及び図３に示した回路と同様に、ダイナミック動作をするオーバーフロー検出回路である。クロック信号ＣＫがローレベルのときは、プリチャージ期間であり、出力信号／Ｖは入力信号によらず常にハイレベルである。この後、クロック信号ＣＫがハイレベルになると、オーバーフロー検出回路として動作する。
【００３３】
本実施例では、図２及び図３に示した回路と同様に、オーバーフロー検出回路を構成する素子数を従来よりも減らすことができる。
なお、図２ないし図４に示した実施例において、例えば電源電位と出力端子間に第７のトランジスタ３７、４７、５７に代えて抵抗を設けてもよい。また、第８のトランジスタ３８、４８、５８を除去し、トランジスタ３１、３２、３３、３４、４５、４６、５１、５２の電流経路のこれらの除去したトランジスタに接続されていた端子を例えば接地してもよい。この場合も、オーバーフロー検出回路として動作し、素子数を減らすことができる。
【００３４】
また、上述の実施例ではトランジスタを用いているが、これに限られるものではなく、スイッチ手段であればよい。また、上述の実施例で電源電位と接地電位を逆にしてもオーバーフロー検出回路として動作する。
【００３５】
【発明の効果】
以上説明したように、本発明によれば、オーバーフロー検出回路をスイッチ回路網による単一の論理ゲートで構成するため、素子数を減らし検出時間を短くすることが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示す回路図。
【図２】本発明の第２の実施例を示す回路図。
【図３】本発明の第３の実施例を示す回路図。
【図４】本発明の第４の実施例を示す回路図。
【図５】従来例を示す回路図。
【符号の説明】
１１〜１６…ＰチャネルＭＯＳトランジスタ、
１７〜２２…ＮチャネルＭＯＳトランジスタ、
Ａ…加算回路の第１の入力信号の最上位ビット、
／Ａ…信号Ａの反転信号、
Ｂ…加算回路の第２の入力信号の最上位ビット、
／Ｂ…信号Ｂの反転信号、
Ｓ…加算回路の出力信号の最上位ビット、
／Ｓ…信号Ｓの反転信号。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an overflow detection circuit of an arithmetic unit, and more particularly to an overflow detection circuit for a microprocessor, a signal processor, and an overflow detection of a bit slice ALU.
[0002]
[Prior art]
Arithmetic operations inside the electronic computer are executed using a binary number of a plurality of bits. At this time, since the calculation accuracy is a finite bit length, an overflow may occur. The overflow can be relatively easily detected by using the result of the operation.
[0003]
For example, consider a case in which an addition operation is performed on 4-bit binary data represented in two's complement representation. For example, when an operation of +5 + (− 7) is performed, 0101 + 1001 = 1110 (= −2), and no overflow occurs. However, for example, when an operation of −7 + (− 6) is performed, 1001 + 1010 = 0011 (= 3), and an overflow occurs. For example, for the operation of +7 + (+ 6), 0111 + 0110 = 1101 (= −3), and an overflow occurs.
[0004]
Thus, it can be seen that overflow occurs when the sign bit of the two input data, that is, the most significant bit (hereinafter referred to as MSB) is the same and the MSB of the output data is different from the MSB of the input data.
[0005]
FIG. 5 shows an overflow detection circuit in this case. The MSBs of two input data input to a multi-bit addition circuit (not shown) are denoted by A and B, respectively, and the MSB of output data of the addition circuit is denoted by S.
[0006]
In FIG. 5, signals A and B are supplied to first and second input terminals of an exclusive NOR gate 1, respectively, and a signal B is supplied to first and second input terminals of an exclusive OR gate 2, respectively. , S are supplied. The output signal of the exclusive NOR gate 1 and the output signal of the exclusive OR gate 2 are supplied to the first and second input terminals of the NAND gate 3, respectively. The NAND gate 3 outputs an inverted signal / V of the overflow signal V (hereinafter, / represents an inverted signal).
[0007]
[Problems to be solved by the invention]
The circuit shown in FIG. 5 has the following two disadvantages. The first drawback is that the number of elements is relatively large at 24 elements. The second drawback is that the overflow detection time is long because the signal passes through the logic gate in two stages. In order to detect whether or not an overflow has occurred using the operation result, the detection must be performed at high speed.
The present invention has been made in view of the above problems, and has as its object to provide an overflow detection circuit having a small number of elements and a short detection time.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an overflow detection circuit according to the present invention comprises: a first switch means having a first terminal connected to a first power supply potential and a first signal supplied to a control terminal; A second switch means having a terminal connected to the first power supply potential and a second signal supplied to the control terminal; a first terminal connected to the first power supply potential and a first signal connected to the control terminal; Third switch means to which an inverted signal of the second signal is supplied, fourth switch means having a first terminal connected to the first power supply potential, and an inverted signal of the second signal supplied to the control terminal, One terminal is connected to the second terminal of the first switch means and the second terminal of the second switch means, a third signal is supplied to the control terminal, and the second terminal outputs an overflow signal. The fifth switch means and the first terminal are connected to the second switch means of the third switch means. A sixth switch means connected to the second terminal of the second switch and the fourth switch means, and a control terminal supplied with an inverted signal of the third signal; and a first terminal connected to the second power supply potential. A seventh switch means for supplying a first signal to the control terminal, and an eighth switch means for connecting the first terminal to the second power supply potential and supplying an inverted signal of the first signal to the control terminal. Switch means, ninth switch means having a first terminal connected to the second terminal of the seventh switch means, and a control terminal supplied with a second signal, and a first terminal connected to the eighth switch means. A tenth switch means connected to a second terminal of the means and an inverted signal of the second signal supplied to a control terminal; a first terminal connected to a second terminal of the ninth switch means; An inverted signal of the third signal is supplied to the control terminal, and the second terminal is connected to the fifth switch means. And a first terminal connected to the second terminal of the tenth switch means, a third signal supplied to the control terminal, and a fifth terminal connected to the fifth terminal. And twelfth switch means connected to the second terminal of the switch means.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment of the overflow detection circuit of the present invention.
As shown in FIG. 1, the signal A is supplied to the gates of the first transistor 11 and the seventh transistor 17, and the signal / A is supplied to the gates of the third transistor 13 and the eleventh transistor 21. The signal B is supplied to the gates of the second transistor 12 and the ninth transistor 19, and the signal / B is supplied to the gates of the fourth transistor 14 and the tenth transistor 20. Further, the signal S is supplied to the gates of the fifth transistor 15 and the twelfth transistor 22, and the signal / S is supplied to the gates of the sixth transistor 16 and the eleventh transistor 21.
[0010]
The first terminals of the current paths of the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are all connected to the power supply potential. The second terminal of the current path of the first transistor 11 and the second transistor 12 is connected to the first terminal of the current path of the fifth transistor 15. The second terminals of the current paths of the third transistor 13 and the fourth transistor 14 are connected to the first terminal of the current path of the sixth transistor 16. The second terminal of the current path of the fifth transistor 15 is connected to the second terminal of the current path of the sixth transistor 16 and the second terminal of the current path of the eleventh transistor 21 and the twelfth transistor 22. Is done.
[0011]
The second terminal of the current path of the seventh transistor 17 is connected to the first terminal of the current path of the ninth transistor 19. The second terminal of the current path of the ninth transistor 19 is connected to the first terminal of the current path of the eleventh transistor 21. The first terminal of the current path of the seventh transistor 17 is grounded. Further, the second terminal of the current path of the eighth transistor 18 is connected to the first terminal of the current path of the tenth transistor 20. The second terminal of the current path of the tenth transistor 20 is connected to the first terminal of the current path of the twelfth transistor 22. The first terminal of the current path of the eighth transistor 18 is grounded.
[0012]
The second terminal of the current path of the fifth transistor 15, the second terminal of the current path of the sixth transistor 16, the second terminal of the current path of the eleventh transistor 21, and the current path of the twelfth transistor 22 Is the output terminal, and outputs an overflow signal / V.
[0013]
In this embodiment, signals A, B, and S and their inverted signals / A, / B, and / S are used. When the signals / A, / B, and / S are generated by another circuit, those signals can be used as input signals of the present circuit. In this case, in this embodiment, the number of elements is 12 and the number of gate stages is one. Therefore, the number of elements and the delay time can be reduced as compared with the conventional example.
[0014]
When the inverted signals / A, / B, / S are not generated by other circuits, these signals must be generated from the signals A, B, S by using three inverters each composed of two transistors. Must. In this case, although the number of elements is 18, the number of elements can be reduced as compared with the conventional example.
[0015]
Note that in FIG. 1, the first to sixth transistors are P-channel transistors, and the seventh to twelfth transistors are N-channel transistors.
FIG. 2 shows a second embodiment of the overflow detection circuit of the present invention.
[0016]
As shown in FIG. 2, the signals A, B, and S are supplied to the gates of the first transistor 31, the second transistor 32, and the fifth transistor 35, respectively. The signals / A, / B, / S are supplied to the gates of the third transistor 33, the fourth transistor 34, and the sixth transistor 36, respectively. Further, the clock signal CK is supplied to the gates of the seventh transistor 37 and the eighth transistor 38.
[0017]
The first terminal of the current path of the seventh transistor 37 is connected to, for example, the power supply potential, and the second terminal of the current path of the seventh transistor 37 is connected to the current of the fifth transistor 35 and the sixth transistor 36. Connected to the second terminal of the path. The first terminal of the current path of the fifth transistor 35 is connected to the second terminal of the current path of the first transistor 31 and the second transistor 32. The first terminal of the current path of the sixth transistor 36 is connected to the second terminal of the current path of the third transistor 33 and the fourth transistor 34. The first terminal of the current path of the first to fourth transistors 31 to 34 is connected to the second terminal of the current path of the eighth transistor 38. The first terminal of the current path of the eighth transistor 38 is, for example, grounded.
[0018]
A connection point between the second terminal of the current path of the seventh transistor 37, the second terminal of the current path of the fifth transistor 35, and the second terminal of the current path of the sixth transistor 36 is an output terminal. , And outputs an overflow signal V.
[0019]
The seventh transistor 37 is a P-channel MOS transistor, and the eighth transistor 38 is an N-channel MOS transistor. The first to sixth transistors 31 to 36 are, for example, N-channel MOS transistors.
[0020]
This circuit is an overflow detection circuit that performs a dynamic operation. When the clock signal CK is at the low level, it is the precharge period, and the output signal V is always at the high level regardless of the input signal. Thereafter, when the clock signal CK goes high, it operates as an overflow detection circuit.
[0021]
In this embodiment, since the overflow detection circuit can be constituted by eight elements, the number of elements can be further reduced as compared with the embodiment shown in FIG.
FIG. 3 shows a third embodiment of the overflow detection circuit of the present invention.
[0022]
As shown in FIG. 3, signals A, B, and S are supplied to the gates of a first transistor 41, a second transistor 42, and a fifth transistor 45, respectively. The signals / A, / B, / S are supplied to the gates of the third transistor 43, the fourth transistor 44, and the sixth transistor 46, respectively. Further, the clock signal CK is supplied to the gates of the seventh transistor 47 and the eighth transistor 48.
[0023]
The first terminal of the current path of the seventh transistor 47 is connected to, for example, a power supply potential, and the second terminal of the current path of the seventh transistor 47 is connected to the current path of the first to fourth transistors 41 to 44. Is connected to the first terminal of The second terminal of the current path of the first and second transistors 41 and 42 is connected to the first terminal of the current path of the fifth transistor 45. The second terminals of the current paths of the third and fourth transistors 43 and 44 are connected to the first terminal of the current path of the sixth transistor 46. The second terminals of the current paths of the fifth and sixth transistors 45 and 46 are connected to the first terminal of the current path of the eighth transistor 48. The second terminal of the current path of the eighth transistor 48 is, for example, grounded.
[0024]
A connection point between the second terminal of the current path of the seventh transistor 47 and the first terminal of the current path of the first to fourth transistors 41 to 44 becomes an output terminal, and outputs an overflow signal V.
[0025]
The seventh transistor 47 is a P-channel MOS transistor, and the eighth transistor 48 is an N-channel MOS transistor. The first to sixth transistors 41 to 46 are, for example, N-channel MOS transistors.
[0026]
This circuit is an overflow detection circuit that performs a dynamic operation similarly to the circuit shown in FIG. When the clock signal CK is at the low level, it is the precharge period, and the output signal V is always at the high level regardless of the input signal. Thereafter, when the clock signal CK goes high, it operates as an overflow detection circuit.
[0027]
In this embodiment, since the overflow detection circuit is composed of eight elements, the number of elements can be reduced as compared with the conventional example.
FIG. 4 shows a fourth embodiment of the overflow detection circuit of the present invention.
[0028]
In the embodiment shown in FIG. 4, signals A, B, and S are supplied to the gates of a first transistor 51, a third transistor 53, and a sixth transistor 56, respectively. The signals / A, / B, / S are supplied to the gates of the second transistor 52, the fourth transistor 54, and the fifth transistor 55, respectively. The clock signal CK is supplied to gates of the seventh transistor 57 and the eighth transistor 58.
[0029]
The first terminal of the current path of the seventh transistor 57 is connected to the power supply potential, and the second terminal of the current path of the seventh transistor 57 is connected to the current path of the fifth transistor 55 and the sixth transistor 56. Is connected to the second terminal. The first terminal of the current path of the sixth transistor 56 is connected to the second terminal of the current path of the fourth transistor 54, and the first terminal of the current path of the fourth transistor 54 is connected to the second transistor 52. Is connected to the second terminal of the current path. The first terminal of the current path of the second transistor 52 is connected to the second terminal of the eighth transistor 58. The first terminal of the current path of the fifth transistor 55 is connected to the second terminal of the current path of the third transistor 53, and the first terminal of the current path of the third transistor 53 is connected to the first terminal. Connected to the second terminal of the current path of transistor 51. The first terminal of the current path of the first transistor 51 is connected to the second terminal of the current path of the eighth transistor 58. The first terminal of the current path of the eighth transistor 58 is grounded.
[0030]
A connection point between the second terminal of the current path of the seventh transistor 57 and the second terminal of the current path of the fifth and sixth transistors 55 and 56 becomes an output terminal and outputs an overflow signal / V.
[0031]
The seventh transistor 57 is a P-channel MOS transistor, and the eighth transistor 58 is an N-channel MOS transistor. The first to sixth transistors 51 to 56 are, for example, N-channel MOS transistors.
[0032]
This circuit is an overflow detection circuit that performs a dynamic operation similarly to the circuits shown in FIGS. When the clock signal CK is at the low level, it is the precharge period, and the output signal / V is always at the high level regardless of the input signal. Thereafter, when the clock signal CK goes high, it operates as an overflow detection circuit.
[0033]
In this embodiment, similarly to the circuits shown in FIGS. 2 and 3, the number of elements constituting the overflow detection circuit can be reduced as compared with the related art.
In the embodiment shown in FIGS. 2 to 4, for example, a resistor may be provided between the power supply potential and the output terminal instead of the seventh transistors 37, 47, and 57. Further, the eighth transistors 38, 48 and 58 are removed, and the terminals of the current paths of the transistors 31, 32, 33, 34, 45, 46, 51 and 52 which are connected to these removed transistors are grounded, for example. You may. Also in this case, the circuit operates as an overflow detection circuit, and the number of elements can be reduced.
[0034]
In the above-described embodiment, a transistor is used. However, the present invention is not limited to this, and any switch may be used. Further, even if the power supply potential and the ground potential are reversed in the above-described embodiment, the circuit operates as an overflow detection circuit.
[0035]
【The invention's effect】
As described above, according to the present invention, since the overflow detection circuit is configured by a single logic gate using a switch network, the number of elements can be reduced and the detection time can be shortened.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a third embodiment of the present invention.
FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.
FIG. 5 is a circuit diagram showing a conventional example.
[Explanation of symbols]
11 to 16 P-channel MOS transistors,
17 to 22... N-channel MOS transistors,
A: the most significant bit of the first input signal of the adding circuit;
/ A: inverted signal of signal A,
B: the most significant bit of the second input signal of the adding circuit;
/ B: inverted signal of signal B,
S: the most significant bit of the output signal of the adding circuit,
/ S: an inverted signal of the signal S.

Claims

First switch means having a first terminal connected to a first power supply potential and a first signal supplied to a control terminal;
A second switch means having a first terminal connected to the first power supply potential and a second signal supplied to a control terminal;
Third switch means having a first terminal connected to the first power supply potential, and a control terminal supplied with an inverted signal of the first signal;
Fourth switch means having a first terminal connected to the first power supply potential and a control terminal supplied with an inverted signal of the second signal;
A first terminal is connected to a second terminal of the first switch means and a second terminal of the second switch means, a third signal is supplied to a control terminal, and the second terminal is an overflow signal. Fifth switch means for outputting
A sixth terminal in which a first terminal is connected to a second terminal of the third switch means and a second terminal of the fourth switch means, and an inverted signal of the third signal is supplied to a control terminal. Switch means;
Seventh switch means having a first terminal connected to a second power supply potential and a control terminal to which the first signal is supplied;
Eighth switch means having a first terminal connected to the second power supply potential, and a control terminal supplied with an inverted signal of the first signal;
Ninth switch means having a first terminal connected to a second terminal of the seventh switch means and a control terminal supplied with the second signal;
A tenth switch means having a first terminal connected to a second terminal of the eighth switch means and a control terminal supplied with an inverted signal of the second signal;
A first terminal is connected to a second terminal of the ninth switch means, an inverted signal of the third signal is supplied to a control terminal, and a second terminal is connected to a second terminal of the fifth switch means. Eleventh switch means connected to the terminal;
A first terminal is connected to a second terminal of the tenth switch means, a third signal is supplied to a control terminal, and a second terminal is connected to a second terminal of the fifth switch means. An overflow detection circuit, comprising: a twelfth switch means.

First switch means having a first terminal connected to a first power supply potential and a first signal supplied to a control terminal;
A second switch means having a first terminal connected to the first power supply potential and a second signal supplied to a control terminal;
Third switch means having a first terminal connected to the first power supply potential, and a control terminal supplied with an inverted signal of the first signal;
Fourth switch means having a first terminal connected to the first power supply potential and a control terminal supplied with an inverted signal of the second signal;
A first terminal is connected to a second terminal of the first switch means and a second terminal of the second switch means, a third signal is supplied to a control terminal, and the second terminal is an overflow signal. Fifth switch means for outputting
A first terminal is connected to a second terminal of the third switch means and a second terminal of the fourth switch means, and an inverted signal of the third signal is supplied to a control terminal. An overflow detection circuit comprising: a sixth switch means whose terminal is connected to a second terminal of the fifth switch means.

First switch means for outputting an overflow signal from the first terminal and supplying the first signal to the control terminal;
A second switch means having a first terminal connected to a first terminal of the first switch means and a control terminal supplied with a second signal;
A third switch means having a first terminal connected to a first terminal of the first switch means, and a control terminal supplied with an inverted signal of the first signal;
A fourth switch means having a first terminal connected to the first terminal of the first switch means and a control terminal supplied with an inverted signal of the second signal;
A first terminal is connected to a second terminal of the first switch means and a second terminal of the second switch means, a third signal is supplied to a control terminal, and the second terminal is connected to the first terminal. Fifth switch means connected to the power supply potential of
A first terminal is connected to a second terminal of the third switch means and a second terminal of the fourth switch means, and an inverted signal of the third signal is supplied to a control terminal. Sixth switch means having a terminal connected to the first power supply potential;
An overflow detection circuit, comprising:

First switch means having a first terminal connected to a first power supply potential and a first signal supplied to a control terminal;
Second switch means having a first terminal connected to the first power supply potential and a control terminal supplied with an inverted signal of the first signal;
A third switch means having a first terminal connected to a second terminal of the first switch means and a control terminal supplied with a second signal;
Fourth switch means having a first terminal connected to a second terminal of the second switch means, and a control terminal supplied with an inverted signal of the second signal;
A first terminal connected to a second terminal of the third switch means, a control terminal supplied with an inverted signal of a third signal, and a second terminal outputting an overflow signal; ,
A first terminal is connected to a second terminal of the fourth switch means, a control terminal is supplied with the third signal, and a second terminal is connected to a second terminal of the fifth switch means. Sixth switch means to be performed;
An overflow detection circuit, comprising:

The first signal is the most significant bit of a first multi-bit signal represented in two's complement;
The second signal is the most significant bit of a second multi-bit signal represented in two's complement;
5. The overflow detection according to claim 1, wherein the third signal is a most significant bit of an output signal of an adder for adding the first multi-bit signal and the second multi-bit signal. circuit.

The first to sixth switch means are first conductivity type MOS transistors,
2. The overflow detection circuit according to claim 1, wherein said seventh to twelfth switch means are second conductivity type MOS transistors.

5. The overflow detecting circuit according to claim 2, wherein said first to sixth switch means are MOS transistors.