JP4336990B2 - Gradation implementation apparatus and method for liquid crystal display device - Google Patents

Gradation implementation apparatus and method for liquid crystal display device Download PDF

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JP4336990B2
JP4336990B2 JP2005263353A JP2005263353A JP4336990B2 JP 4336990 B2 JP4336990 B2 JP 4336990B2 JP 2005263353 A JP2005263353 A JP 2005263353A JP 2005263353 A JP2005263353 A JP 2005263353A JP 4336990 B2 JP4336990 B2 JP 4336990B2
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新 社 殷
炯 ▲ダエ▼ 金
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ハイディス テクノロジーズ株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation

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  • Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Description

本発明は、階調具現装置及び方法に関し、特に、ピクセルに定電流を供給し、ゲートがオン/オフされるまでデータを入力するための充電期間を階調表現数で時分割して階調を表現する階調具現装置及び方法に関する。   The present invention relates to a gray scale implementation apparatus and method, and more particularly, to supply a constant current to a pixel and time-divide a charging period for inputting data until a gate is turned on / off by a gray scale expression number. The present invention relates to an apparatus and method for realizing a gradation.

一般に、液晶表示装置は、複数のデータラインと複数のスキャンラインとの間に複数のピクセルがマトリックス構造で配置され、ピクセルの正極電極がデータライン、ピクセルの負極電極がスキャンラインに各々接続されて、１つの表示パネルを構成している。このような液晶表示装置は、データラインとスキャンラインとの電位差がピクセルのしきい値電圧を越える場合にピクセルを発光させ、ピクセルに電流が流れる時間に応じて明さを変更して多様な階調を具現する。   In general, a liquid crystal display device has a plurality of pixels arranged in a matrix structure between a plurality of data lines and a plurality of scan lines, and a positive electrode of the pixel is connected to the data line and a negative electrode of the pixel is connected to the scan line. One display panel is configured. Such a liquid crystal display device emits light when the potential difference between the data line and the scan line exceeds the threshold voltage of the pixel, and changes the brightness according to the time during which the current flows through the pixel. Embody the key.

図１は、従来の階調具現装置の構成を示すブロックである。   FIG. 1 is a block diagram illustrating a configuration of a conventional gray scale implementation apparatus.

従来の階調具現装置は、シフトレジスタ１０、データレジスタ１１、データラッチ１２、レベルシフタ１３、基準電圧発生器１４、Ｄ／Ａコンバータ１５及び出力バッファ１６を備える。   The conventional gradation implementation apparatus includes a shift register 10, a data register 11, a data latch 12, a level shifter 13, a reference voltage generator 14, a D / A converter 15, and an output buffer 16.

シフトレジスタ１０がエッジサンプリングクロックをデータレジスタ１１に供給し、データレジスタ１１がシフトレジスタ１０から供給されるエッジサンプリングクロックに応じて、タイミングコントローラ（図示していない）から供給されるＲＧＢデータを格納する。その後、ＲＧＢデータは１水平ラインの全ての表示データとして格納された後、データラッチ１２に移動する。   The shift register 10 supplies an edge sampling clock to the data register 11, and the data register 11 stores RGB data supplied from a timing controller (not shown) in accordance with the edge sampling clock supplied from the shift register 10. . Thereafter, the RGB data is stored as all display data of one horizontal line, and then moved to the data latch 12.

基準電圧発生器１４が外部から入力されるガンマ電圧を受信して内部のＲ−ｓｔｒｉｎｇ回路により６４階調レベル（６ビット）、または、２５６階調レベル（８ビット）の基準電圧を発生させる。   The reference voltage generator 14 receives a gamma voltage input from the outside, and generates a reference voltage of 64 gradation levels (6 bits) or 256 gradation levels (8 bits) by an internal R-string circuit.

Ｄ／Ａコンバータ１５が、レベルシフタ１３を介してデータラッチ１２から出力される表示データを受信し、基準電圧発生器１４から提供される各階調レベルの基準電圧に基づいて受信した表示データに対応する出力電圧を発生させる。   The D / A converter 15 receives the display data output from the data latch 12 via the level shifter 13 and corresponds to the display data received based on the reference voltage of each gradation level provided from the reference voltage generator 14. Generate an output voltage.

出力バッファ１６がＬＣＤパネルを駆動する演算増幅器を備え、（出力バッファ１６の）出力信号が１回入力される１水平ラインのスキャン期間の間に一定の電圧を維持する。入力される各階調レベルに対する充電時間は１水平ラインのスキャン期間と同じであり、各々異なる階調レベルを出力するためには各々異なる電圧を必要とする。しかし、この従来の階調具現装置は入力されるガンマ電圧の電圧範囲が狭いので、多様な階調レベルを具現するには限界がある。言い換えると、従来の階調具現装置に入力されるガンマ電圧が５ｍＶの電圧レベルを有するため、従来の階調具現装置は１０２４階調（１０ビット）、または、それ以上の高い階調レベルを具現する場合、小さなレベルのガンマ電圧のために多様な階調を具現することができないという問題がある。   The output buffer 16 includes an operational amplifier that drives the LCD panel, and maintains a constant voltage during the scan period of one horizontal line in which the output signal (of the output buffer 16) is input once. The charging time for each inputted gradation level is the same as the scanning period of one horizontal line, and different voltages are required to output different gradation levels. However, since the conventional gray level implementing apparatus has a narrow voltage range of the input gamma voltage, there are limits to realizing various gray level levels. In other words, since the gamma voltage input to the conventional gray scale apparatus has a voltage level of 5 mV, the conventional gray scale apparatus implements a 1024 gray scale (10 bits) or higher gray level. In this case, there is a problem in that various gradations cannot be realized due to a small level of gamma voltage.

本発明は、上記のような従来の技術に内在していた問題点を解決するために案出されたものであって、階調具現時に定電流を使用してより多い階調を安定に具現できる階調具現装置及び方法を提供することを目的とする。   The present invention has been devised to solve the problems inherent in the prior art as described above, and stably implements a larger number of gradations using a constant current at the time of gradation implementation. An object of the present invention is to provide an apparatus and a method for realizing a gradation.

上記の課題を解決するために、本発明の一側面により、階調具現装置が提供されて、この装置は、ピクセルに充電する電流を供給する電流供給部と、表示データをラッチするバッファと、現在入力される表示データ及び前記バッファにラッチされた以前の表示データを加算する加算器と、前記加算器の出力データを受信し、前記出力データの値に対応するパルス幅を有するスイッチ−オンパルスを前記電流供給部に伝達するパルス発生部と、前記電流供給部、加算器及びパルス発生部を制御する制御部とを備え、前記電流供給部が、ポジティブ定電流源、ネガティブ定電流源及びスイッチを備え、前記ポジティブ定電流源とネガティブ定電流源とが、前記スイッチ−オンパルスを共通に受信し前記スイッチに電流を出力し、前記スイッチが所定のフレームレートで前記ポジティブ定電流源、または、ネガティブ定電流源の出力電流を選択的に前記ピクセルに供給することができることを特徴とする。 In order to solve the above problems, according to an aspect of the present invention, a gray scale implementation device is provided, which includes a current supply unit that supplies a current for charging a pixel, a buffer that latches display data, An adder for adding currently input display data and previous display data latched in the buffer; and output data of the adder, and a switch-on pulse having a pulse width corresponding to the value of the output data. A pulse generation unit that transmits to the current supply unit; and a control unit that controls the current supply unit, the adder, and the pulse generation unit , wherein the current supply unit includes a positive constant current source, a negative constant current source, and a switch. The positive constant current source and the negative constant current source receive the switch-on pulse in common and output a current to the switch. Wherein at the frame rate positive constant current source, or, wherein Rukoto can be selectively supplied to the said pixel output current of the negative constant current source.

上記の構成において、前記ポジティブ定電流源及びネガティブ定電流源は、前記スイッチにより交互に選択されうる。   In the above configuration, the positive constant current source and the negative constant current source can be alternately selected by the switch.

本発明の他の一側面により、階調具現方法が提供されて、この方法は、（ａ）表示データを受信してラッチし、ラッチされた該表示データを第１表示データとするステップと、（ｂ）前記第１表示データの値に対応するパルス幅を有する第１スイッチ−オンパルスを発生するステップと、（ｃ）前記第１スイッチ−オンパルスのパルス幅に対応する第１電流をピクセルに供給し、該ピクセルを充電するステップと、（ｄ）前記第１表示データの次に入力される表示データを受信してラッチし、ラッチされた該表示データを第２表示データとするステップと、（ｅ）今回のラッチでラッチされた前記第２表示データと前回のラッチでラッチされた前記第１表示データとを加算して加算表示データを生成するステップと、（ｆ）前記加算表示データの値に対応するパルス幅を有する第２スイッチ−オンパルスを発生するステップと、（ｇ）前記第２スイッチ−オンパルスに基づいて前記第１電流の反対極性を有する第２電流を前記ピクセルに供給し、該ピクセルを充電するステップとを含み、今回のラッチでラッチされた前記第２表示データの次に受信される表示データを新たに第２表示データとし、今回のラッチでラッチされた前記第２表示データを新たに第１表示データとして、前記（ｄ）〜（ｇ）のステップに従って処理を行うことを特徴とする。 By another aspect of the present invention, the gradation embodied method is provided, the method comprising the steps of (a) and Display Data received by the latch, latched the display data of the first display data (B) generating a first switch-on pulse having a pulse width corresponding to the value of the first display data; and (c) applying a first current corresponding to the pulse width of the first switch-on pulse to the pixel. supplied, the steps of charging the pixel, the steps of (d) and the first to receive Viewing data that is input to the next latch display data, latched the display data to second display data , (e) generating a sum display data by adding the first display data latched by the latched second display data and the previous latch in this latch, (f) the addition display data Generating a second switch-on pulse having a pulse width corresponding to a value of the data; and (g) supplying a second current having a polarity opposite to the first current to the pixel based on the second switch-on pulse. and, and a step of charging the pixel, the Viewing data that will be received next to this said second display data latched by the latch and new second display data, latched in this latch the The second display data is newly set as the first display data, and processing is performed according to the steps (d) to (g).

前記第２電流は、前記第１電流により充電したピクセルを放電させる第１表示データの値に対応する電流と、前記ピクセルを充電する第２表示データの値に対応する電流とを含むことができる。   The second current may include a current corresponding to a value of first display data for discharging a pixel charged with the first current and a current corresponding to a value of second display data for charging the pixel. .

本発明によれば、基準クロック及び電流源を使用することにより、高い階調レベルを容易に具現でき、また、連続的な階調レベルを具現することによりＬＣＤの品質を向上させることができる。   According to the present invention, a high gradation level can be easily realized by using a reference clock and a current source, and the quality of the LCD can be improved by realizing a continuous gradation level.

以下、添付の図面を参照しながら本発明の好ましい実施の形態を説明する。なお、以下の説明及び図面において、同じ参照符号は同じ又は類似の構成要素を示すこととし、よって、同じ又は類似の構成要素に関する説明を省略する。   Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that, in the following description and drawings, the same reference numerals indicate the same or similar components, and thus descriptions of the same or similar components are omitted.

図２は、本発明に係る動作原理を説明する回路図である。   FIG. 2 is a circuit diagram illustrating the operating principle according to the present invention.

ＬＣＤピクセルの液晶セルに備えられたストレージキャパシタＣｓｔ及び液晶キャパシタＣｌｃが、電流源Ｉｃｏｎに接続されて電荷Ｑを供給される。ここで、ピクセルの駆動電流をＩｃｏｎ、その充電期間をＴｏｎとすれば、ピクセルにロードされる総電荷量は下記式（１）の通りである。   The storage capacitor Cst and the liquid crystal capacitor Clc provided in the liquid crystal cell of the LCD pixel are connected to the current source Icon and supplied with the charge Q. Here, if the drive current of the pixel is Icon and the charging period is Ton, the total charge amount loaded into the pixel is expressed by the following formula (1).

Ｑ（Ｃｌｃ＋Ｃｓｔ）＝Iｃｏｎ×Ｔｏｎ ・・・・・（１）
ピクセル電圧は下記式（２）と（３）により得られる。 Q (Clc + Cst) = Icon × Ton (1)
The pixel voltage is obtained by the following equations (2) and (3).

Ｖｌｃ＝Ｑ（Ｃｌｃ＋Ｃｓｔ）／（Ｃｌｃ＋Ｃｓｔ） ・・・・・（２）
Ｖｌｃ＝［Ｉｃｏｎ／（Ｃｌｃ＋Ｃｓｔ）］×Ｔｏｎ ・・・・・（３）
もし電流Ｉｃｏｎ、液晶キャパシタＣｌｃ及びストレージキャパシタＣｓｔの値が与えられたら、式（３）から液晶セルの電圧は充電期間Ｔｏｎにより線形的に制御されうることが分かる。これは、異なる充電期間Ｔｏｎが供給されると、ピクセルには異なる電圧が生成されうることを意味する。即ち、互いに異なる充電期間を与えることにより、互いに異なる階調レベルが得られる。 Vlc = Q (Clc + Cst) / (Clc + Cst) (2)
Vlc = [Icon / (Clc + Cst)] × Ton (3)
If the values of the current Icon, the liquid crystal capacitor Clc, and the storage capacitor Cst are given, it can be seen from Equation (3) that the voltage of the liquid crystal cell can be linearly controlled by the charging period Ton. This means that different voltages can be generated in the pixel when different charging periods Ton are supplied. That is, by providing different charging periods, different gradation levels can be obtained.

図３は、階調レベル及びスイッチ−オンパルス間の関係を示す透過率−時間曲線を図示するグラフである。   FIG. 3 is a graph illustrating a transmittance-time curve showing the relationship between gray level and switch-on pulse.

図３に示した臨界領域は、階調レベル（以下、ＧＬとも記す）調整領域に入るために必要とする液晶の最小充電期間を意味し、この臨界領域では液晶の透過率（Ｔｒ）がほとんど変わらない。例えば、２ｎ個の階調レベルを表示するためにｎビットを利用する場合、階調レベル調整領域を２ｎ部分に分割することができる。この際、各階調レベルが異なる充電期間Ｔに分割される。 The critical region shown in FIG. 3 means a minimum liquid crystal charging period required to enter the gradation level (hereinafter also referred to as GL) adjustment region. In this critical region, the liquid crystal transmittance (Tr) is almost the same. does not change. For example, when using the n bits for displaying the 2 n gradation levels, it is possible to divide the gradation level adjustment region 2 n portions. At this time, each gradation level is divided into different charging periods T.

図４は、本発明の好ましい実施の形態に係る階調具現装置の構成を示すブロック図である。   FIG. 4 is a block diagram illustrating a configuration of a gray scale implementation apparatus according to a preferred embodiment of the present invention.

本実施の形態に係る階調具現装置は、ピクセル（図示せず）に電流を供給する電流供給部２０、表示データをラッチするバッファ２１、現在入力される表示データ及びバッファ２１にラッチされた以前の表示データを加算する加算器２２、加算器２２の出力データを受信し、該出力データの値に対応するパルス幅を有するスイッチ−オンパルスＴｏｎを電流供給部２０に伝達するパルス発生部２３、パルス発生部２３に基準クロックを提供するオシレータ２４、及び電流供給部２０、加算器２２及びパルス発生部２３を制御する制御部２５を備える。   The grayscale implementation apparatus according to the present embodiment includes a current supply unit 20 that supplies current to a pixel (not shown), a buffer 21 that latches display data, display data that is currently input, and before the buffer 21 has latched it. An adder 22 for adding the display data, a pulse generator 23 for receiving the output data of the adder 22, and transmitting a switch-on pulse Ton having a pulse width corresponding to the value of the output data to the current supply unit 20, and a pulse An oscillator 24 that provides a reference clock to the generation unit 23, and a control unit 25 that controls the current supply unit 20, the adder 22, and the pulse generation unit 23 are provided.

電流供給部２０が、ポジティブ定電流源２６、ネガティブ定電流源２７及びスイッチ２８を備え、ポジティブ定電流源２６及びネガティブ定電流源２７がパルス発生部２３から伝えられるスイッチ−オンパルスＴｏｎを共通に受信し、スイッチ２８を介してピクセルに電流を供給する。この際、スイッチ２８が制御部２５によりポジティブ定電流源２６、または、ネガティブ定電流源２７の出力電流を選択的にピクセルに供給させる。   The current supply unit 20 includes a positive constant current source 26, a negative constant current source 27, and a switch 28. The positive constant current source 26 and the negative constant current source 27 commonly receive a switch-on pulse Ton transmitted from the pulse generator 23. Then, a current is supplied to the pixel via the switch 28. At this time, the switch 28 causes the control unit 25 to selectively supply the output current of the positive constant current source 26 or the negative constant current source 27 to the pixel.

以下、本実施の形態に係る階調具現装置の動作を、図５を参照しながら説明する。   Hereinafter, the operation of the grayscale implementation apparatus according to the present embodiment will be described with reference to FIG.

本実施の形態に係る階調具現装置において、初期に入力される表示データはバッファ２１によりラッチされると共に加算器２２を経てパルス発生部２３に入力される。パルス発生部２３が内部にカウンタを備えて、受信した表示データの値に対応するパルス幅を有するスイッチ−オンパルスＴｏｎを発生する。   In the gray scale implementation apparatus according to the present embodiment, display data that is initially input is latched by the buffer 21 and input to the pulse generator 23 via the adder 22. The pulse generation unit 23 includes a counter therein and generates a switch-on pulse Ton having a pulse width corresponding to the value of the received display data.

次に、図５を参照してパルス発生部２３の詳細な動作を考察する。パルス発生部２３は受信する表示データの値だけ基準クロックをカウントし、それに対応するパルス幅を有するスイッチ−オンパルスＴｏｎを発生する。ここで、Ｔｒｅｆがパルス発生部２３で基本クロックとして用いられる基準クロックの期間、または、周期を表し、Ｔ０、Ｔ１、Ｔ２…が階調レベルＧＬ０、ＧＬ１、ＧＬ２、…のそれぞれのスイッチ−オンパルスＴｏｎの幅を表す。また、ｍ０、ｍ１、ｍ２、…が受信する表示データに応じて基準クロックをカウントすることにより得られた整数を指す。スイッチ−オンパルスＴｏｎのパルス幅が、ピクセルに供給する電荷の充電期間を決定する。この充電期間が階調レベル（ＧＬ）の数に応じて、小さい時間単位に分割されうる。即ち、本発明では、パルス発生部２３に供給する基準クロックの周波数を上げることにより、充電期間を容易に分割することができる。 Next, the detailed operation of the pulse generator 23 will be considered with reference to FIG. The pulse generator 23 counts the reference clock by the value of the received display data and generates a switch-on pulse Ton having a pulse width corresponding to the reference clock. Here, Tref represents the period or period of the reference clock used as the basic clock in the pulse generator 23, and T 0 , T 1 , T 2 ... Are the respective switches of the gradation levels GL0, GL1, GL2,. -Represents the width of the on-pulse Ton. Further, m0, m1, m2,... Indicate integers obtained by counting reference clocks according to display data received. The pulse width of the switch-on pulse Ton determines the charging period of the charge supplied to the pixel. This charging period can be divided into small time units according to the number of gradation levels (GL). That is, in the present invention, the charging period can be easily divided by increasing the frequency of the reference clock supplied to the pulse generator 23.

上記動作により発生されるスイッチ−オンパルスＴｏｎが、電流供給部２０に伝えられ、これを受信するポジティブ電流源２６及びネガティブ電流源２７がパルスの持続期間だけ電流を発生する。この際、制御部２５がスイッチ２８を動作させて、所定の電流源（例えば、ポジティブ電流源）から出力される電流をピクセルに供給させて、電流を供給されるピクセルがポジティブ電荷を充電する。   The switch-on pulse Ton generated by the above operation is transmitted to the current supply unit 20, and the positive current source 26 and the negative current source 27 that receive the switch-on pulse Ton generate current for the duration of the pulse. At this time, the control unit 25 operates the switch 28 to supply a current output from a predetermined current source (for example, a positive current source) to the pixel, and the pixel to which the current is supplied charges a positive charge.

その後、次の表示データがバッファ２１及び加算器２２に入力されると、バッファ２１がラッチしていた以前の表示データを加算器２２に出力し、加算器２２が入力された次の表示データ、即ち現在の表示データとバッファ２１から入力される以前の表示データとを加算して、パルス発生部２３に伝達する。   Thereafter, when the next display data is input to the buffer 21 and the adder 22, the previous display data latched by the buffer 21 is output to the adder 22, and the next display data to which the adder 22 is input, That is, the current display data and the previous display data input from the buffer 21 are added and transmitted to the pulse generator 23.

パルス発生部２３が現在の表示データ及び以前の表示データの加算値に対応するパルス幅を有するスイッチ−オンパルスＴｏｎを発生する。これを受信した電流供給部２０が、スイッチ−オンパルスＴｏｎのパルス持続期間だけネガティブ定電流源２７の出力電流をピクセルに供給し、ピクセルにネガティブ電荷を充電する。この際、ネガティブ電荷に含まれている以前の表示データの値に対応する電荷がピクセルに充電していた以前の表示データに対応する電荷を放電させると共に、ピクセルを現在の表示データの値に基づいて新しく充電する。   The pulse generator 23 generates a switch-on pulse Ton having a pulse width corresponding to the added value of the current display data and the previous display data. The current supply unit 20 that has received this supplies the output current of the negative constant current source 27 to the pixel for the pulse duration of the switch-on pulse Ton, and charges the pixel with a negative charge. At this time, the charge corresponding to the previous display data value included in the negative charge is discharged to the pixel corresponding to the previous display data, and the pixel is based on the current display data value. And charge a new one.

次に、従来の技術と本発明とを比較して説明する。   Next, the prior art and the present invention will be compared and described.

図１に示す従来の回路が入力されるガンマ電圧を分割して階調を具現することに対して、本発明に係る階調具現装置は、基準クロックと電流源とを用いて階調を具現する。即ち、ピクセルの充電期間が、表示データに応じて基準クロックをカウントすることにより決定される。従って、基準クロックの周波数が高くなるほど、より精確で、かつ、多様な階調を具現することができる。   In contrast to the conventional circuit shown in FIG. 1 that divides the input gamma voltage to implement the gradation, the gradation implementation apparatus according to the present invention implements the gradation using a reference clock and a current source. To do. That is, the charging period of the pixel is determined by counting the reference clock according to the display data. Therefore, the higher the frequency of the reference clock, the more accurate and various gradations can be realized.

以上では、本発明を特定の好ましい実施の形態に関連して図示し説明したが、本発明はそれに限定されるものではなく、特許請求の範囲により定められる技術的範囲と分野を逸脱しない範囲内で本発明が多様に改造及び変形できるということは当技術分野で通常の知識を有する者であれば容易に分かる。   While the invention has been illustrated and described in connection with certain preferred embodiments, the invention is not limited thereto but is within the scope and scope of the technical scope defined by the claims. It will be readily apparent to those skilled in the art that the present invention can be modified and modified in various ways.

従来の階調具現装置の構成を示すブロック図である。It is a block diagram which shows the structure of the conventional gradation implementation apparatus. 本発明に係る動作原理を説明する回路図である。It is a circuit diagram explaining the principle of operation concerning the present invention. 階調レベル及びスイッチ−オンパルス間の関係を示す透過率−時間曲線を図示するグラフである。It is a graph which illustrates the transmittance-time curve which shows the relationship between a gradation level and a switch-on pulse. 本発明の実施の形態に係る階調具現装置のブロック構成を示す図である。It is a figure which shows the block configuration of the gradation implementation apparatus which concerns on embodiment of this invention. 図４のパルス発生部の詳細動作を示す波形図である。FIG. 5 is a waveform diagram showing a detailed operation of the pulse generator of FIG. 4.

符号の説明Explanation of symbols

１０ シフトレジスタ
１１ データレジスタ
１２ データラッチ
１３ レベルシフタ
１４ 基準電圧発生器
１５ Ｄ/Ａコンバータ
１６ 出力バッファ
２０ 電流供給部
２１ バッファ
２２ 加算器
２３ パルス発生部
２４ オシレータ
２５ 制御部
２６ ポジティブ定電流源
２７ ネガティブ定電流源 10 shift register 11 data register 12 data latch 13 level shifter 14 reference voltage generator 15 D / A converter 16 output buffer 20 current supply unit 21 buffer 22 adder 23 pulse generation unit 24 oscillator 25 control unit 26 positive constant current source 27 negative constant Current source

Claims (4)

液晶表示装置の階調具現装置において、
ピクセルを充電する電流を供給する電流供給部と、
表示データをラッチするバッファと、
現在入力される表示データ及び前記バッファにラッチされた以前の表示データを加算する加算器と、
前記加算器の出力データを受信し、前記出力データの値に対応するパルス幅を有するスイッチ−オンパルスを発生して前記電流供給部に伝達するパルス発生部と、
前記電流供給部、前記加算器及び前記パルス発生部を制御する制御部とを備え、
前記電流供給部が、ポジティブ定電流源、ネガティブ定電流源及びスイッチを備え、
前記ポジティブ定電流源とネガティブ定電流源とが、前記スイッチ−オンパルスを共通に受信し、前記スイッチに電流を出力し、
前記スイッチが、所定のフレームレートで前記ポジティブ定電流源、または、ネガティブ定電流源の出力電流を選択的に前記ピクセルに供給する
ことを特徴とする階調具現装置。 In a gradation implementation device of a liquid crystal display device,
A current supply for supplying a current for charging the pixel;
A buffer for latching display data;
An adder for adding the display data currently input and the previous display data latched in the buffer;
A pulse generator that receives the output data of the adder, generates a switch-on pulse having a pulse width corresponding to the value of the output data, and transmits the generated switch-on pulse to the current supply unit;
A controller that controls the current supply unit, the adder, and the pulse generation unit ;
The current supply unit includes a positive constant current source, a negative constant current source, and a switch,
The positive constant current source and the negative constant current source receive the switch-on pulse in common, and output a current to the switch,
Said switch, said at a predetermined frame rate positive constant current source, or, the gradation implementing system characterized that you selectively supplied to the said pixel output current of the negative constant current source. 前記ポジティブ定電流源及びネガティブ定電流源が、前記スイッチにより交互に選択されることを特徴とする請求項１に記載の階調具現装置。 The gray level embodying device according to claim 1 , wherein the positive constant current source and the negative constant current source are alternately selected by the switch. 液晶表示装置の階調具現方法において、
（ａ）表示データを受信してラッチし、ラッチされた該表示データを第１表示データとするステップと、
（ｂ）前記第１表示データの値に対応するパルス幅を有する第１スイッチ−オンパルスを発生するステップと、
（ｃ）前記第１スイッチ−オンパルスのパルス幅に対応する第１電流をピクセルに供給し、該ピクセルを充電するステップと、
（ｄ）前記第１表示データの次に入力される表示データを受信してラッチし、ラッチされた該表示データを第２表示データとするステップと、
（ｅ）今回のラッチでラッチされた前記第２表示データと前回のラッチでラッチされた前記第１表示データとを加算して加算表示データを生成するステップと、
（ｆ）前記加算表示データの値に対応するパルス幅を有する第２スイッチ−オンパルスを発生するステップと、
（ｇ）前記第２スイッチ−オンパルスに基づいて前記第１電流の反対極性を有する第２電流を前記ピクセルに供給し、該ピクセルを充電するステップとを含み、
今回のラッチでラッチされた前記第２表示データの次に受信される表示データを新たに第２表示データとし、今回のラッチでラッチされた前記第２表示データを新たに第１表示データとして、前記（ｄ）〜（ｇ）のステップに従って処理を行うことを特徴とする液晶表示装置の階調具現方法。 In a method for realizing a gradation of a liquid crystal display device,
A step of latches receive (a) Display data is latched the display data to the first display data,
(B) generating a first switch-on pulse having a pulse width corresponding to the value of the first display data;
(C) supplying a first current corresponding to a pulse width of the first switch-on pulse to the pixel, and charging the pixel;
And (d) step of the to receive Viewing data that is input to the next latch of the first display data to the display data latched to the second display data,
(E) generating a sum display data by adding the time of the first display data latched by the latched second display data and the previous latch in the latch,
(F) generating a second switch-on pulse having a pulse width corresponding to the value of the added display data;
(G) supplying a second current having a polarity opposite to the first current to the pixel based on the second switch-on pulse, and charging the pixel;
The Viewing data that will be received next to the second display data latched in this latch as a new second display data, the second display data latched in this latch as a new first display data A method for realizing a gradation of a liquid crystal display device , wherein processing is performed according to the steps (d) to (g). 前記第２電流が、
前記第１電流により充電されたピクセルを放電させる第１表示データの値に対応する電流と、前記ピクセルを充電する第２表示データの値に対応する電流とを含むことを特徴とする請求項３に記載の階調具現方法。 The second current is
4. The method according to claim 3 , further comprising: a current corresponding to a value of first display data for discharging the pixel charged by the first current; and a current corresponding to a value of second display data for charging the pixel. 2. The gradation implementation method according to 1.
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Publication number Priority date Publication date Assignee Title
WO2006092757A2 (en) * 2005-03-02 2006-09-08 Koninklijke Philips Electronics N.V. Active matrix display devices and methods of driving the same
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Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10105124A (en) 1996-09-30 1998-04-24 Toshiba Electron Eng Corp Liquid crystal driving circuit
JP3503463B2 (en) * 1997-02-27 2004-03-08 セイコーエプソン株式会社 Segment driver
TW420967B (en) * 1998-11-27 2001-02-01 Sanyo Electric Co Electroluminescence display device
JP2000310968A (en) * 1999-02-23 2000-11-07 Canon Inc Device and method for picture display
JP4197814B2 (en) * 1999-11-12 2008-12-17 シャープ株式会社 LED driving method, LED device and display device
US7176948B2 (en) * 2000-04-12 2007-02-13 Honeywell International Inc. Method, apparatus and computer program product for controlling LED backlights and for improved pulse width modulation resolution
KR100381869B1 (en) * 2000-10-25 2003-04-26 삼성전자주식회사 Liquid crystal display device with a function of adaptive brightness intensifier and driving apparatus and method for therefor
JP3951042B2 (en) * 2001-03-09 2007-08-01 セイコーエプソン株式会社 Display element driving method and electronic apparatus using the driving method
US20020145584A1 (en) * 2001-04-06 2002-10-10 Waterman John Karl Liquid crystal display column capacitance charging with a current source
KR100796748B1 (en) * 2001-05-11 2008-01-22 삼성전자주식회사 Liquid crystal display device, and driving apparatus thereof
US7154457B2 (en) * 2001-06-14 2006-12-26 Canon Kabushiki Kaisha Image display apparatus
US7286104B2 (en) * 2001-08-01 2007-10-23 Koninklijke Philips Electronics N.V. Method and device for gamma correction
CN102290005B (en) * 2001-09-21 2017-06-20 株式会社半导体能源研究所 The driving method of organic LED display device
US6952193B2 (en) * 2001-12-12 2005-10-04 Canon Kabushiki Kaisha Image display apparatus and image display methods
JP2004004788A (en) 2002-04-24 2004-01-08 Seiko Epson Corp Method and circuit for controlling electron device, electronic circuit, electro-optical device, driving method for the same, and electronic equipment
US7126592B2 (en) * 2002-08-26 2006-10-24 Intel Corporation Forming modulated signals that digitally drive display elements
US7277076B2 (en) * 2002-12-27 2007-10-02 Sharp Kabushiki Kaisha Method of driving a display, display, and computer program therefor
KR100542687B1 (en) * 2003-07-25 2006-01-11 매그나칩 반도체 유한회사 Apparatus of multi gray scale display using pulse width modulation
KR100542686B1 (en) * 2003-07-25 2006-01-11 매그나칩 반도체 유한회사 Apparatus of multi gray scale display using pulse width modulation
JP2005301176A (en) * 2004-04-16 2005-10-27 Sanyo Electric Co Ltd Display device
JP4367318B2 (en) * 2004-11-08 2009-11-18 セイコーエプソン株式会社 Light source control device, light source control method, and image display device

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