JPH10105124A - Liquid crystal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify circuit constitution required for multigradation display by charging and discharging associated capacity of a signal line with a constant current for only a period corresponding to a control pulse width variably set based on gradation data. SOLUTION: A latch 1 latches digital gradation data D0-D5 externally supplied. Acounter 3 counts a clock synchronizing with operation of the latch 1. A comparator 2 outputs a pulse held at a high level from at the point of time of latch by the' latch 1 to coincidence between a data value from the latch 1 and a data value from the counter 3 as a PWM data signal. A switch control circuit 4 charges or discharges the signal line (signal line capacity) by making to flow a constant current for only a period corresponding to a pulse width of the PWM data signal. Thereby, a potential of the signal line is set to a value required for obtaining desired gradation specified by gradation data D0-D5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal drive circuit for driving an active matrix type liquid crystal display,
In particular, the present invention relates to a liquid crystal drive circuit that drives this liquid crystal display so as to perform gradation display.

[0002]

2. Description of the Related Art Conventionally, an active matrix type liquid crystal display which performs multi-tone display is known. In this multi-gradation display, for example, reference voltages corresponding to the number of display gradations are generated, one of these reference voltages corresponding to the gradation display data is selected by an analog switch, and the liquid crystal display is driven by the selected reference voltage. It is done by doing.

FIG. 6 shows a conventional liquid crystal driving circuit for driving this active matrix type liquid crystal display. In this liquid crystal drive circuit, the first latch 30, the second latch 31,
And a decoder 32 is provided for each vertical pixel line of the liquid crystal display. The first latch 30 is a 3-bit grayscale data D0 input to a bus line for specifying eight levels of grayscale for each vertical pixel line in one horizontal scanning period.
-Read D2. That is, the gradation data D0-D2
Are latched by the first latch 30 and are held for one horizontal scanning period. The second latch 31 latches the gradation data D0-D2 held by the first latch 30, and supplies the gradation data D0-D2 to the decoder 32 in the next one horizontal scanning period. The decoder 32 decodes the gradation data D0-D2 from the second latch 31, and
0-S7 are output to the control terminals of the analog switches A0-A7, respectively. The analog switches A0-A7 selectively output reference voltages V0-V7 respectively supplied to input terminals in accordance with the decode signals S0-S7. That is, one of the reference voltages V0-V7 is the decode signal S
It is selected by 0-S7 and output as a liquid crystal drive voltage.

[0004]

In the above-mentioned liquid crystal driving circuit, since the display gradation is set using a reference voltage prepared in advance, it is necessary to add a new reference voltage in order to increase the number of gradations. There is. Further, since a large number of analog switches are required as the number of reference voltages increases, this increases the circuit scale and complexity of the liquid crystal drive circuit. Liquid crystal driving circuits are generally integrated on a semiconductor chip and occupy a considerable amount of chip area. Therefore, it is difficult to increase the number of display gradations without increasing the manufacturing cost. An object of the present invention is to provide a liquid crystal drive circuit having a simple circuit configuration required for multi-tone display.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal driving circuit for a liquid crystal display in which each display pixel performs gradation display depending on a signal voltage supplied via a signal line. A control means for generating a control pulse having a width variably set based on the gradation data, and charging / discharging an associated capacitance of the signal line with a constant current for a period corresponding to the width of the control pulse generated from the control means. This is achieved by a liquid crystal drive circuit including output means for setting the potential of the signal line.

According to the present invention, the output means charges and discharges the signal line with a constant current, and the control means controls the charging and discharging time based on the grayscale data. That is, the potential of the signal line changes according to the charging / discharging time, and is set to a level for obtaining a desired display gradation. This configuration can eliminate a number of reference voltage generation circuits prepared in advance in the related art.
The circuit configuration of the liquid crystal drive circuit required for multi-gradation display can be simplified.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal drive circuit according to a first embodiment of the present invention will be described with reference to the drawings. This liquid crystal drive circuit has an active matrix type liquid crystal display of 6
It is used for driving with four gradation display. FIG. 2 shows a schematic configuration of the liquid crystal drive circuit, and FIG. 1 shows the switch control circuit shown in FIG. 2 in detail. In this liquid crystal driving circuit, FIG.
, A latch 1, a comparator 2, a counter 3, and a switch control circuit 4 are provided for each vertical pixel line of the liquid crystal display. The latch 1 latches 6-bit digital gradation data D0 to D5 supplied from the outside and supplies the latched data to the comparator 2. The counter 3 counts a clock in synchronization with the operation of the latch 1. The comparator 2 outputs, as a PWM data signal, a pulse that is maintained at a high level from the latch time of the latch 1 until the data value from the latch 1 matches the data value from the counter 3. That is, PWM
The pulse width (duration) of the data signal is equal to the gradation data D0-
It is determined according to D5. The switch control circuit 4 receives the pulse signal supplied from the comparator 4, and supplies a constant current to the signal line for a time corresponding to the pulse width of the PWM data signal signal, thereby changing the signal line (strictly speaking, the signal line capacity). Charge or discharge. As a result, the potential of the signal line is set to a value necessary to obtain a desired gradation designated by the digital gradation data D0 to D5, and is taken into the pixel electrode as a liquid crystal driving voltage. Note that the above-described signal line capacitance means a capacitance attached to a signal line, and a parasitic capacitance generated between a signal line and another wiring, a parasitic capacitance generated between a signal line and a pixel electrode, or a signal line. It is configured using a capacitor or the like added to the input side of the.

The switch control circuit 4 includes inverters 10 and 11, a NOR gate 12, and an N
AND gate 13, P-channel type transistors 14, 1
5 and 18, and N-channel transistors 16, 17 and 19. Transistors 15, 16, 18, and 19 are used as analog switches. Transistors 14 and 17 are used as constant current sources. Transistor 15 is controlled by NAND gate 13,
Transistor 16 is controlled by NOR gate 12. The NAND gate 13 receives the PWM data signal and the FR signal supplied via the two-stage inverters 10 and 11, and supplies an output signal corresponding to these signals to the gate of the transistor 15. The NOR gate 12 receives the PWM data signal and the FR signal supplied through the one-stage inverter 10 and supplies an output signal corresponding to these signals to the gate of the transistor 16. The P-channel transistor 18 is connected between a power supply terminal set to the VDD level by application of the power supply voltage VDD and the output terminal, and the N-channel transistor 18 is set to the ground level by the output terminal and the supply of the power supply voltage VDD. Power terminal. The signal line of the liquid crystal display is connected to the above-mentioned output terminal. The P-channel transistor 18 is a switch for charging the signal line to the VDD level. The N-channel transistor 19 is a switch for discharging the signal line to the ground level. These two switches are used to set the potential of the signal line to a reference value in advance before charging and discharging for generating a liquid crystal driving voltage corresponding to the grayscale data.

FIG. 3 is a time chart for explaining the operation of the above-mentioned liquid crystal drive circuit. This time chart is an example of a case where the liquid crystal display is driven in an H line inversion common inversion in a normally white mode. In this case, the FR signal is inverted every horizontal scanning period (1H),
The RP1 signal temporarily falls with the fall of the FR signal, and the RP2 signal rises temporarily with the rise of the FR signal.

In the first horizontal scanning period, the FR signal is set to a low level to set the pixel electrode to a negative polarity.
The RP1 signal changes from a high level to a low level immediately after the start of the first horizontal scanning period, and the RP2 signal is maintained at a low level. In this situation, only the P-channel transistor 18 is turned on in response to the fall of the RP1 signal, and charges the signal line to the VDD level. RP1
The signal returns from the low level to the high level when the charging of this signal line is completed. The P-channel transistor 18 uses this RP
It is turned off in response to the rise of one signal.

When performing black display, the N-channel transistor 16 is turned on to discharge the potential of the signal line to the ground level in a period obtained by subtracting the time required for charging the signal line from one horizontal scanning period (1H). Set to state. Therefore, the PWM data signal is always at the high level during a period equal to one horizontal scanning period. When performing white display,
P-channel transistor 15 and N-channel transistor 16 are both turned off to maintain the charged potential of the signal line. Therefore, the PWM data signal is always at a low level during a period equal to one horizontal scanning period.
When performing halftone display, the N-channel transistor 16 is turned on for a time equal to the pulse width of the PWM data signal, and discharges the signal line to a level corresponding to the pulse width. Since the pulse width of the PWM data signal changes corresponding to the digital gradation data D0 to D5, a desired intermediate gradation can be obtained by the discharged signal line potential.

In the second horizontal scanning period, the FR signal is set to a high level in order to set the pixel electrode to a positive polarity.
The RP2 signal changes from a low level to a high level immediately after the start of the second horizontal scanning period, and the RP1 signal is maintained at a high level. In this situation, only the N-channel transistor 19 is turned on in response to the rising of the RP2 signal, and discharges the signal line to the ground level. RP2
The signal returns from the high level to the low level when the discharge of this signal line is completed. The N-channel transistor 19 uses this RP
It is turned off in response to the falling of the two signals.

When black display is performed, the P-channel transistor 15 is turned on to charge the potential of the signal line to the VDD level in a period obtained by subtracting the above-described signal line discharge time from one horizontal scanning period (1H). Is set. Therefore, the PWM data signal is always at the high level during a period equal to one horizontal scanning period. When performing white display, the P-channel transistor 15 and the N-channel transistor 1
6 are both set to the off state in order to maintain the discharge potential of the signal line. Therefore, the PWM data signal is always at a low level during a period equal to one horizontal scanning period. When performing halftone display, the P-channel type transistor 15
It is turned on for a time equal to the pulse width of the data signal, and charges the signal line to a level corresponding to the pulse width. Set to bell. Since the pulse width of the PWM data signal changes corresponding to the digital gradation data D0 to D5, a desired intermediate gradation can be obtained by the potential of the charged signal line.

Here, a liquid crystal drive circuit according to a second embodiment of the present invention will be described. This liquid crystal driving circuit has the first configuration except that the switch control circuit 4 is changed as shown in FIG.
The configuration is the same as that of the embodiment.

The switch control circuit 4 includes inverters 20 and E
An XNOR gate 21, N-channel transistors 22 and 23, and a P-channel transistor 24 are provided. Transistor 22 is used as a constant current source, and transistors 23 and 24 are used as analog switches. The transistor 23 is controlled by the EXNOR gate 21. EXNOR gate 13 is connected to inverter 20
Receive the PWM data signal and the FR signal supplied through
3 gate. P-channel type transistor 24
Is connected between a power supply terminal set to the VDD level by the supply of the power supply voltage VDD and the output terminal, and N-channel transistors 23 and 24 are connected between the output terminal and the power supply voltage VDD.
It is connected between the power supply terminal set to the ground level by the supply of D. The signal line of the liquid crystal display is connected to the above-mentioned output terminal. P-channel type transistor 24
Is a switch for charging the signal line to the VDD level, and is used to set the potential of the signal line to a reference value in advance before discharging for generating a liquid crystal drive voltage corresponding to the grayscale data.

FIG. 5 is a time chart for explaining the operation of the above-mentioned liquid crystal drive circuit. This time chart is an example of a case where the liquid crystal display is driven in the H line inversion common inversion in the normally white mode as in the first embodiment. In this case, the FR signal is applied for one horizontal scanning period (1
H), and the RP1 signal temporarily falls with the fall and rise of the FR signal.

In the first horizontal scanning period, the FR signal is set to a low level to set the pixel electrode to a negative polarity.
The RP1 signal changes from a high level to a low level immediately after the start of the first horizontal scanning period. In this situation, the P-channel transistor 24 is turned on in response to the fall of the RP1 signal, and charges the signal line to the VDD level. The RP1 signal returns from the low level to the high level when the charging of this signal line is completed. The P-channel transistor 24 is turned off in response to the rise of the RP1 signal.

When black display is performed, the N-channel transistor 23 is set to the on state in order to discharge the potential of the signal line to the ground level in a period obtained by subtracting the time required for charging from one horizontal scanning period (1H). Is done. Therefore, the PWM data signal is always at the high level during a period equal to one horizontal scanning period. When performing white display, the P-channel transistor 24 is turned off to maintain the discharge potential of the signal line. Therefore, the PWM data signal is always at a low level during a period equal to one horizontal scanning period.
When performing halftone display, the N-channel transistor 23 is turned on for a time equal to the pulse width of the PWM data signal, and discharges the signal line to a level corresponding to the pulse width. Since the pulse width of the PWM data signal changes corresponding to the digital gradation data D0 to D5, a desired intermediate gradation can be obtained by the discharged signal line potential.

In the second horizontal scanning period, the FR signal is set at a high level to set the pixel electrode to a positive polarity.
The RP1 signal changes from a high level to a low level immediately after the start of the second horizontal scanning period. In this situation, the P-channel transistor 24 is turned on in response to the fall of RP1, and charges the signal line to the VDD level. The RP1 signal returns from the low level to the high level when the charging of this signal line is completed. P-channel transistor 24 is turned off in response to the rise of RP1 signal.

When performing black display, the N-channel transistor 23 is set to the off state in order to maintain the charged potential of the signal line during a period obtained by subtracting the time required for the above-mentioned charging from one horizontal scanning period (1H). . Therefore, the PWM data is always at the high level during a period equal to one horizontal scanning period. When performing white display, the N-channel transistor 23 is turned on to discharge the signal line to the ground level. Therefore, the PWM data is always at the low level during a period equal to one horizontal scanning period. When performing halftone display, the N-channel transistor 23 is PWM
It is turned on for a time equal to the pulse width of the data signal, and discharges the signal line to a level corresponding to the pulse width. Since the pulse width of the PWM data signal changes corresponding to the digital gradation data D0 to D5, a desired intermediate gradation can be obtained by the discharged signal line potential.

In the liquid crystal driving circuit of each of the above-described embodiments, gradation display can be performed with a simple circuit configuration, so that the number of components and the number of wirings can be reduced as compared with the conventional case, and multi-gradation display can be easily performed. it can. In addition, an increase in chip area required for forming an integrated circuit can be prevented, so that an increase in cost can be suppressed.

[0022]

As described above, according to the present invention, it is possible to provide a liquid crystal driving circuit having a simple circuit configuration required for multi-gradation display.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing in detail a switch control circuit of a liquid crystal drive circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram schematically showing a configuration of a liquid crystal drive circuit according to the first embodiment of the present invention.

FIG. 3 is a time chart for explaining an operation of the liquid crystal drive circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing in detail a switch control circuit of a liquid crystal drive circuit according to a second embodiment of the present invention.

FIG. 5 is a time chart for explaining an operation of the liquid crystal drive circuit of the second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a conventional liquid crystal drive circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Latch circuit 2 ... Comparator 3 ... Counter circuit 4 ... Switch control circuit 10,11,20 ... Inverter 12 ... NOR gate 13 ... NAND gate 14,17,22 ... Constant current source 15,18,24 ... P channel Type transistors 16, 19, 23 ... N-channel type transistor 21 ... EXOR gate

Claims (2)

[Claims] 1. A liquid crystal driving circuit for a liquid crystal display in which each display pixel performs a gray scale display depending on a signal voltage supplied via a signal line, and is variably set based on gray scale data input from the outside. Control means for generating a control pulse having a width that is set, and charging and discharging the associated capacitance of the signal line with a constant current for a period corresponding to the width of the control pulse generated from the control means, thereby setting the potential of the signal line. A liquid crystal drive circuit comprising: an output unit for setting. 2. The liquid crystal driving circuit according to claim 1, wherein said output means includes a preset circuit for setting a potential of said signal line to a predetermined reference value before charging / discharging said signal line.