JP2617930B2 - Pulse output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a pulse output circuit, a reference power supply for obtaining a positive output pulse and a reference power supply for obtaining a negative output pulse are provided. A period in which the power supply values are equal is provided, and the output polarity of the push-pull driver is switched during this period.

[Industrial applications]

The present invention relates to a pulse output circuit, and particularly to an electroluminescent (EL) as a light source in an electronic printer or the like.
The present invention relates to a pulse output circuit as a driving circuit when a panel is used.

[Problems to be solved by conventional technology and invention]

Conventionally, as such a pulse output circuit, a circuit that selectively generates a pulse train of both positive and negative polarities with a relatively high voltage (100 V or more) and a high frequency (several kHz) is required. Usually, since several tens to one hundred and several tens of such circuits are required, the circuit is configured using a push-pull driver integrated into an integrated circuit.

FIG. 6 is a basic configuration diagram of a conventional circuit, and FIG. 7 is an output waveform diagram thereof. In the figure, reference numeral 61 denotes a push-pull driver, and reference numerals 61a and 61b schematically show changeover switches. Reference numeral 62 denotes a reference power supply, which is connected to the ground side of the push-pull driver 61. The operation of this power supply circuit is such that when the switch 61a is on, the switch 61b is off, the output terminal OUT outputs the weighted voltage of the reference voltage Vref and the voltage _VA , and the switch 61a turns off and the switch 61b Is turned on, only the reference voltage Vref appears in the output.
A pulse voltage as shown in FIG. 7 is obtained by turning on / off the switches 61a and 61b. FIG. 7 is a diagram showing this pulse waveform. In the figure, the solid line is an output waveform, and P1 and P2 are desired positive and negative pulses, respectively. Also, N1 and N2 are problematic spike noises. The dotted line indicates switching of the reference voltage, and O to -Vref
Is switched between. As is clear from the figure, the pulse P1 is obtained when the switch 61a is off and the switch 61b is on, and the pulse P2 is obtained when the switch 61a is on and the switch 6a is on.
Obtained when 1b is off. Therefore, the pulse width is determined by the ON time of each switch.

The spike noise N1 occurs when the reference voltage Vref switches from O → −Vref. State before switching, that is, Vref =
OV, the switch 61a is off and the switch 61b is on. On the other hand, when Vref is switched to -Vref, OUT becomes OV
Switch 61a must be turned on and the switch 61b must be turned off to maintain. However, it is very difficult to make the switching timing of the reference voltage coincide with the switching timing of the switches 61a and 61b. Therefore, if the switching of the switches 61a and 61b is slow, spike noise such as N1 is generated. The generation of the spike noise N2 is described in the same manner. That is, the state before Vref switching, that is,
When Vref = −Vref, the switch 61a is on and the switch 61b is off.
1a is off and switch 61b is on. However, V
If the switching timing of the ref and the switching timing of the switches 61a and 61b are shifted, a spike noise such as N2 is generated.

[Means and actions for solving the problems]

An object of the present invention is to provide a pulse output circuit that solves the above-mentioned problems. FIG. 1 shows a basic configuration diagram of the present invention. In the drawing, reference numeral 11 denotes a push-pull driver, and 11a and 11b.
Is a switch, 12 is a first reference power supply for supplying a negative voltage, and 13 is a second reference power supply for supplying a positive voltage. The first reference power supply 12 through the power supply terminal T ₁ switches 11b
It is connected to a second reference power supply 13 is connected to the switch 11a through the power supply terminal T _2. FIG. 2 is an output waveform of the configuration of FIG. A dotted line A is a waveform of the first reference power supply 12, and a dashed line B is a waveform of the second reference power supply 13. The output waveform is shown by the solid line, where P1 and P2 are the desired pulses. To obtain the pulse P1, the switch 11a is off and the switch 11b is on. On the other hand, to obtain the pulse P2, the switch 11a is on and the switch 11b is off. In other states, for example, when A is -Vref, the switch 11a is turned on, and if the switch 11b is turned off, the output "O" V is obtained.
Similarly, when B is + Vref, the switch 11a is turned off, and if the switch 11b is turned on, the output "O" V is obtained. When both A and B are "O" V, that is, during the period T, the output is "O" V regardless of the form of the switches 11a and 11b. In this way, if a separate power supply is used, for example, when A switches from O to -Vref, the switch 11a may be on and the switch 11b may be off to maintain the output OUT at "O" V. No spike noise is generated. On the other hand, A is −Vr
When switching from ef to OV, the switch 11a only needs to be switched on while the switch 11b remains off, and then the switch 11a must be switched by the time B switches from O to + Vref within the period T.
If a is turned off and switch 11b is turned on, B's O → +
Spike noise at the time of Vref switching can be prevented.

〔Example〕

FIG. 3 is a block diagram of an embodiment of a pulse output circuit according to the present invention. In FIG. 3, reference numeral 31 denotes an integrated push-pull driver incorporating a control circuit; 32, a first reference power supply for supplying a negative voltage; 33, a second reference power supply for supplying a positive voltage; It is a level conversion circuit. The push-pull driver 31 is housed in one chip. The push-pull driver 31 is constituted by the output terminal OUT ₁ to OUT _n inverters 311a~311n corresponding to each and thereto coupled level converter 312a~312n and shift registers 313,. The clock signal CL is supplied to the level conversion circuit 34.
K, a data input D _IN , a strobe signal STB, a polarity signal POL, and the like are input, and are input to the push-pull driver 31 after level conversion.

The operation of this circuit will be described with reference to FIG. The clock signal CLK is a shift clock for the shift register 313, and the strobe signal STB specifies the valid period of the output waveform OUT. The polarity signal POL specifies the polarity of the output waveform. Polarity signal PO in the period of the preceding t ₁
Output waveform OUT ₁ to OUT _n from the at "L" level L becomes a negative pulse, the output waveform because the period of the subsequent stage t ₂ is at "H" level is a positive pulse. A, B in front t ₁ is the output voltage waveform of the first and second reference power supply 32, 33 A
Is a negative voltage −Vref and B is an “O” voltage. The subsequent stage t ₂ is A is "O" voltage, and B is a + Vref. The switching between A and B overlaps and the period T is A
And B coincide with each other to become the “O” voltage. This period T is the same as the period T in FIG. 2, and the switching operation is completed in this period as described in FIG. During this period T, the voltage A and the voltage B coincide with each other as described above, so that a voltage waveform due to noise does not occur in the output waveform.

The 1-bit data input D _IN is level-converted by a level conversion circuit 34 such as a photocoupler or the like, and
Are sequentially shifted by the clock signal CLK. For example, when "H" is input to the level conversion circuit 312a, the level is raised to a predetermined level by this circuit and then input to the CMOS inverter 311a. When an "H" level is input to the CMOS inverter composed of P and N-channels, the N-channel side is turned on and the P-channel side is turned off. Thus negative pulse such as shown is obtained at the output Oout _1. This pulse width is equal to the strobe signal STB as described above.
Is determined by As data is sequentially transferred through the shift register 313, the output waveform is
OUT ₂ ... OUT _n is obtained. Meanwhile, in order to obtain a positive pulse, such as a subsequent stage t ₂ in order that it is sufficient to turn on the P- channel side has its gate to the "L" level may be employed to input.
Thus to obtain a negative output pulse OUT ₁ to OUT _n in for the first data input D _IN, it is possible to obtain an output pulse train OUT ₁ to OUT _n positive polarity with respect to the next data input D _IN .

FIG. 5 shows another embodiment of the pulse output circuit according to the present invention. As shown in the figure, an output stage composed of a P-channel transistor and an output stage composed of an N-channel transistor are respectively integrated in one chip, and outputs are shared. Therefore, the first output circuit 51 is a P-channel output stage.
The second output circuit 54 is composed of an N-channel output stage 541 and its shift register 542, and the second output circuit 54 is provided with level shift circuits 52 and 55 and reference power supplies 53 and 56, respectively. By configuring the push-pull driver in this way, the P and N channels are independent of each other, so that a high withstand voltage can be obtained. Further, since the level conversion circuits 312a to 312n as shown in FIG. Higher density can be achieved. Furthermore, since the P and N channels are independent, each transistor can be an open drain, and the structure can be simplified. In this case, control signals such as CLK, STB, and POL are input to the level conversion circuits 52 and 55 independently.

In the above-described embodiment, the case where the positive and negative output pulses are obtained centering on OV is described. However, the present invention is not limited to this. For example, there are two reference power sources (A) and (B). The present invention can also be applied to a configuration in which an output pulse having a shape in which the center voltage is shifted from OV is obtained by switching the voltage so as to have a predetermined voltage amplitude from a constant voltage.

Also, after completely matching the two reference power supply voltages,
Although the case where the output state of the push-pull driver is switched has been described, from the viewpoint of reducing spike noise, it is not always necessary to make the two coincide with each other. Switching may be performed.

〔The invention's effect〕

As described above, according to the present invention, a highly accurate output waveform can be obtained without generating any waveform distortion such as spike noise at the time of switching of the reference power supply and at the time of switching of the switch.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a pulse output circuit according to the present invention. 2 is an output voltage waveform and a reference voltage waveform diagram according to the present invention, FIG. 3 is a block diagram of a pulse output circuit according to an embodiment of the present invention, FIG. 4 is a signal timing chart of the circuit in FIG. FIG. 6 is a block diagram of a pulse output circuit according to another embodiment of the present invention, FIG. 6 is a diagram of a conventional basic configuration, and FIG. 7 is a diagram illustrating noise in a conventional circuit. (Explanation of reference numerals) 11, 31, 51, 54: Push-pull driver, 11a, 11b, 61a, 61b
... Switch, 12, 32, 56 ... First reference power supply circuit, 13, 33, 53
... second reference power supply circuits, 312a to 312n, 34, 52, 55 ... level conversion circuits, 313, 512, 542 ... shift registers, 511 ... P-channel output stages, 541 ... N-channel output stages,

Claims (1)

(57) [Claims] 1. A pulse output circuit, comprising: a first reference power supply that generates a first voltage; and a second reference power supply that operates independently of the first reference power supply and generates a second voltage. A power supply, a first power supply voltage supply terminal receiving the first voltage, and a second power supply voltage supply terminal receiving the second voltage;
And a push-pull driver that outputs a pulse having a potential corresponding to the first and second voltages. The push-pull driver controls the first and second reference power supplies to control the first and second voltages. Providing a period in which the levels are brought close to or in agreement with each other, and in the period, the push-pull driver is in an output state in which a pulse that changes from the first voltage level to the second voltage level is output, or A pulse output circuit that switches between an output state and an output state for outputting a pulse that changes from the voltage level to the first voltage level.