JPH07181924A - Driving circuit of display device - Google Patents

Abstract

PURPOSE:To provide a driving circuit of display device with a low power consumption by compensating a rush current which is a charging or discharging current generated at the time of the plus/minus inversion of a driving voltage driving a display part for display or owing to variation of the driving voltage. CONSTITUTION:A gradation voltage generating circuit 20 is equipped with a driving circuit 21 and a switch SW1 which is connected in series between the output terminal of the driving circuit 21 and the output terminal 24 of the gradation voltage generating circuit 20. Further, the gradation voltage generating circuit 20 is equipped with a control circuit 22 and switches SW2 and SW3 which have ON/OFF (conduction/disconnection) states controlled by two outputs S1 and S2 of the control circuit 22. The switches SW2 and SW3 are connected in parallel to the output line 25 between the driving circuit 21 and output terminal 24. The switch SW2 supplies a source voltage Vh between two kinds of source voltages Vh and Vg (Vh>=Vg) outputted from a power circuit 23 to the output line 25 or cuts if off. The switch SW3 supplies the source voltage Vg outputted form the power circuit 23 to the output line 25 or cuts if off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly to a common electrode of a matrix liquid crystal display device,
In addition, the present invention relates to a drive circuit of a display device which drives a signal wiring.

[0002]

2. Description of the Related Art Among the display devices, a conventional technique will be described especially for an active matrix type liquid crystal display device.

FIG. 2 is a block diagram of an example of a typical active matrix type liquid crystal display device (hereinafter, display device) 110. FIG. 2 is referred to in the following prior art item, and is also commonly referred to in the embodiments described later. The display device 110 includes a display unit 107 and a drive circuit 108 that drives the display unit 107 for display. In the display unit 107 of the display device 110 shown in FIG. 2, liquid crystal which is a display medium is sealed between two substrates 100 and 101 which are arranged to face each other, and one of the substrates 100 has a liquid crystal side surface. A plurality of picture element electrodes 103 are arranged in a matrix. On the substrate 100, as a switching element for driving the plurality of picture element electrodes 103,
TFT (Thin Film Transistor)
102 is arranged for each pixel electrode 103, and each TFT 10
A plurality of signal wirings (data wirings) 104, which are parallel to each other, are connected to the signal input section 2 of the second TFT 102, respectively.
In the control signal input section of, a plurality of scanning wirings (gate wirings) 1 which are parallel to each other and extend in a direction intersecting the signal wiring 104
05 is arranged.

On the liquid crystal side surface of the other substrate 101, a common electrode (not shown) is formed, for example, over the front surface of the substrate 101 or for each group of the picture element electrodes 103 connected in the row direction. Between the common electrode 101 and the picture element electrode 103, a liquid crystal capacitor that contributes to display is formed by using liquid crystal as a dielectric.

The drive circuit 108 includes the signal wirings 1
A source driving circuit 200 to which 04 is connected, and a gate driving circuit 300 to which each of the scanning wirings 105 are connected are configured. The source drive circuit 200 includes the signal wiring 10
A drive voltage for performing display drive is supplied to 4. In the following description, a digital source drive circuit in which a video signal is given in a digital signal format will be described.

FIG. 9 is a block diagram showing a configuration of a conventional digital source drive circuit 200, and FIG. 10 is an i-th line in the row direction of FIG. 2 in the digital source drive circuit 200 of FIG. 3 is a block diagram showing a configuration of a signal wiring drive circuit 109 which drives the signal wiring 104. FIG. The configuration and operation of the digital source drive circuit 200 have been filed as Japanese Patent Application Laid-Open No. 3-177890 by the applicant of the present application. In the following, for simplicity of description, it is assumed that the video signal data is composed of 2 bits (D ₀ , D ₁ ). As the digital source drive circuit 200 of the prior art, a drive circuit having a configuration as shown in FIG. 9 is used. The digital source drive circuit 200 is provided with each signal wiring 10
It is configured to include a plurality of signal wiring drive circuits 109 provided for every four.

The signal wiring drive circuit 109 is provided for each bit (D ₀ , D ₁ ) of the video signal data and is used for the sampling operation in the first stage D-type flip-flop M.
_{The SMP} , the second-stage D-type flip-flop M _H used for the hold operation, one decoder DEC, and each signal wiring 104 are provided for each of the four types of external power supply voltages V ₀ to
It is configured to include a plurality of analog switches ASW _{0 to} ASW ₃ for outputting or shutting off V ₃ to each of the signal wirings 104. In the analog switches ASW _{0 to} ASW ₃ , four kinds of gradation voltages V _{0 to} V ₃ and the decoder DEC
The control signals S _{0 to} S ₃ from are input. Various types of digital video signal data can be sampled other than the D flip-flop. In the signal wiring drive circuit 109, 2-bit video signal data has four kinds of values of 0 to 3, and the gradation supplied from the gradation voltage generation circuit 400 of FIG. 2 corresponds to each value. Voltage V _{0 to} V ₃
Any one of them is selected and output to the signal wiring 104 as a drive voltage.

The digital source drive circuit 200 operates as follows. The video signal data (D ₀ , D ₁ ) is taken into the sampling flip-flop M _SMP at the rising time of the sampling pulse T _SMPi corresponding to the i-th signal wiring 104 and held there. When the sampling of the video signal data corresponding to one horizontal scanning period of the display unit 107 is completed, an output pulse OE is supplied to the hold flip-flop M _H, video signal data (D held in the sampling flip-flop M _{SMP 0} , D ₁ ) are taken into the hold flip-flop M _H and outputted to the decoder DEC. The decoder DEC receives the 2-bit video signal data (D ₀ ,
D ₁ ) is decoded, and _{one of} the analog switches ASW _{0 to} ASW ₃ is turned on in accordance with the value (0 to 3), and any one of the four types of gradation voltages V _{0 to} V ₃ is set. , Is output as a drive voltage to the corresponding signal wiring 104.

FIG. 11 shows an example of voltage waveforms of the gradation voltages V _{0 to} V ₃ and the common electrode voltage V _com applied to the common electrode. The values of the gradation voltages V _{0 to} V ₃ are such that the voltages applied to the picture elements become higher in this order. That is, the gradation voltage V ₀
~ V ₃ is

[0010]

(1) | V ₀ −V _com | <| V ₁ −V _com | <| V ₂ −V _com | <| V ₃ −V _com | As a modification, this relationship may be reversed. As shown in FIG. 11, the grayscale voltages V _{0 to} V ₃ and the common electrode voltage V _com change in voltage level in synchronization with the polarity inversion signal POL which is inverted every one output period.

FIG. 12 shows gradation voltages V _{0 to} V ₃ seen from the common electrode to which the common electrode voltage V _com is applied. Focusing on one picture element, when the picture element is selected by the gate drive circuit 300 via the scanning wiring 105,
Potential difference | V ₀ −V _com |, | V ₁ −V _com |, |
The pixel is charged with either V ₂ −V _com | or | V ₃ −V _com |. By alternating-currently driving the common electrode in this manner, the amplitude of the voltage applied to the signal wiring 104 for obtaining a predetermined voltage between the pixel electrode 103 and the common electrode can be reduced in each horizontal scanning period, and the digital voltage can be reduced. The operating voltage of the source driver circuit can be reduced.

As an example of the configuration of the common electrode drive circuit 500 of FIG. 6, the configuration shown in FIG. 13 filed by the applicant of the present application as the application number 3-211149 is possible.
The common electrode drive circuit 500 includes an operational amplifier OP1 and a buffer circuit BUF having a complementary MOS (metal-oxide layer-silicon) structure. Each input terminal of operational amplifier OP1
A constant voltage Vhigh and a polarity inversion signal POL are input to the buffer circuit BUF, and the output of the operational amplifier OP1 is the buffer circuit BUF.
It is connected to the. The operational amplifier OP1 is a buffer circuit B
By feeding back the output Vout of the UF,
As shown in FIG. 14, the inversion amplification operation of the polarity inversion signal POL is performed.

The circuit shown in FIG. 13 is replaced by the common electrode drive circuit 5
There is essentially no difference between the case where the voltage generating circuit is used as 00 and the case where it is used as the voltage generating circuit that generates each gradation voltage of the gradation voltage generating circuit 400 in FIG. And the center voltage and the phase with respect to the polarity inversion signal POL may be in-phase or opposite-phase.

A circuit having the structure shown in FIG. 15 is used for the gradation voltage generating circuit 400 shown in FIG. Gradation voltage generation circuit 4
Reference numeral 00 connects the output of the operational amplifier OP2 to the buffer circuit BUF including a unidirectional transistor, and is configured as a unidirectional current amplifier circuit. Figure 1 shows the timing chart at this time.
6 shows.

Another example of the configuration of the signal wiring drive circuit 109 is a circuit filed by the applicant of the present application as application number 4-293528. As an example of this configuration, the circuit shown in FIG. 17 is used as the signal wiring drive circuit 109 for applying a drive signal to each signal wiring 104 in the digital source drive circuit 200 of FIG. The signal wiring drive circuit 109 has a configuration similar to that of the signal wiring drive circuit 109 shown in FIG. 10, and includes sampling flip-flops 1 and flip-flops provided for each bit D ₀ and D _{1 of the} video signal data. A plurality of holding flip-flops 2 for holding and outputting the data signals from 1 and a decoder 3 are provided. The decoder 3 is provided with a plurality of ANs provided for the number of gradations corresponding to each value of the video signal data.
A high level signal is supplied to one of the D circuits 6.

A switching signal DIS is provided to each AND circuit 6.
A bar (hereinafter, when a notation bar is attached to a symbol representing a signal, for example, DIS, the signal DIS bar is defined as an inverted signal of the signal DIS) is commonly input, and each AND
The output of the circuit 6 is input to the plurality of analog switches 4. The switching signal DIS bar is inverted via the inversion circuit 7 and input to the analog switch 8. The four kinds of gradation voltages V _{0 to} V ₃ are input to each analog switch 4, and the voltage V _DIS is input to the analog switch 8.
The output of each analog switch 4, 8 is connected in common,
It is output to the corresponding signal wiring 104.

In the signal wiring drive circuit 109 of the prior art, among the gradation voltages V _{0 to} V ₃ of a plurality of stages, the gradation voltage designated by the video signal data is applied to each signal wiring 10.
4, when the positive and negative voltages are alternately applied every horizontal scanning period, the highest gradation of the positive (or negative) gradation voltage for a certain period is started at the start of the period for applying the positive (or negative) gradation voltage. In order to obtain the specified gradation voltage by applying a voltage equal to or higher than the voltage (or lower than the lowest voltage in the case of negative voltage) to each signal wiring, a voltage equal to or higher than the highest gradation voltage (voltage equal to or lower than the lowest voltage) Only discharging (or charging) is required. Therefore,
In order to obtain each gradation voltage, the display unit 107 can be driven by the unidirectional power source that only discharges (or charges).

The power source of the charging means can also be used as the highest voltage value of the positive gradation voltage, and the power source of the discharging means can also be used as the lowest voltage value of the negative gradation voltage. It is possible to do

[0019]

FIG. 14 is a waveform diagram showing an output waveform of the common electrode drive circuit 500 shown in FIG. Note that FIG. 14 shows a waveform at the time of line inversion driving in which the polarity of the voltage applied to the common electrode is inverted every horizontal period.
The same applies hereinafter. The polarity inversion signal POL is a signal that switches between high and low levels and is inverted and amplified by the operational amplifier OP1. In this case, the polarity inversion signal POL
Is high level, the common electrode driving circuit 500 outputs a low voltage Vlow to the common electrode, and the polarity inversion signal POL
Is low level, the common electrode drive circuit 500 outputs a high voltage Vhigh to the common electrode. Therefore, when the polarity inversion signal POL is at a high level, the pixel is charged so that the pixel electrode 103 has a positive potential. When the polarity inversion signal POL is at a low level, the pixel electrode 103 is charged.
The picture elements are charged so that is at a positive potential.

In the case of the gradation voltage generating circuit 400 shown in FIG. 15, the output of each gradation voltage of the gradation voltage generating circuit 400 is
It is different from the circuit operation of the common electrode driving circuit 500 that the amplitude and the center voltage respectively correspond to the video signal data and that the phase with respect to the polarity inversion signal POL may be in-phase or in anti-phase. is there.

By the way, in the common electrode of the display device 110, there is a capacitive load between the pixel electrodes 103 sandwiching the liquid crystal layer, a capacitive load such as a parasitic capacitance between the signal wiring, and the like. When the voltage applied to the common electrode changes or when the polarity of the voltage applied to the common electrode is reversed, a charging / discharging current flows through these capacitive loads.

In the drive waveform of FIG. 14, the charge / discharge current due to the capacitive load flows as a rush current, and the peak current thereof is several hundred meters, especially at the time of polarity inversion, which is the timing of switching the level of the polarity inversion signal POL.
It is known that the number becomes A to several A.

Conventionally, the common electrode drive circuit 500 had to have the ability to basically satisfy the rush current at the time of charging / discharging by the capacitive load of the display unit 107. Therefore, for example, in the circuit of FIG. 13, an operational amplifier OP1 that can operate as fast as possible and has a large current capacity is used, and a current amplification function by a buffer circuit BUF composed of complementary transistors in the subsequent stage is used. It is necessary to configure the circuit so that such requirements are met.

The same phenomenon occurs in the gradation voltage generating circuit 400. Therefore, for example, in the circuit of FIG. 15, an operational amplifier OP2 that can operate as fast as possible and has a large current capacity is used, and further, a unidirectional buffer circuit BUF formed of unidirectional transistors in the subsequent stage is used. It is necessary to configure the circuit so that the current amplification function can meet such requirements.

However, such a circuit configuration of the prior art causes an increase in price and further an increase in power consumption which is originally unnecessary for driving the display of the display unit 107.

Further, depending on the circuit configuration or the like, the drive waveform of FIG. 14 may be distorted due to the flow of this rush current.
In some cases, the display quality may be degraded.

The present invention has been made in order to solve the above problems, and one of the objects thereof is to occur or change the driving voltage when the polarity of the driving voltage for driving the display unit is reversed. An object of the present invention is to provide a driving circuit for a display device with low power consumption by compensating for a rush current which is a charge / discharge current which is generated. Another object of the present invention is to provide a drive circuit for a display device of high display quality by reducing the distortion of the drive waveform due to the rush current. Still another object of the present invention is to realize low power consumption of the drive circuit by omitting the buffer circuit having the current amplification function in the drive circuit, and thereby the circuit configuration is lower than the conventional one. Thus, it is possible to provide a driving circuit for a display device that can be downsized and save space.

[0028]

A drive circuit for a display device according to the present invention outputs a drive signal for AC display driving a display section in which a plurality of picture elements each having a capacitance are arranged in a matrix in a predetermined cycle. A drive circuit having an output terminal for outputting the drive signal, wherein a power supply unit that generates a plurality of power supply voltages having different levels and a periodic signal that defines the period are input, and a pair of the plurality of power supply voltages is input. A voltage generating unit for generating the drive signal, which is either a voltage having a level between the power supply voltages or two or more voltages having mutually different levels and which is a rectangular wave synchronized with the periodic signal. Connected to the output terminal, and first switch means connected between the voltage generation section and the output terminal for cutting off the drive signal from the voltage generation section during a period including a level switching of the periodic signal. That period Second switch means for outputting one power supply voltage of the pair of power supply voltages to the output terminal, and the other power supply voltage of the pair of power supply voltages is output to the output terminal during the period. And a third switch means for achieving the above object.

The common electrode drive circuit of the display device of the present invention is
The pixel electrode is formed on one substrate of a pair of substrates facing each other across the display medium, and the common electrode is formed on the other substrate to form a capacitance with the pixel electrode. A common electrode drive circuit of a display device, which outputs a drive signal for driving an electrode in an alternating current display at a predetermined cycle, and has an output terminal to which the drive signal is output, the power supply generating a plurality of power supply voltages having different levels. And a period signal that defines the period, and is composed of one voltage having a level between a pair of the plurality of power source voltages or two or more voltages having different levels from each other. A voltage generator that generates one of the driving signals of a rectangular wave that is synchronized with a signal, and the voltage is connected between the voltage generator and the output terminal, and the voltage is included in a period including the level switching of the periodic signal. The drive signal from the generator A first switching means for disconnection, is connected to the output terminal, a second switching means for outputting one of the power supply voltage of said pair of power supply voltage to the output terminal in the period,
The third switching means is connected to the output terminal and outputs the other power supply voltage of the pair of power supply voltages to the output terminal during the period, thereby achieving the above object.

The drive circuit of the display device of the present invention outputs a data signal having a gradation for AC display driving of a display section in which a plurality of picture elements each having a capacitance are arranged in a matrix in a predetermined cycle. A grayscale voltage corresponding to a display grayscale can be obtained by selecting one of the grayscale voltages of a plurality of levels supplied from A data drive circuit of a display device, comprising: a data processing unit for charging a capacity of each picture element as a data signal to realize gradation display; and a gradation voltage generation circuit for generating gradation voltages of a plurality of levels. The data driving circuit is supplied with an output terminal for outputting the gradation voltage, a power supply unit for generating a plurality of power supply voltages having different levels, and a periodic signal for defining the period.
The drive signal is either a voltage having a level between a pair of the plurality of power supply voltages or a rectangular wave composed of two or more voltages having mutually different levels and synchronized with the periodic signal. A voltage generating unit that generates the voltage; and a first switch unit that is connected between the voltage generating unit and the output terminal and that cuts off the drive signal from the voltage generating unit during a period including the level switching of the periodic signal. A second switch means that is connected to the output terminal and outputs one power supply voltage of the pair of power supply voltages to the output terminal during the period; and a second switch means connected to the output terminal for the pair of power supply voltages during the period. Third switch means for outputting the other power supply voltage to the output terminal is provided, thereby achieving the above object.

In the present invention, the power supply unit may output two power supply voltages having mutually different levels.

In the present invention, the first switch means,
The second switch means and the third switch means may be field effect transistors.

In the present invention, the period may be selected as one horizontal scanning period in the display section.

In the present invention, one power supply voltage of the plurality of power supply voltages output from the power supply unit having different levels is
It may be selected as the ground potential.

[0035]

According to the present invention, in a drive circuit that charges and discharges a capacitive load for a certain period of time, the drive circuit and the load connected to its output are
Separated by the first switch means, another power source and a load are connected for a certain period by using the second switch means and the third switch means, and a part of the rush current flowing when the polarity is switched is burdened to this arbitrary power source. By doing so, the load on the drive circuit can be reduced.

According to the present invention, a rush current, which is a charging / discharging current generated when the positive / negative polarity of the driving voltage for driving the display unit is reversed, or a rush current which is generated when the driving voltage changes, is supplied to the power source with a switch. Connect for a period and select the voltage from the drive circuit.

By using these drive circuits, it is possible to save power in the drive circuits of the display device. Also,
A display device with high display quality can be realized by reducing the distortion of the drive waveform due to the rush current. Furthermore, the low power consumption allows the circuit constituent elements to be made smaller than conventional ones, thus saving the space of the drive circuit.

[0038]

EXAMPLES Examples of the present invention will be described below. However, the present invention is not limited to the following examples.

(Embodiment 1) FIG. 1 shows a gradation voltage generating circuit 2 provided in a drive circuit of an active matrix type liquid crystal display device (hereinafter referred to as a display device) 110 according to a first embodiment of the invention.
2 is a block diagram of a display device 110 in which the drive circuit of this embodiment is used, and FIG. 3 is a time chart for explaining the operation of the grayscale voltage generation circuit 20 of this embodiment. is there. The configuration of the display device 110 shown in FIG. 2 has been described in the section of the prior art with reference to FIG.
This description is incorporated in the following examples. In addition, in the present embodiment, the drive circuit 108 of the display device 110 shown in FIG.
Has the same structure as the structure described in the section of the prior art with reference to FIGS. 9 and 10, and the description thereof will be omitted in this embodiment. Further, the configuration and the circuit operation of the grayscale voltage generation circuit 20 of this embodiment shown in FIG. 1 can be used also as the common electrode drive circuit 500 shown in FIG.

The gradation voltage generating circuit 20 of FIG. 1 is provided in the drive circuit 107 of the display device 110 of this embodiment. The gradation voltage generation circuit 20 includes a drive circuit 21, and a switch SW1 connected in series between the output end of the drive circuit 21 and the output terminal 24 of the gradation voltage generation circuit 20. Further, the gradation voltage generating circuit 20 includes a control circuit 22 and a control circuit 22.
The switches SW2 and SW3 whose ON / OFF (conduction / interruption) state is controlled by the two outputs S2 and S3. The switches SW2 and SW3 are connected in parallel to an output line 25 between the drive circuit 21 and the output terminal 24. The switch SW2 outputs 2 from the power supply circuit 23.
The power supply voltage Vh of the seed power supply voltages Vh and Vg (Vh ≧ Vg) is supplied / cut off to the output line 25. The switch SW3 has a power supply voltage Vg output from the power supply circuit 23.
Is supplied to or cut off from the output line 25.

The polarity inversion signal POL output from the control circuit 600 of FIG. 2 is input to the signal generation circuit 25 provided in the gradation voltage generation circuit 20 as an example, and the signal generation circuit 25 outputs the polarity inversion signal POL. Along with
A control signal DIS which will be described later based on the polarity inversion signal POL.
To occur. Polarity inversion signal PO from the signal generation circuit 25
L is input to the drive circuit 21, and the drive circuit 21 outputs the signal VA. The signal VA output from the drive circuit 21 is
Output Vout from the output terminal 24 via the switch SW1
The power supply voltage Vh is output via the switch SW2, and the power supply voltage Vg is output via the switch SW3.
As out, it is selectively output as described later.

The drive circuit 21 includes a display unit 10 shown in FIG.
7 is supplied with a reference signal SV having a waveform serving as a reference of the drive signal applied to the drive signal 7, or the polarity inversion signal POL
Is given. The polarity inversion signal POL is, for example, a signal whose polarity is inverted every horizontal scanning period in the display unit 107. A control signal DIS is input to the control circuit 22, and the control signal DIS is supplied to the switch SW1 to control the on / off state of the switch SW1. The control signals S2 and S3 are generated in the control circuit 22 based on the control signal DIS.

As shown in FIG. 3B, the control signal DIS has the same period H as the polarity inversion signal POL,
The polarity inversion signal POL has a low level in a period L1 including the level inversion timing shown in FIG. 3A, and has a high level in the remaining period L2. In addition, the control signals S2 and S
As shown in FIGS. 3 (3) and 4 (4), 3 has a period 2H that is twice the period H of the polarity inversion signal POL, and is shown in FIG. 3 (1) of the polarity inversion signal POL. It becomes high level in each of the periods L3 and L5 including the level inversion timing, and becomes low level in each of the remaining periods L4 and L6. Further, the control signals S2 and S3 are the polarity inversion signals PO.
It becomes a high level alternately at every L level inversion timing.

That is, when the switch SW1 is turned on, the switches SW2 and SW3 are turned off, and when the switch SW1 is turned off, either the switch SW2 or the switch SW3 is turned on alternately.

The gradation voltage generating circuit 20 of this embodiment will be described below.
The operation of will be described with reference to FIG. As shown in FIG. 2, a case where the polarity inversion signal POL is input as the reference voltage SV of the drive voltage applied to the display unit 107 will be described. The polarity inversion signal POL is a signal whose level is inverted every horizontal scanning period H during the line inversion drive operation, and when the polarity inversion signal POL is at a high level, the drive circuit 21 outputs the voltage VA1 as the output VA. When the polarity inversion signal POL is at low level, the drive circuit 21 outputs the voltage V
A2 is output as the output VA. As a result, the drive circuit 21 causes the voltage VA1 and the voltage VA2 (VA1 ≧ VA2).
It produces a rectangular wave that oscillates between. Here, the phases of the output voltages VA1 and VA2 may be inverted.

In the case of the gradation voltage generating circuit 20 of this embodiment,
From the output terminal 24 of the gradation voltage generating circuit 20 to the display unit 1
At the timing at which the polarity of the voltage input to 07 and charged in the capacitance of each pixel of the display unit 107 switches from negative to positive, the switch SW1 is turned off and the drive circuit is turned on as shown in FIG. 3B. 21 and the output terminal 24 are cut off from each other. At this time, the switch SW2 is turned on, and the power supply voltage Vh of the power supply circuit 23 is connected to the output terminal 24 via the switch SW2. At this time, the switch SW3 is off, and the power supply voltage Vg of the power supply circuit 23 is equal to the output terminal 2
It is cut off with 4.

Further, at the timing when the polarity of the voltage charged in the capacitance of each picture element of the display unit 107 switches from positive to negative, the switch SW1 is turned off and the drive circuit 21 and the output terminal 24 are disconnected. . At this time, the switch SW3 is turned on, and the power supply voltage Vg from the power supply circuit 23 is connected to the output terminal 24. At this time, the switch SW2 is turned off, and the power supply voltage Vh of the power supply circuit 23 is cut off from the output terminal 24.

In the gradation voltage generating circuit 20 of the present embodiment having the above-mentioned structure and operation, the polarity inversion signal PO
The signal wiring 1 of the signal drive circuit 109 shown in FIGS. 2 and 9 at the timing when the polarity of L switches between positive and negative.
The rush current flowing through 04 and the analog switch SW is supplied from the power supply circuit 23. In particular,
When the output Vout from the gradation voltage generating circuit 20 changes from the negative polarity to the positive polarity, the switch SW2 is turned on and the switch SW3 is turned off. As a result, the rush current flowing into the capacitance in the display unit 107 is the power supply circuit 2
3 is supplied from the power supply voltage Vh. On the other hand, when the output Vout from the gradation voltage generating circuit 20 changes from the positive polarity to the negative polarity, the switch SW3 turns on and the switch SW2.
Turns off. As a result, the rush current flowing into the capacitance in the display unit 107 is supplied from the power supply voltage Vg of the power supply circuit 23. As a result, the rush current is supplied from the power supply circuit 23, and the rush current flowing through the drive circuit 21 can be reduced or eliminated.

As is clear from the above description, according to the gradation voltage generating circuit 20 of this embodiment, the polarity inversion signal P
The rush current flowing through the signal wiring 104 at the timing when the polarity of the OL is inverted, and the charge / discharge rush current generated when the voltage applied to the display unit 107 is changed are the power supply circuit 23
To bear the burden. As a result, the rush current that the drive circuit 21 bears can be significantly suppressed or eliminated, and the drive circuit 108 with low power consumption can be realized. Further, conventionally, the rush current causes the signal wiring 104
In addition, the voltage waveform supplied from the gradation voltage generating circuit 20 is distorted and the display quality is deteriorated. However, in this embodiment, the rush current is borne by the power supply circuit 23 independent of the drive circuit 21. It is possible to prevent the display quality from deteriorating. Further, in the conventional technology, a buffer circuit capable of realizing a current amplification function composed of a complementary transistor or the like is not required, so that a cost reduction effect can be obtained.
Conventionally, the power consumed by the transistors that form the buffer circuit is no longer necessary, and the power consumption is further reduced accordingly. Further, since the gray scale voltage generating circuit 20 of this embodiment itself can omit the buffer circuit used in the prior art, the power consumption in the buffer circuit can be eliminated and the gray scale signal voltage generating circuit can be eliminated. 20 is a power saving circuit. In addition, simplification of the circuit configuration is realized by omitting the buffer circuit, and the size of the circuit board can be reduced. Further, the display device can be thinned.

(Embodiment 2) FIG. 4 is a block diagram of a common electrode drive circuit 30 provided in a drive circuit 108 of a display device 110 according to Embodiment 2 of the present invention. This embodiment is similar to the first embodiment, and the corresponding parts are designated by the same reference numerals. In this embodiment, the drive circuit 108 of the display device 110 shown in FIG. 2 has the same configuration as that described in the section of the prior art with reference to FIGS. In the embodiment, the repetitive description will be omitted. The circuit operation of the common electrode drive circuit 30 of the present embodiment is similar to the circuit operation of the first embodiment described with reference to FIG. 3, and FIG. 3 will be referred to in the description of the present embodiment.

In this embodiment, the drive circuit 21 of the first embodiment is used.
Is realized by using the operational amplifier OP3. The reference signal SV or the polarity inversion signal POL is input to the inverting input terminal of the operational amplifier OP3 via the resistor R1. The non-inverting input terminal of the operational amplifier OP3 is supplied with the voltage Vr from the variable resistor RV whose both ends are connected to the high-voltage power supply voltage Vhigh and the low-potential power supply voltage Vlow, respectively. Further, the operational amplifier OP3 has a power supply voltage Vhi
gh and Vlow are supplied respectively. Operational amplifier OP
The output of 3 is connected to the source of a bidirectional switch SW1 composed of an FET (field effect transistor), and is also negatively feedback-connected to the inverting input terminal of the operational amplifier OP3 via a resistor R2. The drain of the switch SW1 is connected to the output Vout. The control signal DIS is input to the gate of the switch SW1.

Further, the switches SW2 and S of the first embodiment are
W3 is also composed of a FET. Switches SW2, SW3
The drains of are commonly connected to the output Vout. The source of the switch SW2 is supplied with the high-potential power supply voltage Vh output from the power supply circuit 23, and the source of the switch SW3 is supplied with the low-potential power supply voltage Vg output from the power supply circuit 23.

The circuit operation of the common electrode drive circuit 30 having the above structure will be described below. At the inversion timing of the polarity of the polarity inversion signal POL input to the operational amplifier OP3 of the common electrode drive circuit 30, the switch SW1 is turned off by the control signal DIS shown in FIG. 3B, and the switch SW1 turns on the operational amplifier OP3. The output VA is cut off from the output Vout of the common electrode drive circuit 30. At this time, the control signal S generated by the control circuit 22 based on the control signal DIS
2 and S3, the power supply voltage Vh becomes the output Vout by the switch SW2 as shown in FIG. 3 (3) and FIG. 4 (4). Alternatively, the power supply voltage Vg becomes the output Vout by the switch SW3.

In the present embodiment, the output voltage VA of the drive circuit 21 is charged and discharged in each period in which the polarity of the polarity inversion signal POL is different, and is the voltage V output from the drive circuit 21.
When the minimum voltage value of the voltage level of A is equal to or higher than the power supply voltage Vg (for example, the ground potential GND), a simple regulator is used for the power supply circuit 23a that outputs the power supply voltage Vh, and the power supply circuit that outputs the power supply voltage Vg. 23b is the ground potential G
By connecting ND, the power supply potentials Vh and Vg
Since it is not necessary to use a power supply circuit for outputting each, it is possible to reduce the size of the entire drive circuit 108 and save power.

In the case of the first embodiment, the rush current generated at the time of charging / discharging the capacity of each pixel of the display unit 107 at the polarity inversion timing of the polarity inversion signal POL is set to the power supply voltage Vh or the power supply voltage. Power supply circuit 23 that outputs Vg
This is because the rush current borne by the drive circuit 21 is reduced or eliminated by supplying the majority of the rush current instead of the drive circuit 21.

When the minimum voltage value of the voltage level of the voltage VA output from the drive circuit 21 is equal to or higher than the ground potential GND as described above, the output Vout is replaced by the power supply circuit 23b which outputs the power supply voltage Vg, and The display device 110 is connected to the ground potential GND through a ground wiring or the like provided in the display device 110. As a result, at the timing when the polarity of the polarity inversion signal POL is switched, the rush current flowing through the common electrode drive circuit 30 via the signal wiring 104 or the like causes the ground potential GND connected to the output Vout by the switch SW3 in the ON state. Supplied from

With the common electrode drive circuit 30 of the present embodiment having such a configuration and circuit operation, it is possible to achieve the same effect as that described in the first embodiment.

In this embodiment, the switches SW1 and SW
2. FET is used for SW3. Since the FET is bidirectional and has an extremely small on-resistance, when used as the switch circuit of the common electrode drive circuit 30 of this embodiment, the power consumption of the common electrode drive circuit 30 can be further reduced. .

Although the switch circuit of the present invention is described as the FET in this embodiment, the present invention is not limited to this embodiment, and other kinds of switches can be used. Although the circuit configuration of the present embodiment shown in FIG. 4 has been described as the common electrode drive circuit 30, the circuit configuration shown in FIG. 4 is used as the grayscale voltage generation circuit 20 shown in FIG. May be. Also in this case, the circuit operation described above in the present embodiment can be achieved,
It is possible to achieve the same effect as that described above.

(Embodiment 3) FIG. 5 is a block diagram of a grayscale voltage generation circuit 40 according to a third embodiment of the drive circuit of the present invention, and FIG. 6 shows a grayscale voltage generation circuit 40 of the present embodiment. It is a timing chart explaining operation. In the explanation below,
The circuit configuration shown in FIG. 5 will be described as the gradation voltage generating circuit shown in FIG. 2. However, the circuit configuration shown in FIG.
It can be used as the common electrode drive circuit shown in FIG. The circuit operation at that time is the same as the circuit operation of this embodiment described later.

This embodiment is similar to the second embodiment, and the same reference numerals are given to corresponding parts. In this embodiment, the drive circuit 108 of the display device 110 shown in FIG. 2 has the same configuration as that described in the section of the prior art with reference to FIGS. In the embodiment, the repetitive description will be omitted. The circuit operation of the grayscale voltage generation circuit 40 of this embodiment will be described with reference to FIG.

In this embodiment, the drive circuit 21 of the first embodiment is used.
Is realized by using the operational amplifier OP4. The reference signal SV or the polarity inversion signal POL is input to the non-inverting input terminal of the operational amplifier OP4. Operational amplifier OP4
The output of the operational amplifier OP4 is connected to the non-inverting input terminal of the same potential. Further, power supply voltages Vhigh and Vlow are supplied to the operational amplifier OP4, respectively. The output of the operational amplifier OP4 is an FET (field effect transistor).
Is connected to the source of the bidirectional switch SW1. The drain of the switch SW1 is connected to the output Vout. The control signal DIS is input to the gate of the switch SW1.

Further, the switches SW2 and SW3 of this embodiment
Is also composed of a FET. The drains of the switches SW2 and SW3 are commonly connected to the output Vout. The source of the switch SW2 is supplied with the high-potential power supply voltage Vh output from the power supply circuit 23, and the source of the switch SW3 is supplied with the low-potential power supply voltage Vg output from the power supply circuit 23. Control signals S2 and S3 from the control circuit 22 are input to the gates of the switches SW2 and SW3, respectively.

The circuit operation of the gradation voltage generating circuit 40 having the above structure will be described below.

In the gradation voltage generating circuit 40 having the configuration shown in FIG. 5, as shown in FIG. 6A, the polarity inversion signal POL whose polarity is inverted every horizontal scanning period is the operational amplifier of the drive circuit 21. It is input to the non-inverting input terminal of OP4. Since the output of the operational amplifier OP4 is connected to the inverting input terminal at the same potential, the output of the operational amplifier OP4 is shown in FIG.
The constant potential VA is obtained as shown in FIG. At the polarity inversion timing of the polarity inversion signal POL shown in FIG. 6 (1), the output VA of the operational amplifier PO4 is separated from the output Vout of the grayscale voltage generation circuit 40 by the switch SW1, and instead, the grayscale is output by the switch SW2. The output Vout of the voltage generation circuit 40 is connected to the high-potential power supply voltage Vh output from the power supply circuit 23. Alternatively, the output Vout
Is the low-potential power supply voltage Vg output from the power supply circuit 23.
To the switch SW3.

Next, at the polarity inversion timing of the polarity inversion signal POL, the switch SW1 is turned on and the operational amplifier OP4.
Output VA becomes the output Vout of the gradation voltage generating circuit 40. At this time, the switches SW2 and SW3 are turned off, and the output Vout is cut off from the power supply circuit 23. Next, at the polarity inversion timing of the polarity inversion signal POL, the output VA of the operational amplifier PO4 is separated from the output Vout of the grayscale voltage generation circuit 40 by the switch SW1, and instead, the switch SW2 outputs the output voltage VA of the grayscale voltage generation circuit 40. Output V
out is connected to the low-potential power supply voltage Vg output from the power supply circuit 23. Alternatively, the output Vout is connected to the high-potential power supply voltage Vh output from the power supply circuit 23 by the switch SW3.

In this embodiment, the output voltage VA of the drive circuit 21 is charged and discharged in each period in which the polarity of the polarity inversion signal POL is different, and is the voltage V output from the drive circuit 21.
When the minimum voltage value of the voltage level of A is equal to or higher than the power supply voltage Vg (for example, the ground potential GND), a simple regulator is used for the power supply circuit 23a that outputs the power supply voltage Vh, and the power supply circuit that outputs the power supply voltage Vg. 23b is the ground potential G
By connecting ND, the power supply potentials Vh and Vg
Since it is not necessary to use a power supply circuit for outputting each, it is possible to reduce the size of the entire drive circuit 108 and save power.

In the case of the first embodiment, the rush current generated at the time of charging / discharging the capacity of each pixel of the display unit 107 at the polarity inversion timing of the polarity inversion signal POL is set to the power supply voltage Vh or the power supply voltage. Power supply circuit 23 that outputs Vg
This is because the rush current borne by the drive circuit 21 is reduced or eliminated by supplying the majority of the rush current instead of the drive circuit 21.

When the minimum voltage value of the voltage level of the voltage VA output from the drive circuit 21 is equal to or higher than the ground potential GND as described above, the output Vout is replaced by the power supply circuit 23b which outputs the power supply voltage Vg, and The display device 110 is connected to the ground potential GND through a ground wiring or the like provided in the display device 110. As a result, at the timing when the polarity of the polarity inversion signal POL is switched, the rush current flowing through the gradation voltage generation circuit 40 via the signal wiring 104 or the like is the ground potential connected to the output Vout by the switch SW3 in the ON state. Supplied from GND.

With the gradation voltage generating circuit 40 of the present embodiment having such a configuration and circuit operation, it is possible to achieve the same effect as that described in the first embodiment.

In the present embodiment, the switches SW1 and SW
2. FET is used for SW3. Since the FET is bidirectional and has an extremely low on-resistance, when it is used as the switch circuit of the grayscale voltage generation circuit 40 of this embodiment, the power consumption of the grayscale voltage generation circuit 40 can be further reduced. You can

Although the switch circuit of the present invention is described as the FET in this embodiment, the present invention is not limited to this embodiment, and other kinds of switches can be used. Further, the circuit configuration of the present embodiment shown in FIG. 5 has been described as the gradation voltage generation circuit 40, but the circuit configuration shown in FIG. 5 should be used as the common voltage drive circuit 20 shown in FIG. You can Also in this case, the circuit operation described above in the present embodiment can be achieved, and the same effect as the effect of the present embodiment described above can be achieved.

(Embodiment 4) FIG. 7 shows signals provided for each signal wiring 104 in the digital source drive circuit (hereinafter, source drive circuit) 50 shown in FIG. 2 according to Embodiment 4 of the drive circuit of the present invention. It is a block diagram of the wiring drive circuit 60,
FIG. 6 is a timing chart for explaining the operation of the signal wiring drive circuit 60 of this embodiment. This embodiment is similar to the first embodiment, and the corresponding parts are designated by the same reference numerals.
In the present embodiment, the grayscale voltage generating circuit 400 of the display device 110 shown in FIG. 2 may use any one of the circuit configurations of the first and third embodiments, or the prior art. The well-known circuit configuration described in the above section may be used. Figure 2
The common electrode drive circuit 500 shown in FIG. 2 may use the configuration example of the second embodiment, or may have the well-known circuit configuration described in the section of the prior art.

The configuration of the signal wiring drive circuit 60 shown in FIG. 7 is a configuration for driving the i-th signal wiring 104 along the row direction of FIG. 2, and the source drive circuit 50 shown in FIG.
The signal wiring driving circuit 60 shown in FIG. 7 is provided for each signal wiring 104. In the following, for simplicity of explanation, it is assumed that the video signal data is composed of 2 bits (D ₀ , D ₁ ).

The feature of this embodiment is that the drive circuit of the present invention is incorporated in the digital source drive circuit 50 shown in FIG. The signal wiring drive circuit 60 is provided for each bit D ₀ and D ₁ of the video signal data, and is used for the sampling operation in the first stage D-type flip-flop M.
_{The SMP} , the second-stage D-type flip-flop M _H used for the hold operation, one decoder DEC, and each signal wiring 104 are provided for each of the four types of external power supply voltages V ₀ to
It is configured to include a plurality of analog switches ASW _{0 to} ASW ₃ for outputting or shutting off V ₃ to each of the signal wirings 104.

In the analog switches ASW _{0 to} ASW ₃ , four kinds of gradation voltages V _{0 to} V ₃ and the decoder DEC are used.
The control signals S _{0 to} S ₃ from are input. Various types of digital video signal data can be sampled other than the D flip-flop. The gradation voltages V _{0 to} V ₃ are output from the gradation voltage generating circuit 400,
Center voltage Vm and power supply voltage VA for each gradation voltage V _{0 to} V ₃
+ And the power supply voltage VA-. The center voltage Vm, the power supply voltage VA +, and the power supply voltage VA− have different voltage levels for each gradation voltage V _{0 to} V ₃ .

In the present embodiment, the signals DISh and DISl are input to the digital source drive circuit 50 in addition to the sampling pulse TSMPi and the output control pulse OEi. Here, the signal DISh bar is the gradation voltage V
The signal DISl is a low active signal that is active for a certain period of time after the output of A + is started. On the other hand, the signal DISl bar is a low active signal that is active for a certain period of time after the output of the grayscale voltage of VA- is started. is there.

Outputs Y0 to Y3 of the decoder DEC
Are connected to the respective one input terminals of the AND circuits 61, 62, 63, 64, respectively, and the AND circuits 61, 62, 63,
The output of the AND circuit 65 is commonly connected to each of the other input terminals of 64. The signals DISh and DISl are input to the AND circuit 65, respectively. Signal DISh
The levels of the bar and the DISl bar are respectively inverted by the inversion circuits 66 and 67 and input to the analog switches 68 and 69, respectively, to switch the switching states of the analog switches 68 and 69 between the on state and the off state.
Power supply voltages VDISH and VDISL output from the power supply circuit 23 are supplied to the analog switches 68 and 69, respectively, and outputs of the analog switches 68 and 69 are commonly connected to the signal wiring 104.

The signal wiring drive circuit 60 of this embodiment will be described below.
The operation of will be described. The output Si of the signal wiring drive circuit 60 of the present embodiment is the power supply voltage V from the gradation voltage generation circuit 400.
At the start of the period T1 in which A + is applied to the signal line 104, another arbitrary power supply voltage VDISH output from the power supply circuit 23 is temporarily set, and then the video signal data D0 and D1.
The decoder DEC described in the first embodiment according to the value of
And the gradation voltage generating circuit 4 by the circuit operation similar to the switching operation of the analog switches ASW0 to ASW3.
The power supply voltage VA + output from 00 is selected and becomes the output Si to the signal wiring 10.

On the other hand, the output Si of the signal wiring drive circuit 60 of the present embodiment is an arbitrary voltage which is once output from the power supply circuit 23 at the start of the period T2 when the voltage VA− is applied to the signal wiring 104. VDISL, and then the decoder DEC and analog switches ASW0 to ASW3 described in the first embodiment according to the values of the video signal data D0 and D1.
The power supply voltage VA− output from the grayscale voltage generation circuit 400 is obtained by the circuit operation similar to the switching operation of FIG.

The present embodiment will be described in detail below with reference to the drawings. In the signal wiring drive circuit 60 of FIG. 7, the signal polarity inversion timing, for example, in FIG.
When either the SH bar or DISL bar switches from high level to low level and becomes active (L), A
The ND circuit 65 is cut off, and by the low level output of the AND circuit 65, all the AND circuits 61 to 64 are cut off and all the low level signals are output. Therefore, all the analog switches ASW0 to ASW3 are cut off. As a result, the output Si to the signal wiring 104 is the power supply voltage V0, V1, V output from the gradation voltage generating circuit 400.
2, separated from V3.

At this time, the low-level control signals DISH bar and DISL bar are inverted by the inverting circuits 66 and 67 to the high level, and the analog switch 68 and
Conduct 69. As a result, the output Si to the signal wiring 104 is the power supply voltage VDIH output from the power supply circuit 23.
One of S and VDISL is alternately connected to power supply voltages VDIHS and VDISL in each horizontal scanning period.

On the other hand, in FIG. 8, when both the control signals DISH and DISL are switched from the low level to the high level and become non-active (H), the AND circuit 65 is turned on and the AND circuit 65 goes high. By the output of the level, all the AND circuits 61 to 64 are turned on, and the signal from the decoder DEC is output. Therefore, each of the analog switches ASW0 to ASW3 is driven by the signal from the decoder DEC. Thereby, the signal wiring 10
As the output Si to 4, the power supply voltage V0, V1, V2, or V3 output from the grayscale voltage generation circuit 400 is selected according to the video signal data D0 or D1, and the output Si is output.
Is supplied to the signal wiring 104 as.

At this time, the high-level control signals DISH bar and DISL bar are inverted by the inverting circuits 66 and 67 to the low level, and the analog switch 68 and
Shut off all 69. As a result, the output Si to the signal wiring 104 becomes the power supply voltage VD output from the power supply circuit 23.
Separated from IHS and VDISL.

As a result, the control signals DISH bar, DI
At the polarity reversal timing of the SL bar, the power supply circuit 23 for generating the power supply voltage VDISH or the voltage power supply VDISL outputs the rush current generated due to the charge and discharge due to the capacity in the display unit 107 shown in FIG. By supplying most of the voltage adjusting circuit 400 instead of the voltage adjusting circuit 400,
The rush current that the gradation voltage generating circuit 400 bears can be reduced. If the minimum voltage value of the gradation voltages V0 to V3 is equal to or higher than the ground potential (GND), the power supply circuit 2
By connecting a ground potential (GND) to the analog switch 69 shown in FIG. 7 instead of the power supply voltage VDISL from 3, the overall power saving of the signal wiring drive circuit 60 including the grayscale voltage generation circuit 400 and Miniaturization can be realized.

As described above, the signal wiring drive circuit 60 of this embodiment can achieve the same effects as those described in each of the above-described embodiments, and in addition, the signal wiring drive circuit 60 shown in FIG. It is possible to achieve power saving and downsizing.

[0087]

As is apparent from the above description, according to the drive circuit of the present invention, in the drive circuit which charges and discharges the capacitive load in a certain period, the drive circuit is switched in the period in which the positive and negative polarities are reversed. And the load connected to the output thereof are separated by the first switch means, and another power source and the load are separated by the second switch.
It is possible to lighten the load on the drive circuit by connecting the switch means and the third switch means for a certain period of time so that a part of the rush current flowing when the polarity is switched is carried by the arbitrary power supply.

According to the present invention, a rush current, which is a charging / discharging current generated when the positive / negative polarity of the driving voltage for driving the display unit is inverted, or a charging / discharging current generated by a change in the driving voltage is compensated, so that the power source is fixed to the power source by a switch. Connect for a period and select the voltage from the drive circuit.

By using these drive circuits, power consumption of the drive circuits of the display device can be reduced. Also,
A display device with high display quality can be realized by reducing the distortion of the drive waveform due to the rush current. Furthermore, the low power consumption allows the circuit constituent elements to be made smaller than conventional ones, thus saving the space of the drive circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a grayscale voltage generation circuit 20 according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a display device 110 having a configuration which is the basis of the present invention.

FIG. 3 is a timing chart of the gradation voltage generating circuit 20 of this embodiment.

FIG. 4 is a block diagram showing a common electrode circuit 30 of a display device according to a second embodiment of the invention.

FIG. 5 is a block diagram showing a grayscale voltage generation circuit 40 of a display device according to a third embodiment of the invention.

FIG. 6 is a timing chart of the grayscale voltage generation circuit 40 of this embodiment.

FIG. 7 is a block diagram of a signal wiring drive circuit 60 according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart of the signal wiring drive circuit 60 of this embodiment.

FIG. 9 is a block diagram of a source drive circuit 200 of a conventional display device.

FIG. 10 is a block diagram of a conventional signal wiring drive circuit 109.

FIG. 11 is a timing chart of a conventional circuit.

FIG. 12 is a timing chart showing each gradation voltage waveform as seen from the common electrode potential.

FIG. 13 is a block diagram showing an example of a gradation voltage generating circuit of a conventional display device.

FIG. 14 is a timing chart in the circuit of FIG.

FIG. 15 is a block diagram showing a grayscale voltage drive circuit 400 of a conventional display device.

16 is a timing chart showing the operation of the circuit of FIG.

17 is a block diagram showing another configuration example of the signal wiring drive circuit 109. FIG.

[Explanation of symbols]

 20 gradation voltage generation circuit 21 drive circuit 22 control circuit 23 power supply circuit 24 output terminal 25 output line 104 signal wiring 105 scanning wiring 107 display section 108 drive circuit 110 display device 300 gate drive circuit 500 common electrode drive circuit 600 control circuit DIS control Signal POL Polarity inversion signal SW1, SW2, SW3 Switch VA Signal Vout Output Vh, Vg Power supply voltage

Claims (7)

[Claims] 1. A drive circuit which outputs a drive signal for AC drive driving a display section in which a plurality of picture elements each having a capacitance are arranged in a matrix in a predetermined cycle, and which has an output terminal to which the drive signal is output. A power supply unit that generates a plurality of power supply voltages having different levels, and a voltage having a level between a pair of power supply voltages of the plurality of power supply voltages, to which a periodic signal that defines the cycle is input,
Or it consists of two or more voltages with different levels from each other,
A voltage generator that generates one of the driving signals of a rectangular wave that is synchronized with the periodic signal, and is connected between the voltage generator and the output terminal, and includes a period including a level switching time of the periodic signal. First switching means for cutting off the drive signal from the voltage generating part, and second switching means connected to the output terminal and outputting one power supply voltage of the pair of power supply voltages to the output terminal during the period. A drive circuit for a display device, comprising: a third switch means connected to the output terminal and outputting the other power supply voltage of the pair of power supply voltages to the output terminal during the period. 2. A pixel electrode is formed on one of a pair of substrates facing each other across a display medium, and a common electrode is formed on the other substrate to form a capacitance with the pixel electrode. A common electrode drive circuit for a display device, comprising: an output terminal for outputting a drive signal for driving the common electrode of the display section to perform an alternating current display in a predetermined cycle, the plurality of power supplies having different levels. A power supply unit that generates a voltage, and a voltage having a level between a pair of power supply voltages of the plurality of power supply voltages, to which a periodic signal that defines the period is input,
Or it consists of two or more voltages with different levels from each other,
A voltage generator that generates one of the driving signals of a rectangular wave that is synchronized with the periodic signal, and is connected between the voltage generator and the output terminal, and includes a period including a level switching time of the periodic signal. First switch means for cutting off the drive signal from the voltage generator, and second switch means connected to the output terminal and outputting one power supply voltage of the pair of power supply voltages to the output terminal during the period. A common electrode drive circuit for a display device, comprising: a third switch unit connected to the output terminal and outputting the other power supply voltage of the pair of power supply voltages to the output terminal during the period. 3. A plurality of levels of floors supplied from the outside, which outputs a data signal having a gray scale for alternating-current display driving a display section in which a plurality of picture elements each having a capacity are arranged in a matrix, in a predetermined cycle. Select one of the voltage adjustments,
Alternatively, a gradation voltage is realized by charging a voltage of a level corresponding to a display gradation as a data signal to a capacity of each picture element by creating an interpolation voltage by combining the gradation voltages of the plurality of levels and outputting the interpolation voltage. A data driving circuit of a display device, comprising: a data processing unit for generating a gray level voltage; and a gray scale voltage generating circuit for generating a gray scale voltage of a plurality of levels, wherein the data drive circuit outputs an output terminal to which the gray scale voltage is output. A power supply unit that generates a plurality of power supply voltages having different levels; and a voltage having a level between a pair of power supply voltages of the plurality of power supply voltages, to which a periodic signal that defines the cycle is input.
Alternatively, a voltage generator that is composed of two or more voltages having different levels from each other and that generates one of the driving signals of a rectangular wave that is synchronized with the periodic signal, and is connected between the voltage generator and the output terminal. First switch means for cutting off the drive signal from the voltage generator during a period including the level switching of the periodic signal, and one power supply of the pair of power supply voltages connected to the output terminal during the period. Display device comprising second switch means for outputting a voltage to the output terminal, and third switch means connected to the output terminal for outputting the other power supply voltage of the pair of power supply voltages to the output terminal Drive circuit. 4. The power supply unit has different levels from each other.
The drive circuit according to claim 1, which outputs two power supply voltages. 5. The drive circuit according to claim 1, wherein the first switch means, the second switch means, and the third switch means are field effect transistors. 6. The drive circuit according to claim 1, wherein the period is selected as one horizontal scanning period in the display section. 7. The drive circuit according to claim 1, wherein one of a plurality of power supply voltages having different levels output from the power supply unit is selected as a ground potential.