JP4299349B2 - 半導体デバイスの製造方法 - Google Patents
半導体デバイスの製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 98
- 238000000034 method Methods 0.000 claims description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000007689 inspection Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 36
- 238000005259 measurement Methods 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 10
- 230000008707 rearrangement Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Description
次に、既存の技術を使用して半導体層13に、チャネル領域15及び拡散領域16、素子分離領域17を形成する(ステップS2)。例えば、LOCOS(Local Oxidization of Silicon)又はSTI(Shallow Trench Isolation)技術等を用いて素子分離領域17を形成しても良い。また、例えば、イオン打ち込み法又はドーピング等によって拡散領域16を形成しても良い。その後、半導体層13上に、例えば、熱酸化法によってゲート絶縁酸化膜18を形成する(ステップS3)。その後、例えば、半導体層13及びゲート絶縁酸化膜18上にポリシリコンを堆積させ、フォトリソグラフィー技術によってポリシリコンをパターニングすることでゲート絶縁膜18上にゲート電極19を形成する(ステップS4)。その後、半導体層13上及びゲート電極19上に第1絶縁層20を形成する(ステップS5)。第1絶縁層20の形成後の断面図を図3(b)に示す。
14 SOIウエハ
21、27 基板コンタクト
29 外部接続パッド
30 内部回路パッド
41 配線パターン
Claims (5)
- シリコン支持基板と、前記シリコン支持基板上に形成された埋め込み酸化膜と、前記埋め込み酸化膜上に形成された半導体層と、からなるSOIウエハを用意する準備工程と、
前記半導体層内にその表面に設けられた絶縁層を含む複数の半導体機能素子と、前記半導体層及び前記埋め込み酸化膜を貫通して前記シリコン支持基板に達する複数の基板コンタクトと、を形成する素子形成工程と、
前記絶縁層上に少なくとも2つの外部接続パッドを形成するパッド形成工程と、
前記2つの外部接続パッド同士が互いに非接続となるように、前記基板コンタクトと前記外部接続パッドとを接続する配線パターンを形成するパターン形成工程と、
前記外部接続パッド間の導電度を測定する基本検査工程と、を有する半導体デバイスの製造方法。 - 前記基本検査工程において前記導電度が基準値以下の場合に、前記2つの外部接続パッドと前記2つの外部接続パッドとは異なる外部接続パッドとの間における導電度を測定する追加検査工程を更に有することを特徴とする請求項1記載の半導体デバイスの製造方法。
- 前記素子形成工程においては、前記基板コンタクトのうち少なくとも2つを接続する配線回路を前記絶縁層内に形成することを特徴とする請求項1又は2記載の半導体デバイスの製造方法。
- 前記パターン形成工程においては、1つの前記外部接続パッドと1つの前記基板コンタクトとを一組として接続する複数組の配線パターンを形成することを特徴とする請求項1又は2記載の半導体デバイスの製造方法。
- 前記基本検査工程若しくは前記追加検査工程の後に、前記複数の外部接続パッドを基準電位端子に接続する配線パターンを形成する配線工程を有することを特徴とする請求項4記載の半導体デバイスの製造方法。
Priority Applications (2)
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JP2007087400A JP4299349B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体デバイスの製造方法 |
US12/076,219 US7947514B2 (en) | 2007-03-29 | 2008-03-14 | Semiconductor device production process |
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JP2007087400A JP4299349B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体デバイスの製造方法 |
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JP2008251585A JP2008251585A (ja) | 2008-10-16 |
JP4299349B2 true JP4299349B2 (ja) | 2009-07-22 |
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JP2007087400A Active JP4299349B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体デバイスの製造方法 |
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Families Citing this family (1)
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US8896102B2 (en) * | 2013-01-22 | 2014-11-25 | Freescale Semiconductor, Inc. | Die edge sealing structures and related fabrication methods |
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JP3530158B2 (ja) | 2001-08-21 | 2004-05-24 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6800562B1 (en) * | 2003-03-05 | 2004-10-05 | Advanced Micro Devices, Inc. | Method of controlling wafer charging effects due to manufacturing processes |
JP5154000B2 (ja) | 2005-05-13 | 2013-02-27 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP4837939B2 (ja) | 2005-05-13 | 2011-12-14 | ラピスセミコンダクタ株式会社 | 半導体装置、及び半導体装置の製造方法 |
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US20080241976A1 (en) | 2008-10-02 |
JP2008251585A (ja) | 2008-10-16 |
US7947514B2 (en) | 2011-05-24 |
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