JP4298276B2 - Photoelectric conversion device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photoelectric conversion device, and more particularly, to a photoelectric conversion device in which a plurality of unit pixels each having a plurality of transistors for reading a signal from a photoelectric conversion region and the photoelectric conversion region are arranged two-dimensionally.
[0002]
[Prior art]
In recent years, CMOS type photoelectric conversion elements have been reconsidered due to the merit that they can be operated with a single power source and have a lower power consumption than CCD type, and the light receiving unit and peripheral circuit can be manufactured by the same CMOS process and are easy to integrate. There is a movement toward commercialization. Since a CMOS type photoelectric conversion device has a large number of elements per pixel, it is required to increase the aperture ratio by wiring a metal layer in multiple layers.
[0003]
FIG. 14 is an equivalent circuit diagram of the CMOS photoelectric conversion device described in Patent Document 1, and FIG. 15 is a layout diagram of the CMOS photoelectric conversion device. 16 is a cross-sectional view taken along line XX of FIG. 15 (adjacent pixels are not shown). In FIG. 15, only four pixels are shown. In the following description, only the pixel relating to the photodiode portion PD2 will be described.
[0004]
Around the photodiode portion PD2, there are a gate 2 of a transfer transistor M2, a floating diffusion (FD) 7, a gate 3 of a reset transistor M3, a gate 6 of a selection transistor M5, a gate 4 of an amplification transistor M4, and an output. Line 5 is provided. Further, TX is a control line for supplying the gate potential of the transfer transistor M2, RES is a control line for supplying the gate potential of the reset transistor M3, and SEL is a control line for supplying the gate potential of the selection transistor M5. φTX is a control signal that gives the gate potential of the transfer transistor M2, φRES is a control line signal that gives the gate potential of the reset transistor M3, and φSEL is a control signal that gives the gate potential of the selection transistor M5.
[0005]
[Patent Document 1]
JP-A-11-195576 [0006]
[Problems to be solved by the invention]
As shown in FIGS. 15 and 16, the drive line of the CMOS photoelectric conversion device has a three-layer structure including a polysilicon layer, an aluminum first layer, and an aluminum second layer.
[0007]
When shrinking the chip size, the simplest method is to reduce the layout of this conventional example to a desired size as it is. However, if the chip size is shrunk by this method, it is difficult to reduce the size in the height direction even if the size can be reduced in the vertical and horizontal directions.
[0008]
According to the conventional example described with reference to FIGS. 14 to 16, since two metal (aluminum) layers are used for wiring, there is a limitation even if the distance h (shown in FIG. 16) from the light receiving surface is reduced. is there. In other amplification CMOS photoelectric conversion devices, there are cases where the area of the light receiving portion is further increased by using three metal layers. In this case, the distance from the light receiving surface is higher than h in FIG. turn into. In a sensor having a high height from the light receiving surface of the chip, the sensitivity is lowered by an optical system having a small F number. In particular, in a sensor such as a digital camera that requires high image quality, the problem is that the sensitivity is lowered by an optical system having a small F number.
[0009]
Accordingly, an object of the present invention is to provide a configuration in which the height from the light receiving surface is reduced when the pixel size is shrunk in a photoelectric conversion device such as the above-described CMOS photoelectric conversion device.
[0010]
[Means for Solving the Problems]
The photoelectric conversion device of the present invention includes a photoelectric conversion region, a transfer transistor that transfers signal charges from the photoelectric conversion region to a storage region, a reset transistor that resets the storage region, and an amplification transistor that amplifies the signal charge. , A plurality of pixels having a wiring connecting the storage region, the control electrode of the amplification transistor, and the source or drain region of the reset transistor are two-dimensionally arranged,
In a photoelectric conversion device having a control line for applying a potential to the control electrode of the transfer transistor, an output line for outputting a signal from the amplification transistor, and a power supply line connected to the amplification transistor,
A plurality of the photoelectric conversion regions are connected to the control electrode of the amplification transistor via the plurality of transfer transistors,
The control electrode of the transfer transistor and the control line are constituted by a first wiring layer which is a polysilicon layer, and the wiring, the output line and the power supply line are constituted by a second wiring layer,
The wiring, the output line, and the power supply line are arranged in parallel, and the wiring is arranged between the power supply line and the output line ,
The output line and the power line intersect perpendicularly to the control line,
The control electrode of the reset transistor is connected to a wiring for reset, and the wiring for reset is configured by the first wiring layer in parallel with the control line,
Further, a color filter is disposed on the second wiring layer through a planarizing film .
[0011]
In the embodiment described below, a photodiode is used as the element constituting the photoelectric conversion region, and a MOS transistor is used as the transistor. However, other elements may be used.
[0012]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
Example 1
FIG. 1 is a layout diagram showing the configuration of a first embodiment of the photoelectric conversion device of the present invention, and FIG. 2 is a cross-sectional view taken along the section aa ′ of FIG. FIG. 3 is an equivalent circuit diagram of the photoelectric conversion device of FIG.
[0014]
1 to 3, reference numeral 1 denotes a photoelectric conversion region (photodiode section), and 2 denotes a gate electrode of a transfer MOS transistor M <b> 2 for transferring charges accumulated in the photoelectric conversion region 1 to a floating diffusion (FD) region 7. Reference numeral 3 denotes a gate electrode (to be a control electrode) of the reset MOS transistor M3, 4 denotes a gate electrode of the amplification MOS transistor M4 connected to the FD region 7, 5 denotes an output line, and 6 denotes a selection MOS transistor M5 It is a gate electrode. In FIG. 2, 8 is a color filter, and 9 is an on-chip lens for condensing light on the photoelectric conversion region 1. As an element constituting the photoelectric conversion region, for example, a bipolar transistor configuration BASIS, electrostatic induction transistor (SIT), or the like that accumulates and reads charges in the base can be used (the same applies to other embodiments).
[0015]
In the horizontal direction of FIG. 1, the gate control line TX of the transfer MOS transistor M2, the gate control line RES of the reset MOS transistor M3, and the gate control line SEL of the selection MOS transistor M5 are wired by a polysilicon layer, and are vertically The output line 5 and the power line VDD are laid out so as to be wired with an aluminum layer or an aluminum alloy layer. In FIG. 3, φRES represents a control line signal for providing the gate potential of the resetting transistor M3, and φSEL represents a control signal for providing the gate potential of the selecting transistor M5.
[0016]
As apparent from the layout diagram of FIG. 1 and the cross-sectional view of FIG. 2, the gate electrode 2 and the gate control line TX of the transfer MOS transistor M2, the gate electrode 3 and the gate control line RES of the reset MOS transistor M3, and the selection MOS The gate electrode 6 and the gate control line SEL of the transistor M5 and the gate electrode 4 of the amplification MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as the gate electrode.
[0017]
When the layout is performed as in the present embodiment, only two wiring layers of a polysilicon layer and a metal layer are used. Therefore, the distance h from the light receiving surface shown in FIG. 2 is compared with the conventional example shown in FIG. It is getting smaller.
[0018]
With the configuration of this example, it was possible to realize a good image quality without decreasing the sensitivity, and even without decreasing the sensitivity even with an optical system having a small F number.
[0019]
Note that the present invention can be suitably used for a photoelectric conversion device including a selection transistor as described in Embodiment 1, but can also be applied to a configuration in which a selection transistor is not provided. The following embodiment will explain this configuration.
[0020]
(Example 2)
FIG. 4 is a layout diagram showing the configuration of the second embodiment of the photoelectric conversion device of the present invention, and FIG. 5 is an equivalent circuit diagram of the photoelectric conversion device of FIG. 4 and 5, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and a part of the description is omitted.
[0021]
The configuration of the light beam conversion device of this embodiment is the same as that of the photoelectric conversion device of Embodiment 1 shown in FIGS. 1 to 3 except that there is no selection MOS transistor M5 and gate control line SEL. A photoelectric conversion device excluding the selection MOS transistor is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-112018.
[0022]
In the horizontal direction of FIG. 4, the gate control line TX of the transfer MOS transistor M2 and the gate control line RES of the reset MOS transistor M3 are wired by a polysilicon layer, and the output line 5 and the power supply line VDD are aluminum layers in the vertical direction. Or it is laid out so as to be wired with an aluminum alloy layer.
[0023]
As is apparent from the layout diagram of FIG. 4, the gate electrode 2 and gate control line TX of the transfer MOS transistor M2, the gate electrode 3 and gate control line RES of the reset MOS transistor M3, and the gate electrode of the amplification MOS transistor M4 4 is formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as the gate electrode.
[0024]
In this embodiment, the same effect as in the first embodiment can be obtained, and the aperture ratio of the pixel is increased (the area of the photoelectric conversion region is increased) because there is no gate electrode, gate control line SEL, etc. of the selection MOS transistor M5. )be able to.
[0025]
(Example 3)
FIG. 6 is an equivalent circuit diagram of a third embodiment of the photoelectric conversion device of the present invention. FIG. 7 is a layout view showing the configuration of the third embodiment of the photoelectric conversion device of the present invention, and FIG. 8 is a cross-sectional view taken along the line bb ′ of FIG. 6 to 8, the same components as those of FIGS. 1 to 3 are denoted by the same reference numerals, and a part of the description is omitted.
[0026]
This embodiment shows a two-pixel common amplification CMOS type photoelectric conversion device using one reset MOS transistor and one amplification MOS transistor in common for two photoelectric conversion regions.
[0027]
Reference numerals 1a and 1b denote photoelectric conversion regions of the photodiodes PD1a and PD1b, 2a and 2b denote gate electrodes of transfer MOS transistors M2a and M2b, 3 denotes a gate electrode of a reset MOS transistor M3, and 4 denotes a gate electrode of an amplification MOS transistor M4. Reference numeral 5 denotes an output line.
[0028]
In the horizontal direction of FIG. 7, two gate control lines TXa and TXb of the transfer MOS transistors M2a and M2b and one gate control line RES of the reset MOS transistor M3 are wired with a polysilicon layer, and vertically The output line 5 and the power supply line VDD are laid out so as to be wired with an aluminum or aluminum alloy layer.
[0029]
As apparent from the layout diagram of FIG. 7 and the sectional view of FIG. 8, the gate electrodes 2a and 2b of the transfer MOS transistors M2a and M2b and the gate control lines TXa and TXb, the gate electrode 3 of the reset MOS transistor M3 and the gate control. The line RES and the gate electrode 4 of the amplification MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as the gate electrode.
[0030]
In this embodiment, since the layout is based on an equivalent circuit common to two pixels, since only two transistors are used per pixel, the aperture ratio is further increased as compared to the second embodiment. High sensor can be made. Furthermore, since only two wiring layers of a polysilicon layer and a metal layer are used, the distance h from the light receiving surface (photoelectric conversion region surface) shown in FIG. 8 is smaller than that of the conventional example.
[0031]
According to this embodiment, a sensor with higher sensitivity than the conventional example can be realized, and even with an optical system having a small F number, good image quality can be realized without lowering the sensitivity.
[0032]
(Example 4)
FIG. 9 is an equivalent circuit diagram of a fourth embodiment of the photoelectric conversion device of the present invention. FIG. 10 is a layout diagram showing the configuration of the fourth embodiment of the photoelectric conversion device of the present invention, and FIG. 11 is a cross-sectional view taken along the line cc ′ of FIG. 9 to 11, the same components as those of FIGS. 1 to 3 are denoted by the same reference numerals, and a part of the description is omitted.
[0033]
This embodiment shows a four-pixel common amplification CMOS type photoelectric conversion device using one reset MOS transistor and one amplification MOS transistor in common for four photoelectric conversion regions.
[0034]
1a, 1b, 1c, 1d are photoelectric conversion regions of photodiodes PD1a, PD1b, PD1c, PD1d, 2a, 2b, 2c, 2d are gate electrodes of transfer MOS transistors M2a, M2b, M2c, M2d, 3 is a reset MOS The gate electrode of the transistor M3, 4 is the gate electrode of the amplification MOS transistor M4, and 5 is the output line.
[0035]
In the horizontal direction of FIG. 10, four gate control lines TXa to TXd of the transfer MOS transistors M2a to M2d and one gate control line RES of the reset MOS transistor M3 are wired with a polysilicon layer, and vertically The output line 5 and the power supply line VDD are laid out so as to be wired with an aluminum or aluminum alloy layer.
[0036]
As apparent from the layout diagram of FIG. 10 and the cross-sectional view of FIG. 11, the gate electrodes 2a to 2d and the gate control lines TXa to TXd of the transfer MOS transistors M2a to M2d, the gate electrode 3 of the reset MOS transistor M3 and the gate control The line RES and the gate electrode 4 of the amplification MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as the gate electrode.
[0037]
In this embodiment, since the layout is based on an equivalent circuit common to four pixels, only 1.5 transistors are used per pixel. Therefore, the aperture ratio is further increased as compared with the third embodiment. An even more sensitive sensor can be made. Further, since only two wiring layers of a polysilicon layer and a metal layer are used, the distance h from the light receiving surface shown in FIG. 11 is smaller than that of the conventional example.
[0038]
According to this embodiment, a sensor with higher sensitivity than the conventional example can be realized, and even with an optical system having a small F number, good image quality can be realized without lowering the sensitivity.
[0039]
(Example 5)
FIG. 12 is a sectional view of a fifth embodiment of the photoelectric conversion device of the present invention. The same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and a part of the description is omitted.
[0040]
In FIG. 12, the right side A of the alternate long and short dash line indicates a pixel area as shown in FIG. 2, and the left side B of the alternate long and short dash line indicates a peripheral circuit area. In the peripheral circuit region B of FIG. 12, 10 is a gate electrode of a MOS transistor, 11 is a wiring, 12 and 14 are a source wiring and drain wiring of a MOS transistor, and 13 is a wiring. The gate electrode 10 and the wiring 11 are formed of a polysilicon layer, the source wiring 12 and the wiring 13 are formed of a first metal layer, and the drain wiring 14 is formed of a second metal layer.
[0041]
In the present embodiment, the peripheral circuit region B is formed of a total of three layers of two metal layers as in the conventional case, whereas the pixel region A is formed of a total of two layers of one polysilicon layer and one metal layer. . Therefore, the distance h from the light receiving surface (photoelectric conversion region surface) can be reduced only in the pixel region without changing the configuration of the peripheral circuit (h << h 'in FIG. 12).
[0042]
According to the present embodiment, it is possible to realize a good image quality without lowering the sensitivity even in an optical system having a small F-number, by simply changing the configuration of the pixel region while maintaining the conventional peripheral circuit configuration.
[0043]
(Example 6)
FIG. 13 is a sectional view of a sixth embodiment of the photoelectric conversion device of the present invention. The same components as those in FIGS. 1 to 3 and FIG.
[0044]
In FIG. 13, the right side A of the alternate long and short dash line indicates the pixel area as shown in FIG. 2, and the left side B of the alternate long and short dash line indicates the peripheral circuit area. In the peripheral circuit region B of FIG. 13, 10 is the gate electrode of the MOS transistor, 11 is the wiring, 12 and 17 are the source wiring and drain wiring of the MOS transistor, and 13, 15 and 16 are the wiring.
[0045]
The gate electrode 10 and the wiring 11 are formed of a polysilicon layer, the source wiring 12 and the wiring 13 are formed of a metal first layer, the wirings 15 and 16 are formed of a metal second layer, and the drain wiring 17 is a metal third layer. Formed in layers.
[0046]
In the present embodiment, the peripheral circuit region B is formed by a total of four layers of one polysilicon layer and three metal layers as usual, whereas the pixel region A is formed by two layers of one polysilicon layer and one metal layer. It is configured. For this reason, the distance h from the light receiving surface (photoelectric conversion region surface) can be reduced only in the pixel region without changing the configuration of the peripheral circuit (h << h 'in FIG. 13).
[0047]
According to the present embodiment, it is possible to realize a good image quality without lowering the sensitivity even in an optical system having a small F-number, by simply changing the configuration of the pixel region while maintaining the conventional peripheral circuit configuration.
[0048]
Next, an imaging system using the photoelectric conversion device of each of the above embodiments will be described. Based on FIG. 17, an embodiment when the photoelectric conversion device of the present invention is applied to a still camera will be described in detail.
[0049]
FIG. 17 is a block diagram showing a case where the solid-state imaging device of the present invention is applied to a “still video camera”.
[0050]
In FIG. 17, reference numeral 101 denotes a barrier that serves both as lens protection and a main switch, 102 denotes a lens that forms an optical image of a subject on a solid-state imaging device (photoelectric conversion device) 104, and 103 denotes a variable amount of light passing through the lens 102. 104, a solid-state imaging device 104 for capturing an object imaged by the lens 102 as an image signal, 106 an A / D converter for performing analog-digital conversion of an image signal output from the solid-state imaging device 104, 107 Is a signal processing unit that performs various corrections and compresses the image data output from the A / D converter 106, 108 is a solid-state image sensor 104, an image signal processing circuit 105, an A / D converter 106, and signal processing. The timing generation unit 109 outputs various timing signals to the unit 107, 109 controls various operations and the entire still video camera. 110 is a memory unit for temporarily storing image data, 111 is an interface unit for recording or reading on a recording medium, and 112 is a semiconductor for recording or reading image data. A removable recording medium such as a memory 113 is an interface unit for communicating with an external computer or the like.
[0051]
Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
[0052]
When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on.
[0053]
Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the diaphragm 103, and the signal output from the solid-state imaging device 104 is converted by the A / D converter 106 and then sent to the signal processing unit 107. Entered. Based on this data, exposure calculation is performed by the overall control / calculation unit 109.
[0054]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.
[0055]
Next, based on the signal output from the solid-state image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
[0056]
Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state image sensor 104 is A / D converted by the A / D converter 106 and is written to the memory unit by the overall control / calculation 109 through the signal processing unit 107. Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Alternatively, the image may be processed by directly entering a computer or the like through the external I / F unit 113.
[0057]
Although the embodiments of the present invention have been described above, the preferred embodiments of the present invention are the embodiments described below.
[0058]
(Embodiment 1) A plurality of unit pixels having a photoelectric conversion region and a plurality of transistors for reading signals from the photoelectric conversion region are arranged two-dimensionally,
A photoelectric conversion device comprising: a control line for applying a potential to the control electrodes of the plurality of transistors; an output line for outputting a signal from the unit pixel; and a power supply line connected to at least one of the plurality of transistors. ,
Each of the control electrodes of the plurality of transistors and the control line is configured by a first wiring layer, and the output line and the power supply line are configured by a second wiring layer. .
[0059]
(Embodiment 2) A photoelectric conversion device, wherein at least one of the plurality of transistors is an insulated gate transistor.
[0060]
(Embodiment 3) The photoelectric conversion device according to Embodiment 1 or 2, wherein the first wiring layer is a polysilicon layer.
[0061]
(Embodiment 4) The photoelectric conversion device according to Embodiment 1 or 2, wherein the second wiring layer is an aluminum layer or an aluminum alloy layer.
[0062]
(Embodiment 5) The photoelectric conversion device according to Embodiment 1 or 2, wherein the first wiring layer and the second wiring layer intersect at a right angle.
[0063]
(Embodiment 6) The photoelectric conversion device according to Embodiment 1 or 2, wherein a color filter is arranged through a planarizing film.
[0064]
(Embodiment 7) The photoelectric transistor according to Embodiment 1, wherein the plurality of transistors are a transfer transistor that transfers a signal charge from the photoelectric conversion region to a storage region, and a reset transistor that resets the storage region. Conversion device.
[0065]
(Embodiment 8) The photoelectric conversion apparatus according to Embodiment 7, wherein the unit pixel includes an amplification transistor that amplifies the signal charge.
[0066]
(Embodiment 9) The photoelectric conversion device according to Embodiment 7 or 8, further including a selection transistor that selects a specific photoelectric conversion region in the unit pixel.
[0067]
(Embodiment 10) The photoelectric conversion device according to Embodiment 7 includes an amplification transistor that amplifies the signal charge, and a plurality of the photoelectric conversion regions are connected to the input portion of the amplification transistor via the transfer transistor. A photoelectric conversion device characterized by that.
[0068]
(Embodiment 11) A pixel region in which a plurality of the unit pixels are arranged two-dimensionally has a wiring composed of the first wiring layer and the second wiring layer, and a circuit for operating the pixel region is arranged. 2. The photoelectric conversion device according to Embodiment 1, wherein the peripheral region is formed of a wiring layer of three or more layers.
[0069]
(Embodiment 12) The photoelectric conversion device according to any one of Embodiments 1 to 11, an optical system for imaging light onto the photoelectric conversion device, and signal processing for processing an output signal from the photoelectric conversion device And an imaging system.
[0070]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the height from the surface of the photoelectric conversion region, and it is possible to provide good image quality without lowering the sensitivity even with an optical system having a small F number. .
[Brief description of the drawings]
FIG. 1 is a layout diagram illustrating a configuration of a first embodiment of a photoelectric conversion apparatus according to the present invention.
FIG. 2 is a cross-sectional view taken along the line aa ′ of FIG.
3 is an equivalent circuit diagram of the photoelectric conversion device in FIG. 1. FIG.
FIG. 4 is a layout diagram showing a configuration of a second embodiment of the photoelectric conversion apparatus of the present invention;
5 is an equivalent circuit diagram of the photoelectric conversion device of FIG. 4. FIG.
FIG. 6 is an equivalent circuit diagram of a third embodiment of the photoelectric conversion device of the present invention.
FIG. 7 is a layout diagram showing a configuration of a third embodiment of the photoelectric conversion apparatus of the present invention.
8 is a cross-sectional view taken along the line bb ′ of FIG.
FIG. 9 is an equivalent circuit diagram of a fourth embodiment of the photoelectric conversion apparatus of the present invention.
FIG. 10 is a layout diagram showing a configuration of a fourth embodiment of the photoelectric conversion apparatus according to the present invention;
11 is a cross-sectional view taken along the line cc ′ of FIG.
FIG. 12 is a cross-sectional view of a fifth embodiment of the photoelectric conversion device of the present invention.
FIG. 13 is a cross-sectional view of a sixth embodiment of the photoelectric conversion device of the present invention.
FIG. 14 is an equivalent circuit diagram of a conventional CMOS photoelectric conversion device.
FIG. 15 is a layout diagram of the CMOS photoelectric conversion device.
16 is a cross-sectional view taken along line XX in FIG.
FIG. 17 is a block diagram showing a case where the photoelectric conversion device of the present invention is applied to a still video camera.
[Explanation of symbols]
1 Photoelectric conversion area (photodiode part)
2 Gate electrode 3 of transfer MOS transistor M 2 3 Gate electrode 4 of reset MOS transistor M 3 Gate electrode 5 of amplification MOS transistor M 4 Output line 6 Gate electrode 7 of selection MOS transistor M 5 Floating diffusion (FD) region 8 Color filter 9 On-chip lens TX, TXa to TXd Transfer MOS transistor gate control line RES Reset MOS transistor gate control line SEL Selection MOS transistor M5 gate control line VDD Power supply line

Claims (4)

A photoelectric conversion region; a transfer transistor that transfers signal charges from the photoelectric conversion region to a storage region; a reset transistor that resets the storage region; an amplification transistor that amplifies the signal charge; the storage region and the amplification transistor A plurality of pixels having a wiring connecting the control electrode and the source or drain region of the reset transistor are arranged two-dimensionally,
In a photoelectric conversion device having a control line for applying a potential to the control electrode of the transfer transistor, an output line for outputting a signal from the amplification transistor, and a power supply line connected to the amplification transistor,
A plurality of the photoelectric conversion regions are connected to the control electrode of the amplification transistor via the plurality of transfer transistors,
The control electrode of the transfer transistor and the control line are constituted by a first wiring layer which is a polysilicon layer, and the wiring, the output line and the power supply line are constituted by a second wiring layer,
The wiring, the output line, and the power supply line are arranged in parallel, and the wiring is arranged between the power supply line and the output line ,
The output line and the power line intersect perpendicularly to the control line,
The control electrode of the reset transistor is connected to a wiring for reset, and the wiring for reset is configured by the first wiring layer in parallel with the control line,
Furthermore, a color filter is disposed on the second wiring layer through a planarizing film, and the photoelectric conversion device is characterized in that: The photoelectric conversion device according to claim 1 , wherein the second wiring layer is an aluminum layer or an aluminum alloy layer. In the pixel region in which a plurality of the pixels are arranged in a two-dimensional manner, the wiring including the wiring, the control line, the output line, and the power supply line includes the first wiring layer and the second wiring layer. is composed of two wiring layers that are, according to claim 1 or 2 peripheral region circuit is arranged for operating the pixel region is characterized in that wires are composed of three or more wiring layers Photoelectric conversion device. It has a photoelectric conversion device given in any 1 paragraph of Claims 1-3 , an optical system which focuses light on this photoelectric conversion device, and a signal processing circuit which processes an output signal from this photoelectric conversion device. An imaging system characterized by the above.

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