JP4747858B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus.

  2. Description of the Related Art Conventionally, various studies have been made on signal reading methods in imaging apparatuses. For example, in the following Patent Document 1, a signal reading method for the purpose of expanding the dynamic range is shown. 12 and 13 are timing charts showing the configuration and operation of the pixel circuit of the fourth embodiment listed in FIGS. 12 and 13 of Patent Document 1, respectively. As described above, the object and effect of the present invention is not to suppress the occurrence of flicker, but to increase the dynamic range. However, since it can be applied to the suppression of flicker generation under fluorescent lamp illumination, it is introduced as a conventional example. .

  As shown in FIG. 12, in the pixel circuit of the CMOS image sensor, two transfer switches of a first transfer switch MTX1 and a second transfer switch MTX2 are provided for one pixel, and the first transfer switch MTX1 and A capacitor CFD1 is provided between the second transfer switch MTX2 and a capacitor CFD2 is provided between the transfer switch MTX2 and the amplification transistor MSF. As shown in FIG. 13, by controlling the signal φTX2, the capacitance attached to the gate of the amplification transistor MSF can be switched between the capacitance CFD1 and the capacitance CFD2 connected in parallel or the capacitance CFD2 alone. ing.

The photo-generated carriers stored in the photodiode PD have a capacitance CFD1 and a capacitance because the gate voltage ΦTX1 of the first transfer switch MTX1 becomes high level while the gate voltage ΦTX2 of the second transfer switch MTX2 is high level. Distributed and transferred to CFD2. Thereafter, the gate voltage ΦTX1 of the first transfer switch MTX1 is set to a low level, and a signal generated by the photogenerated carriers accumulated in the capacitors CFD1 and CFD2 is read. At this time, the voltage V _FD2 applied to the gate of the amplification transistor MSF is Q _{PD as} the charge amount of photogenerated carriers, and C _FD1 and C _{FD2 as} the capacitance values of the capacitors CFD1 and CFD2, respectively.
V _FD2 = Q _PD / (C _FD1 + C _FD2 )
It becomes.

Next, after the charge accumulated in the capacitor CFD1 is transferred to the capacitor CFD2 by some method, the gate voltage ΦTX2 of the second transfer switch MTX2 is set to a low level, and the signal generated by the photogenerated carriers accumulated in the capacitor CFD2 is read. _Assuming that the voltage V _FD2 ′ applied to the gate of the amplification transistor MSF is
V _FD2 '= Q _PD / C _FD2
It becomes.

Here, when comparing V _FD2 and V _FD2 ′, V _FD2 is lower by C _{FD1 of} the denominator. That is, the sensitivity is lowered.

In a luminance region where flicker occurs and the accumulation time is longer than the blinking cycle of the light source of the illuminating device, that is, more than half the cycle of the AC commercial power supply, the accumulation time is extended to more than half the cycle of the power supply. In order to suppress the occurrence of flicker, the sensitivity of the pixel is lowered. That is, a signal based on the voltage V _FD2 applied to the gate of the amplification transistor MSF in a state where charges are distributed and accumulated in the capacitors CFD1 and CFD2 is used. As described above, the occurrence of flicker can be suppressed by reducing the sensitivity of the pixel circuit.

On the other hand, the voltage applied to the gate of the amplification transistor MSF in the state where the charge is accumulated only in the capacitor CFD2 in order to increase the sensitivity of the pixel in the luminance region where flicker does not occur, which can be operated with an accumulation time of more than half of the power cycle. The signal by V _FD2 'is used. In this way, the occurrence of flicker can be suppressed by switching the signal used depending on the luminance.

  However, the image pickup apparatus disclosed in Patent Document 1 must be provided with two capacitors CFD1 and CFD2 and two transfer switches MTX1 and MTX2 in one pixel, which complicates the circuit configuration and increases the manufacturing cost of the image pickup apparatus. There is a problem of inviting.

  By the way, as inventions related to an image sensor that shares floating diffusion (FD) among a plurality of pixels, there are inventions described in Patent Documents 2 to 5 below. Patent Document 2 relates to driving of MOS transistors connected in series, and charges remaining in the second group of photoelectric conversion elements after the signal charges of the second group of photoelectric conversion elements are mixed in the first group of photoelectric conversion elements. The solid-state image sensor which discharges is shown. Patent Document 3 discloses a solid-state imaging device that suppresses variations between pixels by driving the pixel unbalance that occurs when an amplification transistor is shared by a plurality of pixels by a full-surface selection signal wiring. ing. Patent Document 4 discloses an image sensor in which a plurality of photoelectric conversion units are provided in each pixel and the dynamic range at the time of shooting is expanded by varying the accumulation time in each photoelectric conversion unit. Yes. In Patent Document 5, photocharge generated in the photoelectric conversion unit is transferred to the floating gate, signal detection is performed, and then the charge is accumulated again by reverse transfer to the photoelectric conversion unit again. A solid-state imaging device is shown in which a plurality of data having different accumulation times can be taken out.

However, the inventions described in Patent Documents 2 to 5 cannot solve the problems related to the imaging apparatus disclosed in Patent Document 1.
JP 2000-165754 A Japanese Patent Laid-Open No. 06-334920 JP 2004-172950 A JP 2002-199284 A Japanese Patent Laid-Open No. 2004-015291

  The present invention has been made in order to solve the above-described problems, and it is possible to change the sensitivity of a pixel in accordance with subject brightness with an inexpensive and simple configuration without providing a special component. An object of the present invention is to obtain an imaging device that suppresses occurrence.

In order to achieve the above object, a first aspect of the present invention is directed to a plurality of pixels including a photoelectric conversion unit and a semiconductor having transfer means for transferring charges output from the photoelectric conversion unit, and charges transferred from the transfer means. Capacitor means for holding the signal, signal amplification means for amplifying and outputting a signal corresponding to the charge held in the capacitor means, reset means for resetting the charge held in the capacitor means, and a signal read target A pixel circuit having a pixel selection means for selecting a pixel, and an all-pixel readout mode for sequentially reading out signals based on charges output from all the pixels, and a signal based on charges output from the pixels thinned out as appropriate In an imaging apparatus having a pixel decimation readout mode for reading out, the signal amplification means, the reset means, and the pixel selection means are shared between adjacent pixels. Further comprising a luminance determination means for determining whether the subject luminance is equal to or greater than a predetermined threshold value such that the charge accumulation time of the photoelectric conversion unit is equal to or less than the blinking cycle of the light source of the illumination device, and transfer within each pixel Each means has a gate, and a dopant having the same polarity as the capacitor means is formed on the capacitor means side (hereinafter referred to as a capacitor means side portion) in a semiconductor portion below the gate. It is doped thinner than the capacitor means, and the semiconductor portion under the gate is not doped with a dopant on the photoelectric conversion portion side (hereinafter referred to as a photoelectric conversion side portion), or the capacitor means side portion and The dopant of the same polarity is doped thinner than the capacitor means side portion, or the dopant of the opposite polarity to the capacitor means side portion is doped. The pixel thinning readout mode includes a normal luminance mode in which the pixel circuit is driven with normal sensitivity when the luminance determining unit determines that the subject luminance is less than the threshold, and the subject luminance is equal to or higher than the threshold. A high luminance mode for driving the pixel circuit at a lower sensitivity than the normal sensitivity when determined, and the pixels to be thinned and the pixels to be read in the pixel thinning readout mode include the signal amplification unit, In the relationship between the adjacent pixels sharing the reset unit and the pixel selection unit, and in the high luminance mode, the gate voltage of the pixel to be read out of the plurality of pixels is set to a high level, When the charge generated by the photoelectric conversion unit of the pixel to be read is transferred to the capacitor means or the like, the potential is The photoelectric conversion unit of the pixel to be extracted, the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, and the capacitance means, the gate of the pixel to be thinned out in this order When the voltage of the gate of the pixel to be read is set to a low level and the potential of the capacitor is read, the voltage of the gate of the pixel to be read is high. During the transition from the level to the low level, the potential always decreases in the order of the photoelectric conversion side portion of the pixel to be read out, the capacitance means side portion of the pixel to be read out, and the capacitance means, and the capacitance means In addition, the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitance means side portion of the pixel to be thinned out by the photoelectric conversion unit of the pixel to be read out. The use as capacitor for holding the generated electric charges, lowering the potential of said capacitor means, to lower the sensitivity of the pixel is obtained by adapted to suppress the occurrence of flicker with a simple configuration.

According to a second aspect of the present invention, a plurality of pixels made of a semiconductor having a photoelectric conversion unit and a transfer unit that transfers charges output from the photoelectric conversion unit, and a capacitor unit that holds charges transferred from the transfer unit, A signal amplifying means for amplifying and outputting a signal corresponding to the charge held in the capacitance means; a reset means for resetting the charge held in the capacitance means; and a pixel for selecting a signal to be read. A pixel circuit having pixel selection means, and an all-pixel readout mode for sequentially reading out signals based on charges output from all pixels, and a pixel-thinning-out readout mode for reading out signals based on charges output from appropriately thinned pixels. In the imaging apparatus, the signal amplification means, the reset means, and the pixel selection means are shared between adjacent pixels, and the transfer means in each pixel Each having a gate, and a dopant having the same polarity as that forming the capacitor means is formed on the capacitor means side (hereinafter referred to as a capacitor means side portion) in a semiconductor portion below the gate. The photoelectric conversion part side (hereinafter referred to as the photoelectric conversion side part) in the semiconductor part below the gate is doped with a dopant or has the same polarity as the capacitor means side part. Is doped thinner than the capacitance means side portion, or is doped with a dopant having a polarity opposite to that of the capacitance means side portion, and a pixel to be read out and a pixel to be read out in the pixel thinning readout mode Is the relationship between the adjacent pixels sharing the signal amplification means, reset means, and pixel selection means. When the pixel thinning readout mode, when transferring charge generated by the photoelectric conversion portion of the read that the pixel of the plurality of pixels to said capacitor means and the like, potential, the pixel serving as the read target The photoelectric conversion unit, the photoelectric conversion side portion of the pixel to be read out, the capacitance means side portion of the pixel to be read out, and the capacitance means become lower in this order, and when reading the potential of the capacitance means, While the voltage of the gate of the pixel to be changed from the high level to the low level, the potential is always the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, the capacitance means In addition to the capacitance means, the thinned pixel photoelectric conversion unit, photoelectric conversion side portion, and capacitance means side portion, By using it as a capacitor for holding the charge generated by the photoelectric conversion unit of the pixel to be read, the potential of the capacitor means is lowered, the sensitivity of the pixel is lowered, and flicker is generated with a simple configuration. It can be suppressed.

  According to a third aspect of the present invention, in the imaging apparatus according to the second aspect, in the pixel thinning readout mode, the subject luminance is such that the charge accumulation time of the photoelectric conversion unit is equal to or less than the blinking cycle of the light source of the lighting device. A normal luminance mode in which the pixel circuit is driven with a normal sensitivity when the threshold is less than a predetermined threshold, and a high luminance in which the pixel circuit is driven with a sensitivity lower than the normal sensitivity when the subject luminance is equal to or higher than the threshold. Mode, and in the high luminance mode, the voltage of the gate of the pixel to be read out of the plurality of pixels is set to a high level, and the charge generated by the photoelectric conversion unit of the pixel to be read out is When transferring to the capacitance means and the photoelectric conversion unit of the pixel to be thinned out, the potential is the photoelectric conversion unit of the pixel to be read out, the potential of the pixel to be read out The electric conversion side portion, the capacitance means side portion of the pixel to be read out, and the capacitance means become lower in this order, and the voltage of the gate of the pixel to be thinned is kept at a high level, and the pixel to be read out When the potential of the capacitor means is read by setting the gate voltage to a low level, the potential is always set to the read target while the gate voltage of the pixel to be read changes from a high level to a low level. In this order, the photoelectric conversion side portion of the pixel, the capacitance means side portion of the pixel to be read out, and the capacitance means become lower in this order.

  According to the first aspect of the present invention, when the subject luminance is not less than a predetermined threshold value such that the charge accumulation time of the photoelectric conversion unit is not more than the blinking cycle of the light source of the lighting device, the sensitivity is lower than the normal sensitivity. The high-luminance mode for driving the pixel circuit is entered. Then, in this high luminance mode, the voltage of the gate of the transfer means for the pixel to be read out of the plurality of pixels is set to a high level, and the charge generated by the photoelectric conversion unit of the pixel to be read is set as the capacity means or the like The potential is lowered in the order of the photoelectric conversion unit of the pixel to be read, the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, and the capacitance means. . Thereby, the electric charge generated by the photoelectric conversion unit of the pixel to be read can be transferred to the capacitor means and the photoelectric conversion side portion and the capacitor means side portion in the pixel to be read.

  In addition, after the above charge transfer process, the gate voltage of the transfer means of the pixel to be read is kept at a high level while the gate voltage of the transfer means of the pixel to be read is set to a low level, When the potential is read, while the gate voltage of the transfer means of the pixel to be read transitions from the high level to the low level, the potential is always the photoelectric conversion side portion of the pixel to be read, the pixel to be read The capacity means side portion and the capacity means are made lower in this order. As a result, the charge transferred to the capacitor means or the like in the above charge transfer process can be prevented from returning to the photoelectric conversion unit of the pixel to be read out, and thus generated by the photoelectric conversion unit of the pixel to be read out. After the transferred charges are transferred to the capacitor means and the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitor means side portion of the thinned pixel without leakage, the potential of the capacitor means can be read out.

  In addition, as described above, after the charge generated by the photoelectric conversion unit of the pixel to be read is transferred to the capacitor means and the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitance means side portion of the thinned pixel Reading out the potential of the capacitor means means that, in addition to the capacitor means, the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitance means side portion of the pixel to be thinned are generated by the photoelectric conversion unit of the pixel to be read. This leads to use as a capacitor for holding electric charge. Therefore, in the high luminance mode, the sensitivity of the pixel can be lowered by lowering the potential of the capacitor means. In other words, it is possible to suppress the occurrence of flicker by changing the sensitivity of the pixel according to the subject brightness with an inexpensive and simple configuration without providing a special component.

  According to the second aspect of the present invention, in the pixel thinning readout mode, when the charge generated by the photoelectric conversion unit of the pixel to be read out of the plurality of pixels is transferred to the capacitor means or the like, the potential is read out. The photoelectric conversion portion of the pixel to be read, the photoelectric conversion side portion of the pixel to be read out, the capacitance means side portion of the pixel to be read out, and the capacitance means in this order. Thereby, the electric charge generated by the photoelectric conversion unit of the pixel to be read can be transferred to the capacitor means and the photoelectric conversion side portion and the capacitor means side portion in the pixel to be read.

  In addition, after the above charge transfer process, when the potential of the capacitor means is read, the potential is always the same as the read target while the voltage of the gate of the transfer means of the pixel to be read changes from high level to low level. In this order, the photoelectric conversion side portion of the pixel, the capacitance means side portion of the pixel to be read out, and the capacitance means are sequentially lowered. As a result, the charge transferred to the capacitor means or the like in the above charge transfer process can be prevented from returning to the photoelectric conversion unit of the pixel to be read out, and thus generated by the photoelectric conversion unit of the pixel to be read out. After the transferred charges are transferred to the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitance means side portion of the pixel to be thinned out without leakage, the potential of the capacitance means can be read out.

  In addition, as described above, the charge generated by the photoelectric conversion unit of the pixel to be read is transferred to the photoelectric conversion unit, the photoelectric conversion side portion, and the capacitance means side portion of the pixel to be thinned, and then the capacitance unit In addition to the capacitor means, in addition to the capacitor means, the photoelectric conversion unit of the pixel to be thinned out, the photoelectric conversion side part, and the capacitor means side part are charged with the charges generated by the photoelectric conversion part of the pixel to be read out. It leads to using as capacity to hold. Therefore, in the high luminance mode, the sensitivity of the pixel can be lowered by lowering the potential of the capacitor means. In other words, it is possible to suppress the occurrence of flicker by changing the sensitivity of the pixel according to the subject brightness with an inexpensive and simple configuration without providing a special component.

  Hereinafter, an image pickup apparatus according to a best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of the imaging apparatus 100. The imaging device 100 captures an image and outputs it as a corresponding electrical signal, a signal processing unit 20 that processes an output signal 50 output from the imaging unit 10, and a process output from the signal processing unit 20. The control unit 40 includes a control unit 40 that receives a result signal (processing result signal) 60 and outputs a control signal 70 to the imaging unit 10 to control each unit of the imaging unit 10 and the like. The imaging unit 10 has a large number of pixel circuits 11.

  Usually, in a pixel circuit, various components such as a photodiode, a transfer switch, a capacitor, an amplification transistor, a reset switch, and a selection switch described later are provided for each pixel. In such a configuration, many components must be mounted on one pixel, and it is difficult to reduce the size of the pixel circuit. Therefore, in the present invention, the pixels other than the photodiode and the transfer switch are shared between a plurality of adjacent pixels to reduce the pixel size.

  FIG. 2 is a schematic diagram showing a configuration of a pixel circuit 11 that shares a pixel other than a photodiode and a transfer switch between four adjacent pixels. In the figure, four pixels are shown among many pixels. The pixel circuit 11 outputs, for each of the pixels 1, 2, 3, and 4, photodiodes (photoelectric conversion units) PD1, PD2, PD3, and PD4 that convert light into electric signals, and photodiodes PD1, PD2, PD3, and PD4. Transfer switches (transfer means) MTX1, MTX2, MTX3, and MTX4 that transfer the signal charges that have been transferred, and hold the signal charges transferred from the transfer switches MTX1, MTX2, MTX3, and MTX4 between four adjacent pixels Capacitance (capacitance means) CFD as floating diffusion, amplification transistor (signal amplification means) MSF that amplifies and outputs a signal corresponding to the charge held in the capacitance CFD, and resets the charge held in the capacitance CFD A reset switch (reset means) MRES and a selection switch (pixel selection means) MSEL for selecting a pixel from which a signal is to be read are shared.

  FIG. 3 is an example of a plan view of a semiconductor constituting the pixels 1, 2, 3, 4 and the capacitor CFD, and FIG. 4 is a cross-sectional view taken along the line A-A ′ in FIG. 3. The transfer switches MTX1, MTX2, MTX3, and MTX4 in FIG. 2 have gates TX1, TX2, TX3, and TX4, respectively. Hereinafter, the voltages applied to the gates TX1, TX2, TX3, and TX4 are referred to as ΦTX1, ΦTX2, ΦTX3, and ΦTX4, respectively.

  In the transfer switches MTX1, MTX2, MTX3, and MTX4 of each pixel, CFD side (close to CFD) capacitances CD12 and CD22 (and capacitances CD32 and CD42 (not shown) in the semiconductor portion under the gates TX1, TX2, TX3, and TX4 ) (Capacitor side portion in claims) is thinly doped with a dopant having the same polarity as that forming the capacitor CFD. In addition, in the semiconductor portion under the gates TX1, TX2, TX3, TX4, capacitances CD11, CD21 (and not shown) on the respective photodiodes PD1, PD2, PD3, PD4 side (near PD1, PD2, PD3, PD4) (Capacitance CD31, CD41) part (photoelectric conversion side part in claims) is not doped with dopant and has the same impurity and concentration as the semiconductor substrate, or the same as CD12, CD22, CD32, CD42, respectively Polar dopants are doped thinner than CD12, CD22, CD32, CD42, or are doped with dopants of opposite polarity to CD12, CD22, CD32, CD42, respectively.

  In this pixel configuration, the potential on the silicon surface when the voltages φTX1 to φTX4 applied to the gates TX1 to TX4 of the pixels 1 to 4 are both at a low level, as shown in FIG. The portions of the illustrated capacitances CD31 and CD41) are the highest, and the portion having the next highest potential is CD12 and CD22 (and the capacitances CD32 and CD42 not shown). The next highest potential parts are photodiodes PD1, PD2, PD3, and PD4, and the lowest potential part is CFD. In this specification, “low potential” means that the potential well is deep.

  The pixel circuit 11 is configured to read out signals based on the charges output from all the pixels 1, 2, 3, and 4 sequentially when capturing a still image, and the pixel 1 when capturing a moving image or displaying a finder. Only the signal based on the charge output from any one of 2, 3, 3 or the pixel 4 is read out, and the pixel thinning mode in which the signal based on the charge output from other pixels is not read out is provided.

  6 to 10 are timing charts showing the operation of the pixel circuit 11 shown in FIG. In the all-pixel reading mode, the signals of the pixels 1, 2, 3, and 4 are sequentially read according to the timing chart shown in FIG. Therefore, flicker generation cannot be suppressed in the all-pixel readout mode. However, considering the application of the pixel circuit 11 to a digital still camera or the like, normally, in the case of still image imaging using all-pixel readout, it takes time to read out, so it is necessary to use it together with an external mechanical shutter or the like. It is common. Therefore, in this case, since the accumulation time is controlled by an external shutter, the occurrence of flicker is not a problem.

  Next, a method of suppressing the occurrence of flicker in the pixel thinning readout mode for reading out pixels in a skipped manner will be described below. In this mode, since it is necessary to read out signals quickly, the pixels are read out in a blinking manner, so that only the signal of pixel 1 is used and the signals of pixels 2 to 4 are not used. The pixel thinning readout mode has a normal luminance mode and a high luminance mode according to the subject luminance, and the control unit 40 selectively switches to either mode to drive the pixel circuit 11.

  Whether the pixel circuit 11 is driven in the normal luminance mode or the high luminance mode is determined by determining whether or not the subject luminance is equal to or higher than a predetermined threshold in the signal processing unit (luminance determination unit) 20. Is done. The determination of the subject luminance may be performed by a logic circuit provided separately inside the imaging unit. Here, the predetermined threshold is, for example, a value such that the charge accumulation time of the photodiodes PD1, PD2, PD3, and PD4 is equal to or less than ½ of the commercial power supply cycle (blink cycle of the fluorescent lamp illumination device). . The pixel circuit 11 is driven with a normal sensitivity setting in the normal luminance mode, and is driven with a low sensitivity setting in the high luminance mode.

First, the driving method in the normal luminance mode, that is, when the sensitivity of the pixel is not lowered will be described. As shown in FIG. 7, when driven in the normal luminance mode timing chart, the gate voltages ΦTX2, ΦTX3, and ΦTX4 of the transfer switches MTX2, MTX3, and MTX4 remain at a low level at the time of reading, so that the charge accumulated in the photodiode PD1 Is transferred only to the capacitor CFD by the transfer switch MTX1. At this time, the voltage V _FD ′ applied to the gate of the amplification transistor MSF is Q _PD1 , where the charge amount of photogenerated carriers accumulated in the photodiode PD1 is C _PD1 and the capacitance value of the capacitor CFD is C _FD.
V _FD '= Q _PD1 / C _FD
Thus, the sensitivity of the pixel circuit 11 remains high.

  FIG. 11 shows the photodiode PD1 of the pixel 1 in the pixel thinning readout mode, the capacitance CD11 on the photodiode PD1 side of the pixel 1, the capacitance CD12 on the CFD side of the pixel 1, the capacitance CFD, the capacitance CD22 on the CFD side of the pixel 2, and the pixel 2 The change in potential on the silicon surface of the capacitor CD21 on the photodiode PD2 side and the photodiode PD2 of the pixel 2 is shown. The photodiodes PD3 and PD4, the capacitors CD31 and CD41, and the capacitors CD32 and CD42 of the pixels 3 and 4 are the same as the photodiode PD2, the capacitor CD21, and the capacitor CD22 of the pixel 2, and are not shown. In the figure, the left side shows the potential change in the normal luminance mode, and the right side shows the potential change in the high luminance mode.

  The operation in the normal luminance mode will be described in detail with reference to FIGS. First, as shown in “pixel 1 reset” in FIG. 7, the gate voltage φTX1 of the transfer switch MTX1 of the pixel 1 is set to the high level, and the charge accumulated in the PD1 is reset by the reset transistor MRES via the capacitor CFD. . At this time, as shown in “Reset” in FIG. 11, the gate voltage φTX1 and the impurity concentrations of the photodiode PD1, the capacitor CD11, the capacitor CD12, and the capacitor CFD are the photodiode PD1, the capacitor CD11, the capacitor CD12, and the capacitor CFD. Since the potential is set to decrease in this order, the charge of the photodiode PD1 is completely transferred to the capacitor CFD, and a complete reset is performed. Next, as shown in FIG. 7, when the gate voltage φTX1 is set to the low level, accumulation of photogenerated charges is started in PD1.

  After the accumulation time has elapsed, first, for correlated double sampling to reduce noise, the capacitor CFD is reset while the gate voltage φTX1 is kept at a low level, and then the gate voltage φSEL of the selection transistor MSEL is set to high. Read the reset level. The potential at this time is as shown in “reset level reading” on the left side of FIG.

  Next, the gate voltage φTX1 is set to a high level, and photogenerated charges are transferred from the photodiode PD1 to the capacitor CFD as shown in “Charge transfer” on the left side of FIG.

  After completion of the above charge transfer, the gate voltage φTX1 is set to low level. At this time, as shown in “intermediate states 1 and 2 in which φTX1 transits from a high level to a low level” on the left side in FIG. 11, the capacitances CD11 and CD12 are always generated while the gate voltage φTX1 transits from a high level to a low level. Since the impurity concentrations of the capacitors CD11, CD12, and CFD are set so that the potential decreases in the order of CDF and CDF, when the gate voltage φTX1 becomes low level, the “signal level readout” on the left side of FIG. As shown in FIG. 2, the photogenerated charge can be transferred only to the capacitor CFD or under the capacitors CD12, CD22, CD32, and CD42 when the charge is large.

  After the above charge transfer, the signal potential is read out. At this time, the charge accumulation height shown in “Signal level reading” on the left side of FIG. 11 corresponds to the signal level (signal voltage) that becomes the gate input voltage of the amplification transistor MSF, and the sensitivity remains high. Become. Note that the signals of the pixels 2 to 4 are not read for pixel thinning readout.

Next, a driving method in the case of reducing the sensitivity of the pixel in order to suppress the occurrence of flicker in a high luminance mode, that is, in a high luminance area where flicker is generated that cannot be operated in an accumulation time of half or more of the cycle of the power supply will be described. . As shown in FIG. 8, when driven by the timing chart of the high luminance mode, the charges stored in the photodiode PD1 are transferred because the gate voltages φTX2, φTX3, and φTX4 of the transfer switches MTX2, MTX3, and MTX4 are at a high level during reading. By the switch MTX1, the capacitance CFD and the photodiodes PD2, PD3, PD4 are distributed and transferred. At this time, the voltage V _FD applied to the gate of the amplification transistor MSF is set such that the capacitance values of the photodiodes PD2, PD3, and PD4 are C _PD2 , C _PD3 , and C _PD4 , respectively.
V _FD = Q _PD1 / (C _FD + C _PD2 + C _PD3 + C _PD4 )
It becomes. Thereby, the sensitivity of the pixel circuit 11 is reduced, and the occurrence of flicker can be suppressed.

  The operation in the high luminance mode will be described in detail with reference to FIGS. As shown in FIG. 11, the operation and potential at the time of reset and accumulation are the same as those in the normal luminance mode. However, in the high luminance mode, as shown in the timing chart of FIG. 8, the gate voltages φTX2, φTX3, and φTX4 of the transfer switches MTX2, MTX3, and MTX4 are set to the high level before resetting for reset level reading.

  After the accumulation time has elapsed, for correlated double sampling, the gate voltage φRES of the reset switch MRES is set to a high level while the gate voltage φTX1 of the transfer switch MTX1 is kept at a low level, and the capacitor CFD and the photodiode PD2, Reset PD3 and PD4. Next, after setting the gate voltage φRES to a low level, the gate voltage φSEL of the selection transistor MSEL is set to a high level to read the reset level. The potential at this time is as shown in “reset level reading” on the right side of FIG. 11. Since the gate voltages φTX2, φTX3, and φTX4 are at a high level, the charges accumulated in the photodiodes PD2, PD3, and PD4 Reset is performed via the capacitor CFD, and the reset level of the state is read out.

  Next, after setting the gate voltage φSEL to a low level, the gate voltage φTX1 is set to a high level, and as shown in “charge transfer” on the right side of FIG. The photogenerated charges are transferred under the gates of the transfer switches MTX2, MTX3, and MTX4 (capacitances CD11, CD12, CD21, CD22, CD31, CD32, CD41, and CD42).

  After charge transfer, before performing “signal level readout” (corresponding to “pixel 1 signal level readout” in FIG. 8) on the right side of FIG. 11, the gate voltage φTX1 is set to a low level as shown in FIG. . At this time, as shown in “intermediate states 1 and 2 in which φTX1 transits from a high level to a low level” on the right side of FIG. The impurity concentrations of the capacitors CD11, CD12, and CFD are set so that the potential decreases in the order of CDF. Thereby, it is possible to prevent the charges transferred to the capacitor CFD, the capacitors CD11, CD12, etc. in the “charge transfer” process on the right side of FIG. 11 from returning to the photodiode PD1. Therefore, when the gate voltage φTX1 becomes low level, as shown in “signal level reading” on the right side of FIG. 11, not only the capacitance CFD but also the capacitances CD21, CD22, CD31, CD32, CD41, It can also be transferred under CD42 and photodiodes PD2, PD3, PD4.

  In contrast, in “intermediate states 1 and 2 in which φTX1 transits from high level to low level” on the right side of FIG. 11, during the transition of gate voltage φTX1 from high level to low level, for example, the potential of the capacitor CD11 If the impurity concentration of each of the capacitors CD11 and CD12 is set so that is lower than the capacitor CD12, the charge transferred to the capacitor CD11 and the capacitor CD12 may return to the photodiode PD1. Can happen. Therefore, as described above, while the gate voltage φTX1 transitions from the high level to the low level, the impurity concentrations of the capacitors CD11, CD12, and CFD are set so that the potential always decreases in the order of the capacitors CD11, CD12, and CDF. This prevents the charge from returning to the photodiode PD1.

  The charge accumulation height shown in “Signal level reading” on the right side of FIG. 11 corresponds to the signal level (signal voltage) that becomes the gate input voltage of the amplification transistor MSF, and this height is the left of FIG. It is lower than the charge level shown in “Signal level reading” on the stage side. That is, it can be seen that the sensitivity of the pixel circuit 11 is lowered.

  2 and 3, since there are three photodiodes that can be used as capacitors, the present invention is not limited to the case where three capacitors PD2, PD3, and PD4 are used as shown in FIG. As shown in Fig. 10, it can be operated even when two capacitors PD2 and PD3 are used, or when one capacitor PD2 is used as shown in Fig. 10, depending on the luminance. By changing the number of photodiodes to be used, the pixel sensitivity can be changed more finely. In the present embodiment, the signal readout method of the pixel 1 has been described. The gate voltage φTX1 of the transfer switch MTX1 at the time of readout is set to one of the gate voltages φTX2, φTX3, and φTX4 of the transfer switches MTX2, MTX3, and MTX4. Needless to say, the signals can be read out from the pixels 2, 3, and 4 by switching.

  As described above, according to the imaging apparatus 100 of the present embodiment, the subject brightness has a predetermined threshold value such that the charge accumulation time of the photodiodes PD1, PD2, PD3, and PD4 is less than or equal to the blinking cycle of the light source of the lighting device. When it is above, the mode shifts to the high luminance mode in which the pixel circuit 11 is driven with a sensitivity lower than the normal sensitivity. In this high luminance mode, the gate voltage φTX1 of the pixel 1 to be read out of the plurality of pixels 1 to 4 is set to the high level, and the charge generated by the photodiode PD1 of the pixel 1 to be read is stored in the capacity. When transferring to CFD, etc., the potential is decreased in the order of the photodiode PD1 of the pixel 1 to be read, the capacitance CD11 of the pixel 1 to be read, the capacitance CD12 of the pixel to be read, and the capacitance CFD. . Thereby, the charge generated by the photodiode PD1 of the pixel 1 to be read can be transferred to the capacitor CFD and the capacitors CD11 and CD12 in the pixel 1 to be read.

  Further, after the above charge transfer processing, the gate voltages φTX2, φTX3, and φTX4 of the pixels 2 to 4 to be thinned out are kept at the high level, and the gate voltage φTX1 of the pixel 1 to be read out is set to the low level so that the capacitance When the potential of the CFD is read, the potential is always decreased in the order of the capacitances CD11, CD12, and CFD while the gate voltage φTX1 of the pixel 1 to be read changes from the high level to the low level. Thus, the charge transferred to the capacitor CFD or the like in the above charge transfer process can be prevented from returning to the photodiode PD1 of the pixel 1 to be read, and thus the photodiode PD1 of the pixel 1 to be read. The charge generated by the capacitor CFD is transferred to the capacitors CFD, the photodiodes PD2 to PD4, the capacitors CD11, CD21, CD31, CD41, and the capacitors CD12, CD22, CD32, CD42 without leakage, and then the potential of the capacitor CFD is set. Can be read.

  Further, as described above, the charge generated by the photodiode PD1 of the pixel 1 to be read is added to the capacitor CFD, and the photodiodes PD2 to PD4 of the pixels 2 to 4 to be thinned out, the capacitors CD11, CD21, and CD31. , CD41, and the capacitance CD12, CD22, CD32, and CD42, and reading the potential of the capacitance CFD means that in addition to the capacitance CFD, the photodiodes PD2-4 of the pixels 2 to 4 to be thinned out, these Capacitors that hold the charges generated by the photodiode PD1 of the pixel 1 to be read out of the capacitors CD11, CD21, CD31, and CD41 on the photodiodes PD2 to PD4 side and the capacitors CD12, CD22, CD32, and CD42 on the capacitor CFD side Lead to use as. Accordingly, in the high luminance mode, the potential of the capacitor CFD can be lowered to reduce the sensitivity of the pixel. In other words, it is possible to suppress the occurrence of flicker by changing the sensitivity of the pixel according to the subject brightness with an inexpensive and simple configuration without providing a special component.

  The present invention is not limited to the configuration of the above embodiment, and various modifications can be made. For example, in the above mobile phone, an example in which the amplification transistor MSF, the reset switch MRES, and the selection switch MSEL are shared between four adjacent pixels has been shown, but the amplification transistor MSF, the reset switch MRES, and the selection switch The number of pixels sharing the MSEL is not limited to four, and may be two or more.

1 is a block diagram showing a schematic configuration of an imaging apparatus according to an embodiment of the present invention. 2 is a diagram showing a configuration of a pixel circuit applied to the imaging apparatus. FIG. The top view of the semiconductor which comprises the pixels 1, 2, 3, 4 and capacity | capacitance CFD of the pixel circuit. FIG. 4 is a cross-sectional view taken along line A-A ′ in FIG. 3. The figure which shows the potential distribution in the A-A 'line cross section of FIG. 3 when gate voltage (phi) TX1 and (phi) TX2 are both low level. 6 is a timing chart showing the operation of the pixel circuit in the all-pixel readout mode. 6 is a timing chart showing the operation of the pixel circuit in a normal luminance mode. 6 is a timing chart showing the operation of the pixel circuit when the pixel 1 is read and the remaining pixels 2 to 4 are used as capacitors in the high luminance mode. 4 is a timing chart showing the operation of the pixel circuit when the pixel 1 is read and the pixels 2 to 3 are used as capacitors in the high luminance mode. 9 is a timing chart showing the operation of the pixel circuit when the pixel 1 is read and the pixel 2 is used as a capacitor in the high luminance mode. The figure which shows the change of the potential distribution of the A-A 'line cross section of FIG. 3 in the normal luminance mode and the high luminance mode. FIG. 6 is a diagram illustrating a configuration of a pixel circuit applied to a conventional imaging device. 6 is a timing chart showing the operation of the pixel circuit.

Explanation of symbols

1 pixel 2 pixel 3 pixel 4 pixel 11 pixel circuit 20 signal processing unit (luminance determination means)
100 Imaging device
PD1, PD2, PD3, PD4 Photodiode (photoelectric converter)
MTX1, MTX2, MTX3, MTX4 transfer switch (transfer means)
CFD capacity (capacity means)
MSF amplification transistor (signal amplification means)
MRES reset switch (reset means)
MSEL selection switch (pixel selection means)
TX1, TX2, TX3, TX4 gate
CD12, CD22, CD32, CD42 capacity (capacity means side part)
CD11, CD21, CD31, CD41 capacity (photoelectric conversion side)

Claims (3)

A plurality of pixels made of a semiconductor having a photoelectric conversion unit and a transfer unit that transfers charges output from the photoelectric conversion unit, a capacitor unit that holds charges transferred from the transfer unit, and a capacitor unit A pixel having signal amplifying means for amplifying and outputting a signal corresponding to the charge, reset means for resetting the charge held in the capacitor means, and pixel selecting means for selecting a pixel from which a signal is to be read. With a circuit,
In an imaging apparatus having an all-pixel readout mode for sequentially reading out signals based on charges output from all pixels and a pixel-thinning-out readout mode for reading out signals based on charges output from appropriately thinned pixels,
Between the adjacent pixels, the signal amplification means, the reset means, and the pixel selection means are shared,
Brightness determination means for determining whether the subject brightness is equal to or greater than a predetermined threshold value such that the charge accumulation time of the photoelectric conversion unit is equal to or less than the blinking cycle of the light source of the illumination device;
Each of the transfer means in each pixel has a gate,
On the capacitor means side (hereinafter referred to as a capacitor means side portion) in the semiconductor portion under the gate, a dopant having the same polarity as that forming the capacitor means is doped thinner than the capacitor means,
On the photoelectric conversion part side (hereinafter referred to as the photoelectric conversion side part) in the semiconductor part under the gate, a dopant is not doped, or a dopant having the same polarity as that of the capacity means side part is present from the capacity means side part. Thinly doped or doped with a dopant having a polarity opposite to that of the capacitor means side portion,
The pixel thinning readout mode includes a normal luminance mode in which the pixel circuit is driven with normal sensitivity when the luminance determining unit determines that the subject luminance is less than the threshold, and the subject luminance is equal to or higher than the threshold. A high brightness mode for driving the pixel circuit with a lower sensitivity than the normal sensitivity when determined,
The pixel to be thinned out in the pixel thinning readout mode and the pixel to be read are in the relationship between the adjacent pixels sharing the signal amplification unit, the reset unit, and the pixel selection unit,
When in the high brightness mode,
When the voltage of the gate of the pixel to be read out of the plurality of pixels is set to a high level and the charge generated by the photoelectric conversion unit of the pixel to be read out is transferred to the capacitor means or the like, the potential is increased. Is in the order of the photoelectric conversion unit of the pixel to be read, the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, the capacitance means,
When the voltage of the gate of the pixel to be read is set to a low level while the gate voltage of the pixel to be thinned is kept at a high level, the potential of the capacitor means is read out While the voltage of the gate of the pixel transits from a high level to a low level, the potential is always the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, Lower in order,
In addition to the capacitance means, the thinned-out pixel photoelectric conversion unit, photoelectric conversion side portion, and capacitance means side portion are used as a capacity for holding charges generated by the photoelectric conversion unit of the pixel to be read out. By reducing the potential of the capacitive means, the sensitivity of the pixel is lowered,
An imaging apparatus characterized by being able to suppress the occurrence of flicker with a simple configuration. A plurality of pixels made of a semiconductor having a photoelectric conversion unit and a transfer unit that transfers charges output from the photoelectric conversion unit, a capacitor unit that holds charges transferred from the transfer unit, and a capacitor unit A pixel having signal amplifying means for amplifying and outputting a signal corresponding to the charge, reset means for resetting the charge held in the capacitor means, and pixel selecting means for selecting a pixel from which a signal is to be read. With a circuit,
In an imaging apparatus having an all-pixel readout mode for sequentially reading out signals based on charges output from all pixels and a pixel-thinning-out readout mode for reading out signals based on charges output from appropriately thinned pixels,
Between the adjacent pixels, the signal amplification means, the reset means, and the pixel selection means are shared,
Each of the transfer means in each pixel has a gate,
On the capacitor means side (hereinafter referred to as a capacitor means side portion) in the semiconductor portion under the gate, a dopant having the same polarity as that forming the capacitor means is doped thinner than the capacitor means,
On the photoelectric conversion part side (hereinafter referred to as the photoelectric conversion side part) in the semiconductor part under the gate, a dopant is not doped, or a dopant having the same polarity as that of the capacity means side part is present from the capacity means side part. Thinly doped or doped with a dopant having a polarity opposite to that of the capacitor means side portion,
The pixel to be thinned out in the pixel thinning readout mode and the pixel to be read are in the relationship between the adjacent pixels sharing the signal amplification unit, the reset unit, and the pixel selection unit,
In the pixel thinning readout mode,
When transferring the charge generated by the photoelectric conversion unit of the pixel to be read out of the plurality of pixels to the capacitor unit or the like, the potential is the photoelectric conversion unit of the pixel to be read out, the read target and The lower the photoelectric conversion side part of the pixel, the lower part of the capacity means side of the pixel to be read, the lower the order of the capacity means,
When the potential of the capacitor means is read, while the gate voltage of the pixel to be read transitions from a high level to a low level, the potential is always the photoelectric conversion side portion of the pixel to be read, The capacity means side portion of the pixel to be read out becomes lower in the order of the capacity means,
In addition to the capacitance means, the thinned-out pixel photoelectric conversion unit, photoelectric conversion side portion, and capacitance means side portion are used as a capacity for holding charges generated by the photoelectric conversion unit of the pixel to be read out. By reducing the potential of the capacitive means, the sensitivity of the pixel is lowered,
An imaging apparatus characterized by being able to suppress the occurrence of flicker with a simple configuration. The pixel decimation readout mode drives the pixel circuit with normal sensitivity when the subject brightness is less than a predetermined threshold such that the charge accumulation time of the photoelectric conversion unit is less than or equal to the blinking cycle of the light source of the lighting device. A normal luminance mode, and when the subject luminance is equal to or higher than the threshold, a high luminance mode for driving the pixel circuit with a sensitivity lower than the normal sensitivity,
When in the high brightness mode,
The voltage of the gate of the pixel to be read out of the plurality of pixels is set to a high level, and the electric charge generated by the photoelectric conversion unit of the pixel to be read out is photoelectrically converted by the capacitor means and the pixels to be thinned out When transferring to the unit, the potential is in the order of the photoelectric conversion unit of the pixel to be read, the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, and the capacitance means. Lower,
When the voltage of the gate of the pixel to be read is set to a low level while the gate voltage of the pixel to be thinned is kept at a high level, the potential of the capacitor means is read out While the voltage of the gate of the pixel transits from a high level to a low level, the potential is always the photoelectric conversion side portion of the pixel to be read, the capacitance means side portion of the pixel to be read, The imaging apparatus according to claim 2, which decreases in order.

Images