CN117412190A

CN117412190A - Image sensor and electronic device including the same

Info

Publication number: CN117412190A
Application number: CN202310873036.XA
Authority: CN
Inventors: 朴奭容; 金敬珉; 金东炫
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-07-15
Filing date: 2023-07-14
Publication date: 2024-01-16

Abstract

An image sensor, comprising: a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first and second pixels including a first Photodiode (PD) and a second PD sharing a driving transistor, the first and second pixels configured to operate in a first mode and a second mode according to a conversion gain based on the first PD, and configured to operate in a third mode and a fourth mode based on the second PD; and an analog-to-digital converter including a first Correlated Double Sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit, which reads pixel signals output through the first column line and the second column line. The first CDS circuit is connected to the first column line and the second column line in a time division manner.

Description

Image sensor and electronic device including the same

Cross Reference to Related Applications

The present application is based on korean patent application No. 10-2022-0087798 filed on 7/15/2022 and korean patent application No. 10-2023-0020816 filed on 16/2023, and claims priority from the above-mentioned korean patent applications, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

Various example embodiments relate to image sensors, and more particularly, to image sensors that provide images with an extended dynamic range and high quality, and/or electronic devices including the same.

Background

The image sensor is or includes: a device for capturing two-dimensional and/or three-dimensional images of an object. The image sensor generates an image of an object using a photoelectric conversion element that reacts according to the intensity of light reflected from the object. With the development of Complementary Metal Oxide Semiconductor (CMOS) technology, CMOS image sensors using CMOS are widely used. Recently, as image sensors are installed in various devices, there is a need or desire for image sensors having improved characteristics of High Dynamic Range (HDR) and/or signal-to-noise ratio (SNR) at low and high illuminance.

Disclosure of Invention

Various example embodiments provide an image sensor including a pixel including a plurality of photoelectric conversion elements sharing a driving transistor and supporting a dual conversion gain mode and generating image data having a high dynamic range and an improved signal-to-noise ratio, and an electronic device including the image sensor.

According to some example embodiments, there is provided an image sensor comprising: a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first and second pixels including a first Photodiode (PD) and a second PD sharing a driving transistor, the first and second pixels configured to operate in a first mode and a second mode according to a conversion gain based on the respective first PD, and the first and second pixels configured to operate in a third mode and a fourth mode based on the respective second PD; and an analog-to-digital converter including a first Correlated Double Sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals output through the first and second column lines. The first CDS circuit is configured to be connected to the first column line and the second column line in a time division manner.

Alternatively or additionally, according to some example embodiments, there is provided an image sensor comprising: a pixel array including a plurality of pixels, a plurality of row lines configured to provide control signals to the plurality of pixels, and a plurality of column lines configured to output a plurality of pixel signals generated from the plurality of pixels, each of the plurality of pixels including a first Photodiode (PD) and a second PD sharing a driving transistor; an analog-to-digital converter configured to convert a plurality of pixel signals output through column lines, the analog-to-digital converter including a first Correlated Double Sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received through a first column line and a second column line among the plurality of column lines; and a switching circuit configured to connect the first column line to the first CDS circuit and the second column line to the third CDS circuit in a time division manner in the first period, and to connect the second column line to the first CDS circuit and the second CDS circuit and the first column line to the third CDS circuit in a time division manner in the second period.

Alternatively or additionally, according to some example embodiments, there is provided an electronic device comprising: a pixel array including a plurality of pixels, a plurality of row lines configured to provide control signals to the plurality of pixels, and a plurality of column lines configured to output a plurality of pixel signals generated from the plurality of pixels, each of the plurality of pixels including a first Photodiode (PD) and a second PD sharing a driving transistor; an analog-to-digital converter configured to convert a plurality of pixel signals output through column lines, the analog-to-digital converter including a first Correlated Double Sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received through a first column line and a second column line among the plurality of column lines; and a switching circuit configured to connect the first column line to the first CDS circuit and the second column line to the third CDS circuit in a time division manner in the first period, and to connect the second column line to the first CDS circuit and the second CDS circuit and the first column line to the third CDS circuit in a time division manner in the second period.

Drawings

Various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of an image sensor according to various example embodiments;

fig. 2A and 2B are circuit diagrams illustrating pixel structures according to various example embodiments;

fig. 3A and 3B are diagrams illustrating separated photodiode structures of pixels according to various example embodiments;

fig. 4A and 4B are circuit diagrams of Correlated Double Sampling (CDS) circuits included in an image sensor according to various example embodiments;

fig. 5A and 5B schematically illustrate connections between pixels and CDS circuits in an image sensor according to various example embodiments;

fig. 6 is a timing chart showing the operation of the pixel and CDS circuit in fig. 5A and 5B;

fig. 7 is a timing chart showing a pixel signal readout scheme in a High Conversion Gain (HCG) mode and a Low Conversion Gain (LCG) mode of a pixel in an image sensor of a comparative example of the image sensor according to various exemplary embodiments;

fig. 8 shows signal-to-noise ratio (SNR) characteristics for a readout method of an image sensor according to various exemplary embodiments and for each illuminance of the readout method according to a comparative example;

fig. 9A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 9B is a timing chart illustrating readout of the pixel of fig. 9A;

Fig. 10A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 10B is a timing chart illustrating readout of the pixel of fig. 10A;

fig. 11A and 11B illustrate connections between pixels and CDS circuits in an image sensor according to various example embodiments, and fig. 11C is a timing chart illustrating readout of the pixels of fig. 11A and 11B;

fig. 12A and 12B illustrate connections between pixels and CDS circuits in an image sensor according to various exemplary embodiments, and fig. 12C is a timing chart illustrating readout of the pixels of fig. 12A and 12B;

fig. 13A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 13B is a timing chart illustrating readout of the pixel of fig. 13A;

fig. 14A and 14B illustrate a stacked structure of an image sensor according to various exemplary embodiments; and

fig. 15 is a block diagram schematically illustrating an electronic device including an image sensor according to various example embodiments.

Detailed Description

Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of an image sensor 100 according to various example embodiments.

The image sensor 100 may be mounted on an electronic device having image and/or light sensing capabilities. For example, the image sensor 100 may be mounted on an electronic device such as one or more of a camera, a smart phone, a wearable device, an internet of things (IoT) device, a home appliance, a tablet Personal Computer (PC), a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a navigation system, an unmanned aerial vehicle, and an Advanced Driver Assistance System (ADAS). In addition, the image sensor 100 may be mounted on an electronic device provided as a component in one or more of a vehicle, furniture, manufacturing facility, door, various measurement devices, and the like.

Referring to fig. 1, the image sensor 100 may include a pixel array 110, a row driver 120, an analog-to-digital conversion circuit 130 (hereinafter, referred to as an ADC circuit), a ramp signal generator 140, a timing controller 150, and an image signal processor 160. The row driver 120, the ADC circuit 130, the ramp signal generator 140, and the timing controller 150 may be referred to as a readout circuit.

The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in rows and columns. The plurality of pixels PX may be Active Pixel Sensors (APS). The number of the plurality of row lines RL may be equal to, greater than, or less than the number of the plurality of column lines CL.

In various example embodiments, the pixels PX arranged in the same column may be connected to a plurality of column lines CL. For example, the pixels PX arranged in the same column may be alternately connected to two column lines, e.g., the first column line CL1 and the second column line CL2. However, the example embodiment is not limited thereto, and the pixels PX arranged in the same column may be connected to the same column line CL.

Each of the plurality of pixels PX may sense light by using a photoelectric conversion element, and output an image signal, which is an electrical signal according to the sensed light. The photoelectric conversion element may be or include a photosensitive element including an organic or inorganic material, such as one or more of a photodiode (inorganic photodiode), an organic photosensitive film, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode. Hereinafter, a photodiode will be described as an example of a photoelectric conversion element; however, the example embodiments are not limited thereto.

A microlens for condensing light may be disposed above each of the plurality of pixels PX or above each of the pixel groups composed of the adjacent pixels PX. A color filter for transmitting light in a specific spectral region may be disposed above each of the plurality of pixels PX, and each of the plurality of pixels PX may sense light in the specific spectral region from light received through the microlens based on the corresponding color filter. For example, the pixel array 110 may include red pixels for converting light in a red spectral region into an electrical signal, green pixels for converting light in a green spectral region into an electrical signal, and blue pixels for converting light in a blue spectral region into an electrical signal. However, the example embodiment is not limited thereto, and the pixel array 110 may further include white pixels, or the pixel array 110 may include pixels according to other color combinations, such as cyan pixels, yellow pixels, green pixels, and magenta pixels. The pixels PX may be arranged in a bayer pattern; however, the example embodiments are not limited thereto.

In the pixel array 110 according to various exemplary embodiments, the pixels PX may have the following pixel structures: in which several photodiodes (e.g., a first photodiode and a second photodiode) share some circuit elements of the pixel PX, such as the reset transistor RX in fig. 2A, the driving transistor DX in fig. 2A, and the selection transistor SX in fig. 2A. The light receiving regions of the photodiodes may be different from each other; for example, the light receiving area of the first photodiode may be larger than the light receiving area of the second photodiode. The first photodiode may be referred to as the large photodiode LPD in fig. 2A, and the second photodiode may be referred to as the small photodiode SPD in fig. 2A. Alternatively or additionally, the pixel PX may include a high-capacity capacitor C _LOF (see fig. 2A) for storing charge spilled from the second photodiode (i.e. the small photodiode SPD).

Because the large photodiode LPD has a relatively large light receiving area, the large photodiode LPD may generate more charge (e.g., more electron-hole pairs) than the small photodiode SPD under the same light receiving conditions. For example, a large photodiode LPD may have higher sensitivity than a small photodiode SPD. Because of this characteristic, in the case of low illuminance, an image signal can be generated using a pixel signal based on the charge generated by the large photodiode LPD; while in the case of high illuminance, an image signal may be generated using a pixel signal based on the charge generated by the small photodiode SPD. Hereinafter, for convenience of description, it is assumed that the pixel PX includes a large photodiode LPD and a small photodiode SPD; however, the example embodiments are not limited thereto. The pixel PX may include a plurality of photodiodes having the same light receiving area or different light receiving areas.

The pixels PX may sequentially operate according to a plurality of modes (operation modes). In various example embodiments, the pixel PX may operate in the first mode and the second mode based on the first photodiode, and may operate in the third mode and the fourth mode based on the second photodiode. The first mode and the second mode are distinguished from each other according to a conversion gain, wherein the conversion gain represents a ratio at which charges generated by a photodiode (e.g., a first photodiode) are converted into an electrical signal (e.g., into a pixel voltage). The conversion gain may vary according to the capacitance of a parasitic capacitor connected to the floating diffusion node (hereinafter, simply referred to as the capacitance of the floating diffusion node). For example, the pixel PX supports a dual conversion gain mode, and the first mode may be a low conversion gain mode based on the first photodiode, and the second mode may be a high conversion gain mode based on the first photodiode. The third mode and the fourth mode may be distinguished from each other based on whether a signal according to overflowing electric charge of the second photodiode stored in the high-capacity capacitor provided in the pixel PX is read (or read). The structure and mode of the pixel PX will be described in detail below with reference to fig. 2A to 3B and fig. 5A to 6.

The pixel signals of the first to fourth modes read out according to the first to fourth modes may correspond to different illuminance ranges. For example, the second mode pixel signal according to the second mode may correspond to a first illuminance section which is a lowest illuminance section, the first mode pixel signal according to the first mode may correspond to a second illuminance section higher than the first illuminance section, and the third mode pixel signal according to the third mode and the fourth mode pixel signal according to the fourth mode may correspond to a third illuminance section and a fourth illuminance section higher than the second illuminance section, respectively. The fourth illumination section may be a maximum illumination section. The first to fourth mode pixel signals may be generated within one frame period scanned after the pixel array 110 is exposed once.

At least four digital signals, such as first to fourth mode digital signals generated based on first to fourth mode pixel signals output from each of a plurality of pixels of the pixel array 110, respectively, may be combined into one image, and the combined image may have a high dynamic range.

In some example embodiments, each of the plurality of pixels PX may operate in a single exposure method in which one exposure is performed or in a multiple exposure method in which multiple exposures are performed. For example, the pixel PX may operate in a single exposure method to generate a pixel signal through the first photodiode and/or the second photodiode after one exposure operation. Alternatively or additionally, the pixel PX may operate in a multiple exposure method, wherein the pixel signal is generated by the first photodiode and/or the second photodiode in response to the first exposure operation, and then the pixel signal is additionally generated by the first photodiode and/or the second photodiode in response to the second exposure operation.

The row driver 120 drives the pixel array 110 in units of one or more rows. The row driver 120 may decode a row control signal (e.g., a row address) received from the timing controller 150, and may select at least one pixel row from among a plurality of pixel rows of the pixel array 110 to read out in response to the decoded row control signal.

The row driver 120 may supply control signals, such as one or more of a selection signal, a transfer control signal, a switching control signal, and a switching control signal, to the selected two or more pixel rows through the row line RL. The pixels PX included in the pixel row selected by the selection signal supplied from the row driver 120 output a pixel signal, for example, a pixel voltage. The pixels PX may sequentially operate according to the first mode to the fourth mode. The pixel PX may operate according to the first mode and the second mode, and then operate according to the third mode and the fourth mode. The pixels PX may output first to fourth mode pixel signals corresponding to the first to fourth modes, respectively. The row driver 120 may generate control signals for controlling the pixels PX to operate in the first to fourth modes, and supply the generated control signals to the pixel array 110.

In various example embodiments, the row driver 120 may simultaneously select one or more rows for quick readout of the pixel array 110. Two or more pixels included in two or more selected rows and arranged in the same column may be connected to different column lines CL. The readout periods of two or more pixels connected to different column lines CL may at least partially overlap each other. For example, when the pixels PX included in one row are operated in the first mode and the second mode, the pixels PX included in the other row may be operated in the third mode and the fourth mode. Accordingly, the rows of the pixel array 110 may be read out in an interleaved manner, as described below with reference to fig. 11C, 12B, and 13B.

The RAMP signal generator 140 may generate a RAMP signal RAMP that increases or decreases with a particular slope (e.g., a dynamically determined or predetermined slope), and may provide the RAMP signal RAMP to each of the plurality of ADCs 135 of the ADC circuit 130. In various example embodiments, the ramp signal generator 140 may generate a first ramp signal and a second ramp signal, may provide the first ramp signal to the first Correlated Double Sampling (CDS) circuit 131 and the second CDS circuit 132 of the ADC 135, and may provide the second ramp signal to the third CDS circuit 133 of the ADC 135. In various example embodiments, the ramp signal generator 140 may generate the first, second, and third ramp signals and provide the first to third ramp signals to the first to third CDS circuits 131 to 133.

The ADC circuit 130 may convert a pixel signal (e.g., a pixel voltage such as an analog pixel value) output from the pixel array 110 into a pixel value that is a digital signal. The ADC circuit 130 may include a plurality of ADCs 135 and a switching circuit (SWC), and each of the plurality of ADCs 135 may convert a pixel signal into a pixel value by using a CDS method. The pixel signal received through each of the plurality of column lines CL may be converted into a pixel value by a corresponding ADC among the plurality of ADCs 135.

Each of the ADCs 135 may include CDS circuits, such as a second CDS circuit (e.g., CDS 2) 132 and/or a third CDS circuit (e.g., CDS 3) 133, and a counter 134. In addition, two adjacent ADCs 135 corresponding to two adjacent column lines CL (e.g., a first column line CL1 and a second column line CL 2) may share a first CDS circuit (i.e., CDS 1) 131. In other words, two adjacent column lines CL may share the first CDS circuit 131.

In various example embodiments, two adjacent ADCs 135 corresponding to two adjacent column lines CL may share the first to third CDS circuits (i.e., CDS1, CDS2, and CDS 3) 131, 132, and 133.

The switching circuit SWC may include a plurality of switches, and may provide each of the outputs of the column lines CL to the corresponding ADC 135. In this case, the switching circuit SWC may provide each of the outputs of the two adjacent column lines CL to the first CDS circuit 131 in a time-division manner, and/or may provide each of the outputs of the two adjacent column lines CL to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner. For example, the switching circuit SWC may supply the output of the first column line CL1 and the output of the second column line CL2 to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time division manner. This will be described in detail below with reference to fig. 5A to 6.

In this way, according to the operation of the switching circuit SWC, each of the two adjacent column lines CL may be connected to the first CDS circuit 131 shared by the two adjacent ADCs 135 in a time-division manner, and/or may be connected to the first, second, and third CDS circuits 131, 132, and 133 shared by the two adjacent ADCs 135 in a time-division manner.

The CDS circuit (for example, each of the first to third CDS circuits 131, 132, and 133) may compare the pixel signal received through the column line CL with the RAMP signal RAMP and output the comparison result. When the voltage level of the RAMP signal RAMP and the voltage level of the pixel signal are the same, the CDS circuit may output a comparison result signal transiting from a first level (e.g., logic high) to a second level (e.g., logic low). The time point of the level transition of the comparison result signal may be determined according to the voltage level of the pixel signal.

The CDS circuit may sample and hold a pixel signal supplied from the pixel PX according to a CDS method, and may double sample a specific noise level (e.g., a reset level and/or a signal level). The CDS circuit may generate a comparison result signal corresponding to the reset level and a comparison result signal corresponding to the signal level. In this case, a method of reading out a signal level after reading out a reset level may be referred to as a full CDS method, and a method of reading out a reset level after reading out a signal level may be referred to as an incomplete CDS method and/or a variable (delta) reset sampling (DRS) method.

In order to read out the first mode pixel signal and the second mode pixel signal from one pixel PX by the full CDS method, two CDS circuits corresponding to the first mode and the second mode (e.g., a low conversion gain mode and a high conversion gain mode based on the first photodiode), respectively, are required or used; and, among the two CDS circuits, the CDS circuit corresponding to the second mode may correspond to the third mode and the fourth mode. Alternatively, one or more CDS circuits corresponding to the third mode and the fourth mode may be required or used separately from the two CDS circuits.

As described above, when the first mode pixel signal and the second mode pixel signal are output through one of the two adjacent column lines CL according to the staggered readout, the third mode pixel signal and the fourth mode pixel signal may be output through the other column line CL. Accordingly, the first CDS circuit 131 corresponding to the first mode may be shared by two adjacent ADCs 135. Alternatively, the first CDS circuit 131 and the second CDS circuit 132 corresponding to the first mode and the second mode, respectively, and the third CDS circuit 133 corresponding to the third mode and the fourth mode may be shared by two adjacent ADCs 135.

The counter (e.g., counter CNT) 134 may count time points of level transitions of the comparison result signals respectively output from the first to third CDS circuits 131, 132, and 133. Accordingly, a reset value and/or a signal value may be obtained for each of the first to fourth modes, and a value obtained by subtracting the reset value from the signal value may be generated as a pixel value.

The control signals supplied to the ADC circuit 130, for example, the switching signal supplied to the switching circuit SWC and the auto-zero signal supplied to the first to third CDS circuits 131, 132 and 133, may be supplied from the timing controller 150 or may be supplied from the row driver 120 under the control of the timing controller 150.

The timing controller 150 may output a timing control signal to each of the row driver 120, the ADC circuit 130, and the ramp signal generator 150, and may control operations and operation timings of the row driver 120, the ADC circuit 130, and the ramp signal generator 150.

The image signal processor 160 may perform various signal processes on the image data output from the ADC circuit 130, for example, first to fourth image data corresponding to the first to fourth mode pixel signals, respectively. For example, the image signal processor 160 may perform signal processing on the received image data, such as one or more of picture quality compensation, combining (binning), and downsizing. The picture quality compensation may include, for example, one or more of black level compensation, lens shading compensation, crosstalk compensation, and bad pixel correction.

The image data IDT output from the image signal processor 160 may be transmitted to an external processor. For example, the external processor may be a main processor of an electronic device on which the image sensor 100 is mounted. For example, the external processor may be or may include an application processor of the mobile terminal, or may be included in an application processor of the mobile terminal. The image sensor 100 may transmit image data to an external processor according to a data communication method based on a setup interface, such as a Mobile Industrial Processor Interface (MIPI). The external processor may generate a High Dynamic Range (HDR) image by merging (mege) the first image to the fourth image.

Fig. 2A and 2B are circuit diagrams illustrating pixel structures according to various example embodiments. The pixels PXa and PXb of fig. 2A and 2B may be applied as the pixels PX of the pixel array 110 of fig. 1.

Referring to fig. 2A, the pixel PXa may include a plurality of photodiodes, for example, a large photodiode LPD and a small photodiode SPD. The pixel PXa may include a plurality of transistors, for example, a first transfer transistor LTX, a second transfer transistor STX, a reset transistor RX, a driving transistor DX, a selection transistor SX, a gain control transistor DRX (also referred to as a conversion gain control transistor), a switching transistor SWT, and a capacitor C _LOF . Control signals STS, LTS, RS, SEL, GCS and SWS can be applied to the pixels PXa and control signals STS, LTS, RS, SEL, GCS and SWS can be provided from the row driver 120 in fig. 1.

The large photodiode LPD and the small photodiode SPD may generate a photo-charge (e.g., electron-hole pairs) that varies according to the light intensity. For example, the large photodiode LPD and the small photodiode SPD may generate charges, such as negative charges (or electrons) and positive charges (or holes), in proportion to the amount of incident light. Photo-charges generated by the large photodiode LPD and the small photodiode SPD may be transferred to and accumulated in at least one of the first to third floating diffusion nodes FD1, FD2, and FD 3. A parasitic capacitor (not shown) may be formed at each of the first to third floating diffusion nodes FD1, FD2, and FD 3. Alternatively or additionally, an actual capacitor element (not shown) may be connected to each of the first to third floating diffusion nodes FD1, FD2 and FD 3.

The first transfer transistor LTX may be connected between the large photodiode LPD and the first floating diffusion node FD1, and may be turned on or off in response to the first transfer control signal LTS. The first transfer transistor LTX may be turned on to transfer the photo-charges generated by the large photodiode LPD to the first floating diffusion node FD1.

The pixel PXa may include a conversion gain control transistor DRX. The conversion gain control transistor DRX may be connected to the first and second floating diffusion nodes FD1 and FD2. The conversion gain control transistor DRX may be turned on or off in response to the gain control signal GCS. The conversion gain control transistor DRX may be turned on to connect the first and second floating diffusion nodes FD1 and FD2 to each other. When the first and second floating diffusion nodes FD1 and FD2 are connected to each other (e.g., connected to each other in series), the capacitance of the first floating diffusion node FD1 may increase and the conversion gain may decrease. When the conversion gain control transistor DRX is turned on, the pixel PXa may operate in a low conversion gain mode (hereinafter, referred to as LCG mode). In contrast, when the conversion gain control transistor DRX is turned off, the pixel PXa may operate in a high conversion gain mode (hereinafter, referred to as HCG mode).

The second transfer transistor STX may be connected between the small photodiode SPD and the second floating diffusion node FD2. The second transfer transistor STX may be turned on or off in response to the second transfer control signal STS and may be turned on to transfer the photo-charges generated by the small photodiode SPD to the third floating diffusion node FD3.

Capacitor C _LOF May be connected to the third floating diffusion node FD3, and a reset voltage VRD may be applied to the capacitor C _LOF Is provided for the second terminal of (c). In various example embodiments, the reset voltage VRD may be equal to the pixel supply voltage VPIX. Capacitor C _LOF May be greater than the capacitance of parasitic capacitors generated at the first and second floating diffusion nodes FD1 and FD2, respectively. For example, capacitor C _LOF May be a high capacity capacitor. Charge overflowing from the small photodiode SPD may be accumulated in the capacitor C through the third floating diffusion node FD3 _LOF Is a kind of medium.

The switching transistor SWT may be connected to the second and third floating diffusion nodes FD2 and FD3. The switching transistor SWT may be turned on or off in response to the switching control signal SWS. When the switching transistor SWT is turned on, the second and third floating diffusion nodes FD2 and FD3 may be connected to each other, and the capacitor C _LOF May be connected in parallel with a parasitic capacitor formed at the second floating diffusion node FD 2. Accordingly, the capacitance of the second floating diffusion node FD2 may increase.

A first terminal of the reset transistor RX may be connected to the second floating diffusion node FD2, and a reset voltage VRD may be applied to a second terminal of the reset transistor RX. The reset transistor RX may be turned on and off in response to a reset control signal RS. When the reset transistor RX is turned on, the conversion gain control transistor DRX may be turned on. When the reset voltage VRD is applied to the first and second floating diffusion nodes FD1 and FD2, the first and second floating diffusion nodes FD1 and FD2 may be reset. For example, the charge accumulated in the parasitic capacitors of the first and second floating diffusion nodes FD1 and FD2 may be completely or at least partially removed. When the reset transistor RX is turned on, the conversion gain control transistor DRX and the switching transistor SWT may be turned on. When the reset voltage VRD is applied to the first to third floating diffusion nodes FD1, FD2 and FD3, the first to third floating diffusion nodes FD1, FD2 and FD3 may be reset.

A first terminal of the driving transistor DX may be connected to the selection transistor SX, and the pixel power supply voltage VPIX may be applied to a second terminal of the driving transistor DX. A first terminal of the selection transistor DX may be connected to the driving transistor DX, and a second terminal of the selection transistor DX may be connected to the column line CL. The selection transistor SX may be turned on or off in response to a selection signal SEL. When the selection transistor SX is turned on in the readout operation, the driving transistor DX may operate as a source follower based on the bias current IL generated by the current source CS connected to the column line CL; and the driving transistor DX may output a voltage corresponding to the charge accumulated in the first floating diffusion node FD1 as a pixel signal.

According to various example embodiments, the conversion gain control transistor DRX may be turned on or off during a readout period of the large photodiode LPD, and thus, the pixel PX may operate in the first mode or the second mode. When the conversion gain control transistor DRX is turned on, the first floating diffusion node FD1 may be connected to the second floating diffusion node FD2, and the pixel PX may operate in the LCG mode. When the conversion gain control transistor DRX is turned off, the first floating diffusion node FD1 may be electrically disconnected from the second floating diffusion node FD2, and thus, the pixel PX may operate in the HCG mode.

During the readout period of the small photodiode SPD, the conversion gain control transistor DRX and the switching transistor SWT may be turned on. The small photodiode SPD may be read out twice during the read out period of the small photodiode SPD.

In this case, based on the energy of the capacitor C _LOF Whether or not the signal of the overflowing electric charge accumulated in the pixel P is read outX may operate in a third mode or a fourth mode. When the reset level is read after resetting the first to third floating diffusion nodes FD1, FD2 and FD3 after reading the signal level, the data can be read according to the data stored in the capacitor C _LOF A signal of overflowing electric charge accumulated in the capacitor. Accordingly, in the readout period of the small photodiode SPD, when the signal level is read out after the readout of the reset level, the pixel PX may operate in the third mode, and when the reset level is read out after the readout of the signal level, the pixel PX may operate in the fourth mode. The third mode may be referred to as CDS mode and the fourth mode may be referred to as lateral overflow integrating capacitor (LOFIC) mode.

Referring now to fig. 2B, the pixel PXb may include a plurality of photodiodes, such as a large photodiode LPD and a small photodiode SPD. The pixel PXb may include a plurality of transistors, for example, a first transfer transistor LTX, a second transfer transistor STX, a reset transistor RX, a driving transistor DX, a selection transistor SX, a gain control transistor DRX (also referred to as a conversion gain control transistor), a switching transistor SWT, and a capacitor C _LOF . Control signals STS, LTS, RS, SEL, GCS and SWS can be applied to the pixels PXb and control signals STS, LTS, RS, SEL, GCS and SWS can be provided from the row driver 120 in fig. 1.

The structure and/or operation of the pixel PXb of fig. 2B may be similar to the structure and/or operation of the pixel PXa of fig. 2A. However, in the pixel PXb of fig. 2B, the second transfer transistor STX may be connected between the small photodiode SPD and the second floating diffusion node FD 2. During the readout period of the small photodiode SPD, the switching transistor SWT may be turned on or off, and when the switching transistor SWT is turned on, the data on the capacitor C may be read out _LOF A signal of overflowing electric charge accumulated in the capacitor. Accordingly, when the switching transistor SWT is turned on, the pixel PXb may operate in the fourth mode, and when the switching transistor SWT is turned off, the pixel PXb may operate in the third mode.

Each of the transistors shown in fig. 2A, for example, a first transfer transistor LTX, a second transfer transistor STX, a reset transistor RX, a driving transistor DX, a selection transistorThe transistor SX, the gain control transistor DRX and the switching transistor SWT may have the same or different electrical and/or physical properties as the corresponding transistors included in fig. 2B. Furthermore, each of the photodiodes shown in fig. 2A, e.g., the large photodiode LPD and the small photodiode SPD, may have the same or different electrical and/or physical properties as the corresponding photodiode included in fig. 2B. Further, a capacitor C included in fig. 2A _LOF May have a capacitor C as included in fig. 2B _LOF The same or different electrical and/or physical properties. The example embodiments are not limited thereto.

Fig. 3A and 3B are diagrams illustrating separated photodiode structures of pixels according to various example embodiments.

Referring to fig. 3A, the pixel array 110a may include a plurality of pixels PX arranged in rows and columns in an X-Y plan view. Each of the plurality of pixels PX may include a photoelectric conversion portion and a pixel circuit portion. The photoelectric conversion portion and the pixel circuit portion may vertically overlap.

The photoelectric conversion portion may include a microlens, a color filter, and a photodiode. In some example embodiments, the photoelectric conversion portion may further include a color filter, an overcoat layer, and an insulating structure. The microlens may be disposed above the photodiode, and may be configured to collect light incident from the outside and make the light incident to the photoelectric conversion element or focus the light to be incident to the photoelectric conversion element.

The pixel PX may include a large photodiode LPD and a small photodiode SPD. The region forming the large photodiode LPD and the region forming the small photodiode SPD may be separated from each other by an isolation region such as a Deep Trench Isolation (DTI) structure. The large photodiode LPD of each pixel PX may have a relatively large light receiving area, and the small photodiode SPD of each pixel PX may have a relatively small light receiving area. One or both of the large photodiode LPD and the small photodiode SPD may be polygonal in shape; however, the example embodiments are not limited thereto. As shown in fig. 3A, the large photodiode LPD and the small photodiode SPD may each have a quadrangular shape, such as a square shape. As shown in fig. 3B, the large photodiode LPD may have an octagonal shape such as a regular octagonal shape, and the small photodiode SPD may have a quadrangular shape such as a square shape. However, the example embodiments are not limited thereto, and the shapes of the large photodiode LPD and the small photodiode SPD may be variously modified.

A microlens that collects light incident from the outside may be disposed over each of the large photodiode LPD and the small photodiode SPD, and a color filter, a protective layer, and an insulating structure may be disposed between the microlens and the large photodiode LPD and the small photodiode SPD.

The pixel circuit portion may be formed under the large photodiode LPD and the small photodiode SPD, and may include a floating diffusion node, source/drain and gate of a transistor, a load resistor, a via contact, and a wiring structure.

Fig. 4A and 4B are circuit diagrams of CDS circuits included in an image sensor according to various example embodiments.

The CDS circuits CDSCa and CDSCb of fig. 4A and 4B may be applied to the first to third CDS circuits 131, 132, and 133 of fig. 1.

Referring to fig. 4a, the cds circuit CDSCa may include a comparator 11, first and second auto-zero switches SAZ1 and SAZ2, and first and second capacitors C1 and C2.

The comparator 11 may be implemented as a differential amplifier, for example an Operational Transconductance Amplifier (OTA). The first auto-zero switch SAZ1 may be connected to the first input terminal INP and the second output terminal ON of the comparator 11, and the second auto-zero switch SAZ2 may be connected to the second input terminal INN and the first output terminal OP of the comparator 11. The first and second auto-zero switches SAZ1 and SAZ2 may be turned on and off in response to the auto-zero signal AZ. In various example embodiments, the first auto-zero switch SAZ1 and the second auto-zero switch SAZ2 may be implemented as transistors.

The RAMP signal RAMP may be applied to one end of the first capacitor C1, and the other end of the first capacitor C1 may be connected to the first input terminal INP of the comparator 11. The pixel signal VPS may be applied to one end of the second capacitor C2, and the other end of the second capacitor C2 may be connected to the second input terminal INN of the comparator 11. For example, the RAMP signal RAMP and the pixel signal VPS may be supplied to the first and second input terminals INP and INN of the comparator 11 through the first and second capacitors C1 and C2, respectively. In this case, the first capacitor C1 and the second capacitor C2 are coupling capacitors, and may block DC components of the RAMP signal RAMP and the pixel signal VPS, and supply AC components of the RAMP signal RAMP and the pixel signal VPS to the first input terminal INP of the comparator 11 and the second input terminal INN of the comparator 11, respectively, completely or at least partially.

The CDS circuit CDSCa may perform an auto-zero operation based on a reset level (i.e., a reset level in the LCG mode or a reset level in the HCG mode) supplied as the pixel signal VPS before the comparison operation. The first and second auto-zero switches SAZ1 and SAZ2 may be turned ON in response to the auto-zero signal AZ, and thus, the first and second input terminals INP and ON of the comparator 11 may be connected to each other, and the second and first output terminals INN and OP may be connected to each other. Accordingly, the offset of the comparator 11 can be eliminated or reduced, and the DC operation level of the comparator 11 can be determined.

When the first and second auto-zero switches SAZ1 and SAZ2 are turned ON, the voltage levels of the first input terminal INP, the second input terminal INN, the first output terminal OP, and the second output terminal ON of the comparator 11 may be the same. The voltage levels of the first input terminal INP, the second input terminal INN, the first output terminal OP, and the second output terminal ON may be referred to as auto-zero voltages. The auto-zero voltage may be determined according to the pixel signal VPS, the RAMP signal RAMP, and the offset of the comparator 11. The auto-zero voltage may be at the DC operating level of the comparator 11.

During a comparison operation after the auto-zero operation, the first and second auto-zero switches SAZ1 and SAZ2 may be turned on, and AC components of the RAMP signal RAMP and the pixel signal VPS may be added to the auto-zero voltage and applied to the first and second input terminals INP and INN of the comparator 11. During the comparison operation, when the RAMP signal RAMP having a voltage level obtained by adding an offset to the voltage level during the auto-zero operation is applied to the first input terminal INP through the first capacitor C1, the voltage level of the first input terminal INP is higher than the voltage level of the second input terminal INN, and thus, the comparator 11 may output a logic high signal. Thereafter, as the RAMP signal RAMP decreases with a certain slope, the voltage level of the first input terminal INN may decrease. The comparator 11 may output a logic low signal when the voltage level of the first input terminal INP decreases to or below the voltage level of the second input terminal INP. The period from the time when the RAMP signal RAMP starts decreasing to the time when the comparator 11 outputs the logic low signal may be generated by the counter 134 in fig. 1 as a digital value corresponding to the pixel signal (e.g., reset level or signal level).

Referring to fig. 4b, the cds circuit CDSCb may include a comparator 11, first and second auto-zero switches SAZ1 and SAZ2, first and second capacitors C1 and C2, and an amplifier 12.

The CDS circuit CDSCb may further include an amplifier 12 as compared to the CDS circuit CDSCa of fig. 4A. Amplifier 12 may be implemented, for example, as an OTA. Amplifier 12 may operate as an inverter or a buffer. The amplifier 12 may amplify or invert and amplify the comparison result signal output from the comparator 11 and output the amplified signal.

Fig. 5A and 5B schematically illustrate connections between pixels and CDS circuits in an image sensor according to various example embodiments.

Referring to fig. 5A, a switching circuit SWC may be disposed between the first to third CDS circuits 131 to 133 and the first and second column lines CL1 and CL2, and a plurality of switches SW11, SW12, SW21, SW22, SW31 and SW32 disposed in the switching circuit SWC may time-divisionally connect the first to third CDS circuits 131 to 133 to the first and second column lines CL1 and CL2.

The switches SW11, SW21 and SW31 may be turned on or off in response to the switch signals SS11, SS21 and SS31, respectively, and the switches SW12, SW22 and SW32 may be turned on or off in response to the switch signals SS12, SS22 and SS32, respectively.

The switch SW11 may be turned on to connect the first column line CL1 to the first CDS circuit 131, the switch SW21 may be turned on to connect the first column line CL1 to the second CDS circuit 132, and the switch SW31 may be turned on to connect the first column line CL1 to the third CDS circuit 133. The switches SW11, SW21 and SW31 may not be turned on at the same time but may be turned on time-divisionally at different periods. Accordingly, the first pixel signal VPS1 output from the first pixel PX1 through the first column line CL1 may be supplied to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner.

The switches SW12, SW22 and SW32 may be turned on or off in response to the switch signals SS12, SS22 and SS32, respectively. The switch SW12 may be turned on to connect the second column line CL2 to the first CDS circuit 131, the switch SW22 may be turned on to connect the second column line CL2 to the second CDS circuit 132, and the switch SW32 may be turned on to connect the second column line CL2 to the third CDS circuit 133. The switches SW12, SW22 and SW32 may not be turned on simultaneously but may be turned on time-division. Accordingly, the second pixel signal VPS2 output from the second pixel PX2 through the second column line CL2 may be supplied to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner.

Here, the switches SW11 and SW12 may not be turned on at the same time but may be turned on at different periods to selectively connect the first CDS circuit 131 to the first column line CL1 or the second column line CL2. The switches SW21 and SW22 may not be turned on simultaneously but may be turned on at different periods to selectively connect the second CDS circuit 132 to the first column line CL1 or the second column line CL2. The switches SW31 and SW32 may not be turned on simultaneously but may be turned on at different periods to selectively connect the third CDS circuit 133 to the first column line CL1 or the second column line CL2.

According to the switching operations of the plurality of switches SW11, SW12, SW21, SW22, SW31 and SW32, the first CDS circuit 131, the second CDS circuit 132 and the third CDS circuit 133 may be time-divisionally connected to the first column line CL1 and the second column line CL2, and pixels connected to the first column line CL1 and the second column line CL2, for example, the first pixel PX1 and the second pixel PX2, may be read out. The first CDS circuit 131 may generate the comparison result signal r_lcg in the LCG mode based on the pixel signal indicating the reset level of the LCG mode from the first pixel PX1 and the second pixel PX2, and the second CDS circuit 132 may generate the comparison result signal r_lcg in the HCG mode based on the pixel signal indicating the reset level of the HCG mode from the first pixel PX1 and the second pixel PX2. The third CDS circuit 133 may generate a comparison result signal r_spd in a read mode of the small photodiode SPD (for example, an SC mode or a SLOF mode to be described below) based on pixel signals from the first pixel PX1 and the second pixel PX2 according to the level of the small photodiode SPD.

Since the first and second column lines CL1 and CL2 share the first, second, and third CDS circuits 131, 132, and 133, readout periods of pixels (e.g., first and second pixels PX1 and PX 2) connected to the first and second column lines CL1 and CL2 may partially overlap each other, as described below with reference to fig. 9B. The pixel signals output through the first and second column lines CL1 and CL2, for example, the first and second pixel signals VPS1 and VPS2, may be time-divisionally applied to the second input terminal INN1 of the first comparator 11_1, the second input terminal INN2 of the second comparator 11_2, and the third input terminal INN3 of the third comparator 11_3 through the capacitors C12, C22, and C32, respectively. In this case, the first RAMP signal RAMP1 may be applied to the first input terminal INP1 of the first comparator 11_1 and the first input terminal INP2 of the second comparator 11_2 through the capacitors C11 and C21, and the second RAMP signal RAMP2 may be applied to the first input terminal INP3 of the third comparator 11_3 through the capacitor C31.

Referring to fig. 5B, the plurality of switches SW11, SW12, SW21 and SW32 may time-divisionally connect the first CDS circuit 131 and the second CDS circuit 132 to the first column line CL1 and connect the first CDS circuit 131 and the third CDS circuit 133 to the second column line CL2.

The switches SW11 and SW12 may connect the first CDS circuit 131 to the first column line CL1 or the second column line CL2 in response to the switching signals SS11 and SS 12. Here, the switches SW11 and SW12 may not be turned on at the same time, and the first CDS circuit 131 may be selectively connected to the first column line CL1 or the second column line CL2.

The switch SW21 may be turned on to connect the first column line CL1 to the second CDS circuit 132. The switches SW11 and SW21 may not be turned on at the same time, but may be turned on time-divisionally at different periods. Accordingly, the first pixel signal VPS1 output from the first pixel PX1 through the first column line CL1 may be supplied to the first CDS circuit 131 and the second CDS circuit 132 in a time-division manner.

The switch SW32 may be turned on to connect the first column line CL1 to the second CDS circuit 132. The switches SW12 and SW32 may not be turned on at the same time, but may be turned on at different time periods. Accordingly, the second pixel signal VPS2 output from the second pixel PX2 through the second column line CL2 may be supplied to the first CDS circuit 131 and the third CDS circuit 133 in a time-division manner.

Fig. 6 is a timing chart showing operations of pixels and CDS circuits in an image sensor according to various exemplary embodiments.

The readout operation of the pixel PX (e.g., the first pixel PX 1) of fig. 1 will be described with reference to fig. 5A and 6. The readout operation of the first pixel PX1 may be similarly applied to other pixels PX.

In fig. 6, it is assumed that the active (active) level of the control signals (e.g., the switching signals SS11 to SS23, the selection signal SEL, the reset signal RS, the gain control signal GCS, the switching control signal SWS, the first transmission control signal LTS, the second transmission control signal STS, the first auto-zero signal AZ1, the second auto-zero signal AZ2, and the third auto-zero signal AZ 3) is logic high (first level), and the inactive (inactive) level of the control signal is logic low (second level).

The readout period of the first pixel PX1 may be referred to as one horizontal period, and one horizontal period may be identified by a vertical synchronization signal. During the readout period of the first pixel PX1, the selection transistor SX may be turned on in response to the selection signal SEL having a logic high level. Accordingly, the first pixel PX1 may be connected to the first column line CL1, and thus, the first pixel PX1 may be read out. The readout period of the first pixel PX1 may include a first period P1 and a second period P2. During the first period P1, the large photodiode LPD may be read out; and during the second period P2, the small photodiode SPD can be read out.

The first period P1 may include first to fourth sub-periods S11, S12, S13, and S14. In the first and fourth sub-periods S11 and S14, the first pixel PX1 may operate in the LCG mode based on the large photodiode LPD. In response to the active level of the switching signal SS11, the switch SW11 may be turned on to supply the first pixel signal VPS1 to the first CDS circuit 131 through the first column line CL 1. In the first sub-period S11, the first CDS circuit 131 may read out the reset level LCG RST (hereinafter, referred to as LCG reset level) in the LCG mode, and in the fourth sub-period S14, the first CDS circuit 131 may read out the signal level LCG SIG (hereinafter, referred to as LCG signal level) in the LCG mode.

In the second and third sub-periods S12 and S13, the first pixel PX1 may operate in the HCG mode based on the large photodiode LPD. In response to the active level of the switching signal SS12, the switch SW12 may be turned on to supply the first pixel signal VPS1 to the second CDS circuit 132 through the first column line CL 1. In the second sub-period S12, the second CDS circuit 132 may read out the reset level HCG RST (hereinafter, referred to as an HCG reset signal) in the HCG mode, and in the third sub-period S13, the second CDS circuit 132 may read out the signal level HCG SIG (hereinafter, referred to as an HCG image signal) in the HCG mode.

In response to the reset signal RS transitioning from logic high to logic low in the first sub-period S11, the reset transistor RX may change from an on state to an off state. The conversion gain control transistor DRX may be turned on in response to the gain control signal GCS having a logic high level. The pixel PX may operate in the LCG mode, and the LCG reset level may be output as the first pixel signal VPS 1.

In the first sub-period S11, the switch SW11 may be turned on in response to an active level of the switching signal SS11, and thus, the first column line CL1 may be connected to the second input terminal INN1 of the first CDS circuit 131. The first auto-zeroing signal AZ1 may be switched to an active level, and in response to the first auto-zeroing signal AZ1, the first and second auto-zeroing switches SAZ11 and SAZ12 of the first CDS circuit 131 may be turned on, and thus, the first CDS circuit 131 may perform an auto-zeroing operation. When the auto-zero operation is performed, the voltage levels of the first input terminal INP1 and the second input terminal INN1 of the comparator 11_1 of the first CDS circuit 131 may be equal to the first auto-zero level.

Thereafter, the voltage level of the first input terminal INP1 may increase according to a change of the first RAMP signal RAMP1, and then decrease with a certain slope. When the voltage level of the first input terminal INP1 is less than or equal to the voltage level of the second input terminal INN1, the output of the first CDS circuit 131 (i.e., the first comparison result signal) may transition from logic high to logic low. In this way, according to the comparison operation of the comparator 11_1, the LCG reset level of the first pixel PX1 can be read out.

In the second sub-period S12, the switch SW11 may be turned off in response to an inactive level of the switch signal SS11, and the switch SW12 may be turned on in response to an active level of the switch signal SS 12. The first column line CL1 may be connected to the second input terminal INN2 of the second CDS circuit 132. The gain control signal GCS may transition from logic high to logic low and the conversion gain control transistor DRX may be turned off in response to the gain control signal GCS. The pixel PX may operate in the HCG mode, and the HCG reset level may be output as the first pixel signal VPS 1.

The second auto-zero signal AZ2 may be switched to an active level, and in response to the second auto-zero signal AZ2, the first auto-zero switch SAZ21 and the second auto-zero switch SAZ22 of the second CDS circuit 132 may be turned on, and thus, the second CDS circuit 132 may perform an auto-zero operation. When the auto-zero is performed, the voltage levels of the first input terminal INP2 and the second input terminal INN2 of the comparator 11_2 of the second CDS circuit 132 may be equal to the second auto-zero level. Thereafter, according to the comparison operation of the comparator 11_2, the HCG reset level of the first pixel PX can be read out.

In the third sub-period S13, the first column line CL1 may be connected to the second input terminal INN2 of the second CDS circuit 132. In the third sub-period S13, the first pixel PX1 may operate in the HCG mode, and the HCG image signal may be output as the pixel signal VPS. In the third sub-period S13, the first transmission control signal LTS may be switched to an active level, and the first transmission control transistor LTX may be turned on in response to the first transmission control signal LTS. The charges (electrons and/or holes) generated by the large photodiode LPD may be transferred to the first floating diffusion node FD1 and accumulated in the first floating diffusion node FD1, specifically, in a parasitic capacitor connected to the first floating diffusion node FD 1. The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1, i.e., the HCG signal level of the first pixel PX1, may be applied to the second input terminal INN2 of the second CDS circuit 132 through the first column line CL 1. Accordingly, the voltage level of the second input terminal INN2 may be lower than the second auto-zero level. Thereafter, according to the comparison operation of the comparator 11_2, the HCG signal level of the first pixel PX1 can be read out. The counter 134 in fig. 1 may calculate a difference between a value corresponding to the HCG signal level and a value corresponding to the HCG reset level as a pixel value of the HCG mode.

In the fourth sub-period S14, the switch SW12 may be turned off in response to an inactive level of the switch signal SS12, and the switch SW11 may be turned on in response to an active level of the switch signal SS 11. The first column line CL1 may be connected to the second input terminal INN1 of the first CDS circuit 131 again. The gain control signal GCS may transition from logic low to logic high and the conversion gain control transistor DRX may be turned on in response to the gain control signal GCS. The first and second floating diffusion nodes FD1 and FD2 may be connected to each other, and thus, the first pixel PX1 may operate in the LCG mode, and the LCG signal level may be output as the first pixel signal VPS 1.

The first transmission control signal LTS may be switched to an active level, and the first transmission control transistor LTX may be turned on in response to the first transmission control signal LTS. The charges remaining in the large photodiode LPD may be transferred to the first floating diffusion node FD1, and may be accumulated in the first floating diffusion node FD 1.

The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1, i.e., the LCG signal level of the first pixel PX1, may be applied to the second input terminal INN1 of the second CDS circuit 132 through the first column line CL 1. The voltage level of the second input terminal INN1 of the first CDS circuit 131 may be lower than the first auto-zero level determined in the first sub-period S11. Thereafter, according to the comparison operation of the comparator 11_1, the LCG signal level of the first pixel PX1 can be read out. The counter 134 in fig. 1 may calculate a difference between a value corresponding to the LCG signal level and a value corresponding to the LCG reset level as a pixel value of the LCG mode.

During the second period P2, the small photodiode SPD can be read out. The second period P2 may include fifth to eighth sub-periods S21, S22, S23, and S24. In the fifth and sixth sub-periods S21 and S22, the pixel PX may operate in a CDS mode (hereinafter, referred to as SC mode) based on the small photodiode SPD, and in the seventh and eighth sub-periods S23 and S24, the pixel PX may operate in a LOFIC mode (hereinafter, referred to as SLOF mode) based on the small photodiode SPD.

During the second period P2, the switch SW11 may be turned off in response to an inactive level of the switch signal SS11, and the switch SW13 may be turned on in response to an active level of the switch signal SS 13. The third CDS circuit 133 may be connected to the first column line CL1, and thus, the third CDS circuit 133 may read out the reset level SC RST and the signal level SC SIG (hereinafter, referred to as SC reset signal and SC image signal) in the SC mode, and may read out the reset level SLOF RST and the signal level SLOF SIG (hereinafter, referred to as SLOF reset signal and SLOF image signal) in the SLOF mode.

The first pixel signal VPS1 output through the first column line CL1 may be supplied to the second input terminal INN3 of the third comparison circuit 11_3 through the capacitor C32, and the second RAMP signal RAMP2 may be supplied to the first input terminal INP3 of the third comparison circuit 11_3 through the capacitor C31.

In the fifth sub-period S21, the reset transistor RX may be turned off in response to a logic low level of the reset signal RS, and the switching transistor SW may be turned on in response to a logic high level of the switching control signal SWs. Accordingly, the first, second and third floating diffusion nodes FD1, FD2 and FD3 may be electrically connected to each other to form one floating diffusion node. In this way, the first pixel PX1 may operate in the SC mode, and the SC reset level may be output as the first pixel signal VPS 1.

The third auto-zeroing signal AZ3 may be switched to an active level, and in response to the third auto-zeroing signal AZ3, the first auto-zeroing switch SAZ31 and the second auto-zeroing switch SAZ32 of the third CDS circuit 133 may be turned on, and thus, the third CDS circuit 133 may perform an auto-zeroing operation. When auto-zeroing is performed, the voltage levels of the first input terminal INP3 and the second input terminal INN3 of the comparator 11_3 of the third CDS circuit 133 may be equal to the third auto-zeroing level. Thereafter, the SC reset level can be read out according to the comparison operation of the comparator 11_3.

In the sixth sub-period S22, the first pixel PX1 may operate in the SC mode, and the SC signal level may be output as the first pixel signal VPS 1. The second transmission control signal STS may be switched to an active level, and the second transmission control transistor STX may be turned on in response to the second transmission control signal STS. The charges generated by the small photodiode SPD may be transferred to the floating diffusion nodes, that is, the first floating diffusion node third floating diffusion nodes FD1, FD2, and FD3 electrically connected to each other. The first pixel signal VPS1 corresponding to the potential of the floating diffusion node, i.e., the SC signal level of the first pixel PX1, may be applied to the second input terminal INN3 of the third CDS circuit 133 through the first column line CL 1. Accordingly, the voltage level of the second input terminal INN3 may be lower than the third auto-zero level. Thereafter, according to the comparison operation of the comparator 11_3, the SC signal level of the first pixel PX1 can be read out.

In the seventh sub-period S23, the first pixel PX1 may operate in the SLOF mode, and the SLOF signal level may be output as the first pixel signal VPS 1. The second transmission control signal STS may be switched to an active level, and the second transmission control transistor STX may be turned on in response to the second transmission control signal STS. The charge remaining in the small photodiode SPD can be transferred to the floating diffusion node. The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1, i.e., the SLOF signal level of the first pixel PX1, may be applied to the second input terminal INN3 of the third CDS circuit 133 through the first column line CL 1.

The third auto-zeroing signal AZ3 may be switched to an active level, and in response to the third auto-zeroing signal AZ3, the first auto-zeroing switch SAZ31 and the second auto-zeroing switch SAZ32 of the third CDS circuit 133 may be turned on, and thus, the third CDS circuit 133 may perform an auto-zeroing operation. When auto-zero is performed, the voltage levels of the first input terminal INP3 and the second input terminal INN3 of the comparator 11_3 of the third CDS circuit 133 may be equal to the fourth auto-zero level. Thereafter, the SLOF signal level can be read out according to the comparison operation of the comparator 11_3.

In the eighth sub-period S24, the first pixel PX1 may operate in the SLOF mode, and the SLOF reset level may be output as the first pixel signal VPS 1.

The reset signal RS may be switched to an active level, and the reset transistor RX may be turned on in response to the reset signal RS and apply the reset voltage VRD to the floating diffusion nodes, that is, to the first to third floating diffusion nodes FD1, FD2 and FD3 electrically connected to each other. Thus, the potential of the floating diffusion node increases. The SLOF reset level is output as the first pixel signal VPS1, and the voltage level of the second input terminal INN3 increases according to a change of the first pixel signal VPS 1. Thereafter, the SLOF signal level of the first pixel PX1 can be read out according to a comparison operation between the voltage level of the first input terminal INP3 of the comparator 11_3 and the voltage level of the second input terminal INN3 of the comparator 11_3.

In addition, in the second period P2, when the third CDS circuit 133 is connected to the first pixel PX1 through the first column line CL1 and reads out the pixel signal VPS of the first pixel PX1 operating in the SC mode and the SLOF mode, the first CDS circuit 131 and the second CDS circuit 132 may be connected to another pixel, for example, the second pixel PX2, through the second column line CL2 and read out the second pixel PX2 operating in the LCG mode and the HCG mode.

In response to the switching signal SS21 having an active level in the fifth and eighth sub-periods S21 and S24, the switch SW12 may be turned on and connect the second column line CL2 to the second input terminal INN1 of the first CDS circuit 131. The second pixel signal VPS2 from the second pixel PX2 according to the LCG mode may be supplied to the first CDS circuit 131 through the second column line CL 2. In response to the switching signal SS22 having an active level in the sixth and seventh sub-periods S22 and S23, the switch SW22 may be turned on and connect the second column line CL2 to the second input terminal INN1 of the second CDS circuit 132. The second pixel signal VPS2 from the second pixel PX2 according to the HCG mode may be supplied to the second CDS circuit 132 through the second column line CL 2. The operation of the second pixel PX2 in the second period P2 is the same as the operation of the first pixel PX1 in the first period P1, and thus, a repeated description thereof is omitted.

In this way, the first to third CDS circuits 131, 132, and 133 are shared by two column lines, and thus, the first and second pixels PX1 and PX2 can be read out staggered in time.

As described above, in the image sensor according to the embodiment, the first CDS circuit 131 may be used for the LCG mode, the second CDS circuit 132 may be used for the HCG mode, and the third CDS circuit 133 may be used for the SC mode and the SLOF mode. Since each of the first to third CDS circuits 131, 132 and 133 operates in response to a specific mode, each of the first to third CDS circuits 131, 132 and 133 may be customized according to the corresponding mode. For example, the first to third CDS circuits 131, 132, and 133 may be designed to cover (cover) input signals according to corresponding modes, and may have different operating ranges. Accordingly, the sizes of the transistors provided in each of the first to third CDS circuits 131, 132, and 133 may be different from each other, and thus, layout areas of the first to third CDS circuits 131, 132, and 133 may be different from each other. In this way, since each of the first to third CDS circuits 131, 132 and 133 operates in response to a specific mode, the performance of the first to third CDS circuits 131, 132 and 133 can be improved, and the circuit size (i.e., layout area) of the ADC circuit 130 in fig. 1 including the first to third CDS circuits 131, 132 and 133 can be reduced.

In addition, since the first to third CDS circuits 131, 132, and 133 are shared by two adjacent column lines according to the interleaved readout, the circuit size of the ADC circuit 130 can be reduced as compared with the case in which the first to third CDS circuits 131, 132, and 133 are provided in each column line.

As shown in fig. 5B, when the first CDS circuit 131 and the second CDS circuit 132 are connected to the first column line CL1 and the first CDS circuit 131 and the third CDS circuit 133 are connected to the second column line CL2, the first CDS circuit 131 may perform readout of an LCG pixel signal of a pixel (e.g., the first pixel PX 1) connected to the first column line CL1, and the second CDS circuit 132 may perform readout of an HCG pixel signal and the small photodiode SPD. In other words, in the first period P1, as shown in fig. 6, the first CDS circuit CDS1 and the second CDS circuit CDS2 may read out the LCG pixel signal and the HCG pixel signal of the first pixel PX1, and in the second period P2, the second CDS circuit CDS2 may read out the SC pixel signal and the SLOF pixel signal of the first pixel PX 1. In the second period P2, the first CDS circuit 131 may perform readout of the LCG pixel signal of the second pixel PX2, and the third CDS circuit 133 may perform readout of the HCG pixel signal and the small photodiode SPD.

In this way, the corresponding CDS circuits, for example, the second CDS circuit 132 and the third CDS circuit 133, can perform a readout operation on the two column lines, and the first CDS circuit 131 can share and read out the LCG pixel signals of the pixels PX connected to the two column lines by the two column lines. Accordingly, the pixels PX connected to the two column lines can be read out in an interlaced manner.

Embodiments in which two column lines share the first to third CDS circuits 131, 132, and 133 as shown in fig. 5A, and various exemplary embodiments in which two column lines share the first CDS circuit 131 as shown in fig. 5B will be described below with reference to fig. 9A and 9B.

Fig. 7 is a timing chart showing pixel signal readout schemes in the HCG mode and the LCG mode of pixels in the image sensor of the comparative example of the image sensor according to various exemplary embodiments.

Referring to fig. 7, in the image sensor according to the comparative example, one CDS circuit can read out the pixels PX. Thus, one CDS circuit can operate in response to the HCG mode and the LCG mode.

As described with reference to fig. 6, the large photodiode LPD may be read out in the first period P1 of the readout period. The first period P1 may include first to fourth sub-periods S11, S12, S13 and S14, the HCG reset level may be read out in the first sub-period S11, the HCG signal level may be read out in the second sub-period S12, the LCG signal level may be read out in the third sub-period S13, and the LCG reset level may be read out in the fourth sub-period S14. The operation of the second period P2 in which the small photodiode SPD is read out is the same as that of the second period P2 of the image sensor according to the embodiment described above with reference to fig. 6, and thus a repetitive description thereof is omitted.

In the comparative example, since one CDS circuit reads out both the HCG pixel signal and the LCG pixel signal, when the LCG pixel signal is read out after the HCG pixel signal is read out, signal levels other than the reset level are read out first. Thereafter, in response to the reset signal RS having an active level, the reset transistor RX may apply the reset voltage VRD to the first and second floating diffusion nodes FD1 and FD2, and thus the first and second floating diffusion nodes FD1 and FD2 may be reset, and then the LCG reset level may be read out. In this way, when the pixel signal is read out in the incomplete CDS method, the first and second floating diffusion nodes FD1 and FD2 are reset before the reset level is determined by the comparison operation of the CDS circuits. As a result, the correlation between the signal level and the reset level is lost. When the pixel signal is analog-to-digital converted into a pixel value, kT/C noise of the pixel PX may not be removed, and thus, signal-to-noise ratio (SNR) characteristics may be poor. Therefore, according to the comparative example, SNR characteristics may be poor when LCG pixel signals are read out.

However, as described with reference to fig. 5A and 6, since the image sensor according to various exemplary embodiments separately includes the first CDS circuit operating in the LCG mode and shared by the two column lines, and the different CDS circuits operate in the HCG mode and the LCG mode, the pixel PX may be read out in the full CDS method in the HCG mode and the LCG mode.

Fig. 8 shows SNR characteristics for each illuminance for a readout method of an image sensor according to various exemplary embodiments and for a readout method according to a comparative example.

Referring to fig. 8, the HCG mode corresponds to a lowest illuminance region, the LCG mode corresponds to a higher illuminance region than the HCG mode, the SLOF mode corresponds to a highest illuminance region, and the SC mode corresponds to a lower illuminance region than the SLOF mode.

An external processor (e.g., an application processor) may generate an HDR image by synthesizing image data generated in each of the HCG mode, the LCG mode, the SC mode, and the SLOF mode.

As described with reference to fig. 7, the image sensor according to the comparative example reads out the LCG pixel signal in the LCG mode in the incomplete CDS method, and the image sensor according to the various exemplary embodiments reads out the LCG pixel signal in the complete CDS method in the LCG mode.

When the LCG pixel signal is read out using the incomplete CDS method, SNR degradation may occur between the HCG mode and the LCG mode. As the analog gain of the HCG mode increases, the SNR drop between the HCG mode and the LCG mode further increases.

As described with reference to fig. 5 and 6, in the image sensor according to various exemplary embodiments, when the first CDS circuit 131 reads out the LCG pixel signal and the second CDS circuit 132 reads out the HCG pixel signal, both the LCG pixel signal and the HCG pixel signal may be read out in the full CDS method. Therefore, the SNR characteristic of the LCG pixel signal is good, and the SNR drop between the HCG mode and the LCG mode can be reduced. As the SNR characteristics of the LCG mode improve, the quality of the HDR image may improve. In addition, the reduction in SNR degradation between HCG mode and LCG mode makes it possible to use high analog gain in HCG mode. Thus, HDR performance can be improved by reducing quantization noise, and apparent sensitivity can be improved due to the improvement of low-illuminance SNR.

Fig. 9A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 9B is a timing chart illustrating readout of the pixel of fig. 9A.

Referring to fig. 9A, an nth pixel PX of the pixel array 110a _N N+1th pixel PX _N+1 N+2th pixel PX _N+2 And an n+3 th pixel PX _N+3 May be arranged in the same column (same position in the X-axis direction) and may be arranged in different rows, e.g. respectively the Nth row R _N N+1st row R _N+1 N+2nd row R _N+2 And row n+3R _N+3 . N-th pixel PX _N N+1th pixel PX _N+1 N+2th pixel PX _N+2 And an n+3 th pixel PX _N+3 The different column lines, i.e., the first to fourth column lines CL1, CL2, CL3 and CL4, may be connected by the first contact CT1, respectively.

N-th pixel PX _N N+1th pixel PX _N+1 N+2th pixel PX _N+2 And an n+3 th pixel PX _N+3 May be connected to a plurality of row lines RL by second contacts CT2 _N 、RL _N+1 、RL _N+2 And RL(s) _N+3 Corresponding row lines of (a) are provided. N-th pixel PX _N And an n+2th pixel PX _N+2 Can pass through the Nth row line RL separately _N And the n+2th row line RL _N+2 The same control signals (e.g., select signal, transmit control signal, switch control signal, and switch control signal) are received. N+1th pixel PX _N+1 And an n+3 th pixel PX _N+3 Can pass through the n+1th row line RL separately _N+1 And the (n+3) th row line RL _N+3 The same control signal is received. Here, although one second contact CT2 and one row line are shown to be connected to each pixel, this is for convenience of description only. For example, a plurality of second contacts CT2 and a plurality of row lines may be connected to each pixel, and the number of the second contacts CT2 and the row lines connected to each pixel may be determined according to the number of control signals.

N-th pixel PX _N N+1th pixel PX _N+1 N+2th pixel PX _N+2 And the (n+3) th imageElement PX _N+3 May include a large photodiode LPD and a small photodiode SPD as described with reference to fig. 2A and 2B.

CDS circuits CDS11, CDS12, CDS13, CDS21, CDS22, and CDS23 may be disposed at both sides of the pixel array 110 a. However, the example embodiment is not limited thereto, and CDS circuits CDS11, CDS12, CDS13, CDS21, CDS22, and CDS23 may be disposed at one side of the pixel array 110 a.

The CDS circuits CDS11, CDS12, CDS13, CDS21, CDS22, and CDS23 may be connected to the first to fourth column lines CL1, CL2, CL3, and CL4 through switching circuits SWCa and SWCb (also referred to as multiplexers). The CDS circuits CDS11, CDS12, and CDS13 may be connected to the first column line CL1 and the second column line CL2, and the CDS circuits CDS21, CDS22, and CDS23 may be connected to the third column line CL3 and the fourth column line CL4. As described with reference to fig. 5A, the switching circuits SWCa and SWCb may each include a plurality of switches, and may include the N-th to n+3-th pixels PX _N 、PX _N+1 、PX _N+2 And PX _N+3 The switching circuits SWCa and SWCb may time-divisionally connect the CDS circuits CDS11, CDS12, and CDS13 to the first and second column lines CL1 and CL2, and may time-divisionally connect the CDS circuits CDS21, CDS22, and CDS23 to the third and fourth column lines CL3 and CL4.

In a first period P1, which will be described below with reference to fig. 9B, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 may be connected to the first column line CL1 and the third column line CL3, respectively. For example, the CDS circuit CDS11 may output the pixel PX of the N _N Is connected to the first column line CL1 during a period of a pixel signal corresponding to the LCG reset level of (c), and then, the CDS circuit CDS12 may output a signal corresponding to the nth pixel PX _N Is connected to the first column line CL1 during a period of the pixel signal corresponding to the HCG reset level and the HCG signal level. Thereafter, at the output and N-th pixel PX _N During a period of the pixel signal corresponding to the LCG signal level of (a), the CDS circuit CDS11 may be connected to the first column line CL1 again. In this way, in the first period P1, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 may be respectively connected to the first column line CL1 and the third column line CL1 in time divisionColumn line CL3.

In the second period P2, the third CDS circuits CDS13 and CDS23 may be connected to the first column line CL1 and the third column line CL3, respectively. In addition, during the second period P2, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 may be connected to the second column line CL2 and the fourth column line CL4, respectively. Thereafter, in the third period P3, the third CDS circuits CDS13 and CDS23 may be connected to the second column line CL2 and the fourth column line CL4, respectively.

Accordingly, the first column line CL1 and the second column line CL2 may share the CDS circuits CDS11, CDS12, and CDS13, and the third column line CL3 and the fourth column line CL4 may share the CDS circuits CDS21, CDS22, and CDS23.

The first CDS circuits CDS11 and CDS21 can read out pixel signals of the LCG mode, the second CDS circuits CDS12 and CDS22 can read out pixel signals of the HCG mode, and the third CDS circuits CDS13 and CDS23 can read out pixel signals of the SC mode and the SLOF mode. For example, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 located below the pixel array 110a may read out pixel signals according to the large photodiodes LPD, and the third CDS circuits CDS13 and CDS23 located above the pixel array 110a may read out pixel signals according to the small photodiodes SPD.

Referring to fig. 9B, in the first readout period RD1, pixels connected to the first and third column lines CL1 and CL3, for example, nth pixels PX may be read out _N And an n+2th pixel PX _N+2 . In the second readout period RD2, pixels connected to the second column line CL2 and the fourth column line CL4, for example, the n+1th pixel PX can be read out _N+1 And an n+3 th pixel PX _N+3 . The first readout period RD1 includes a first period P1 and a second period P2, and the second readout period RD2 includes a second period P2 and a third period P3. A portion of the first readout period RD1 (the second period P2) and a portion of the second readout period RD2 (the second period P2) may overlap each other.

In the first period P1, the nth pixel PX may be sequentially read out _N And an n+2th pixel PX _N+2 An LCG reset level LCG_RST, an HCG reset level HCG_RST, an HCG signal level HCG_SIG, and an LCG signal level LCG_SIG of each of (1), andand the first CDS circuits CDS11 and CDS21 can read out the LCG reset level lcg_rst and the LCG signal level lcg_sig. The second CDS circuits CDS12 and CDS22 can read out the HCG reset level hcg_rst and the HCG signal level hcg_sig.

In the second period P2, the third CDS circuits CDS13 and CDS23 may sequentially read out the nth pixel PX _N And an n+2th pixel PX _N+2 The SC reset level sc_rst, the SC signal level sc_sig, the SLOF signal level slof_sig, and the SLOF reset level slof_rst of each of them. In addition, in the second period P2, the first CDS circuits CDS11 and CDS21 may sequentially read out the n+1th pixel PX _N+1 And an n+3 th pixel PX _N+3 The LCG reset level lcg_rst, the HCG reset level hcg_rst, the HCG signal level hcg_sig, and the LCG signal level lcg_sig of each of them.

In the third period P3, the third CDS circuits CDS13 and CDS23 may sequentially read out the n+1th pixel PX _N+1 And an n+3 th pixel PX _N+3 The SC reset level sc_rst, the SC signal level sc_sig, the SLOF signal level slof_sig, and the SLOF reset level slof_rst of each of them.

As shown in fig. 9A, are respectively arranged in the nth row R _N And row n+2R _N+2 N-th pixel PX in (a) _N And an n+2th pixel PX _N+2 Receives the same control signals and is respectively arranged on the (n+1) th row R _N+1 And row n+3R _N+3 N+1th pixel PX in (b) _N+1 And an n+3 th pixel PX _N+3 The same control signal is received. Thus, as shown in fig. 9B, the nth pixel PX _N And an n+2th pixel PX _N+2 Is read out simultaneously, and the (n+1) th pixel PX _N+1 And an n+3 th pixel PX _N+3 Is read out simultaneously. Because it is respectively connected to the nth pixel PX _N And an n+1th pixel PX _N+1 The first and second column lines CL1 and CL2 of (1) share the CDS circuits CDS11, CDS12, and CDS13 and are connected to the n+2th pixel PX, respectively _N+2 And an n+3 th pixel PX _N+3 The third column line CL3 and the fourth column line CL4 of (a) share the CDS circuits CDS21, CDS22, and CDS23, so the nth pixel PX _N And an n+2th pixel PX _N+2 N+1th pixel PX _N+1 And an n+3 th pixel PX _N+3 Can be read out simultaneously. Alternatively or additionally, readoutN-th pixel PX _N And an n+2th pixel PX _N+2 Is to read out the n+1th pixel PX _N+1 And an n+3 th pixel PX _N+3 May be staggered.

Fig. 10A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 10B is a timing chart illustrating readout of the pixel of fig. 10A.

The description of the pixel array 110A, CDS circuit arrangement, and switching circuits SWCa and SWCb, and the readout operation of the pixel of fig. 9A, which are given with reference to fig. 9A, can be similarly applied to fig. 10A and 10B, and thus, a repetitive description thereof will be omitted and differences will be described.

In a first period P1, which will be described below with reference to fig. 10B, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 may be connected to the first column line CL1 and the third column line CL3, respectively. In the second period P2, the second CDS circuits CDS12 and CDS22 may be connected to the first and third column lines CL1 and CL3, respectively. In addition, in the second period P2, the first CDS circuits CDS11 and CDS21 and the third CDS circuits CDS13 and CDS23 may be connected to the second column line CL2 and the fourth column line CL4, respectively. In the third period P3, the third CDS circuits CDS13 and CDS23 may be connected to the second column line CL2 and the fourth column line CL4, respectively.

In this way, the first column line CL1 and the second column line CL2 may share the first CDS circuit CDS11, and the third column line CL3 and the fourth column line CL4 may share the first CDS circuit CDS21. The first CDS circuits CDS11 and CDS21 may read out the nth pixel PX in the first period P1 _N And an n+2th pixel PX _N+2 Pixel signals of the LCG mode of each of the pixels and the (n+1) th pixel PX may be read out in the second period P2 _N+1 And an n+3 th pixel PX _N+3 A pixel signal of an LCG mode of each of the above. The second CDS circuits CDS12 and CDS22 can read out the nth pixel PX in the first period P1 _N And an n+2th pixel PX _N+2 The pixel signal of the HCG mode of each of the pixels, and the nth pixel PX may be read out in the second period P2 _N And an n+2th pixel PX _N+2 The pixel signals of the SC mode and the SLOF mode of each of them. The third CDS circuits CDS13 and CDS23 mayTo read out the (n+1) th pixel PX in the second period P2 _N+1 And an n+3 th pixel PX _N+3 The pixel signal of the HCG mode of each of (n+1) th pixel PX may be read out in the third period P3 _N+1 And (n+3) -th pixel PX _N+3 The pixel signals of the SC mode and the SLOF mode of each of them.

For example, the second CDS circuit CDS12 and the third CDS circuit CDS13 may read out pixels connected to the first column line CL1 and the second column line CL2, such as the nth pixel PX, respectively _N And an n+1th pixel PX _N+1 The first CDS circuit CDS11 may be shared by the first and second column lines CL1 and CL2, and thus the nth pixel PX may be read out _N And an n+1th pixel PX _N+1 LCG pixel signals of each of the (c) pixels. In addition, the second CDS circuit CDS12 and the third CDS circuit CDS13 can read out pixels connected to the third column line CL3 and the fourth column line CL4, for example, n+2th pixel PX, respectively _N+2 And an n+3 th pixel PX _N+3 The first CDS circuit CDS11 may be shared by the third and fourth column lines CL3 and CL4 and thus the n+2th pixel PX connected to the third and fourth column lines CL3 and CL4 may be read out _N+2 And an n+3 th pixel PX _N+3 LCG pixel signals of each of the (c) pixels.

Since the first CDS circuit CDS11 is shared by the first and second column lines CL1 and CL2, that is, since the first CDS circuit CDS11 is time-divisionally connected to the first and second column lines CL1 and CL2, the nth pixel PX _N And an n+1th pixel PX _N+1 The readout may be staggered. Since the first CDS circuit CDS21 is shared by the third column line CL3 and the fourth column line CL4, that is, since the first CDS circuit CDS21 is time-divisionally connected to the third column line CL3 and the fourth column line CL4, the n+2th pixel PX _N+2 And an n+3 th pixel PX _N+3 The readout may be staggered.

As described with reference to fig. 9A and 10A, in the image sensor according to various exemplary embodiments, two adjacent column lines, for example, a first column line CL1 and a second column line CL2 and a third column line CL3 and a fourth column line CL4, may share the first CDS circuits CDS11 and CDS21 for reading out LCG pixel signals and read out pixels in an interleaved manner. Therefore, the layout area of the CDS circuit can be reduced as compared with the following case: in this case, CDS circuits corresponding to each of the first to fourth column lines CL1, CL2, CL3, and CL4 are provided to read out LCG pixel signals.

Fig. 11A and 11B illustrate connections between pixels and CDS circuits in an image sensor according to various exemplary embodiments, and fig. 11C is a timing chart illustrating readout of the pixels of fig. 11A and 11B.

Referring to fig. 11a, the adc circuit 130 may be disposed at one side of the pixel array 110 and include a first CDS circuit CDS1, a second CDS circuit CDS2, and a third CDS circuit CDS3. The first to third CDS circuits CDS1, CDS2, and CDS3 may be set for each pixel pitch PPC.

In the pixel array 110, the pixels PX arranged in the same column may be alternately connected to two adjacent column lines CL. The switching circuit SWC may be disposed between the pixel array 110 and the ADC circuit 130, and time-divisionally connect two column lines to the first to third CDS circuits CDS1, CDS2, and CDS3.

Referring to fig. 11b, adc circuits 130a and 130b may be disposed on opposite sides of pixel array 110. In addition, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be disposed at one side of the pixel array 110, and the third CDS circuit CDS3 may be disposed at the other side of the pixel array 110. The switching circuit SWCa may be disposed between the pixel array 110 and the ADC circuit 130a, and may connect two column lines to the first CDS circuit CDS1 and the second CDS circuit CDS2 in a time division manner. The switching circuit SWb may be disposed between the pixel array 110 and the ADC circuit 130b, and may connect two column lines to the third CDS circuit CDS3 in a time division manner.

Referring to fig. 11C, pixels arranged in a plurality of rows of the pixel array 110, for example, nth to (n+3) th rows R _N 、R _N+1 、R _N+2 And R is _N+3 Can be read out in an interleaved manner.

In the period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be arranged in the nth row R from _N The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode. In the period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS 2) may be arranged from the row R in the nth row _N The pixel PX in (a) reads out the pixel signal SC in SC mode and the pixel signal SL in SLOF mode. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS 3) may be arranged in the n+1th row R from _N+1 The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode.

In the period T3, the third CDS circuit CDS3 may be arranged in the n+1th row R from _N+1 The pixel PX in (a) reads out the pixel signal SC in SC mode and the pixel signal SL in SLOF mode. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be arranged in the n+2th row R from _N+2 The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode.

In this way, the first CDS circuit CDS1 may be shared by two adjacent column lines CL, or the first to third CDS circuits CDS1, CDS2, and CDS3 may be shared by two adjacent column lines CL, and thus, the pixels PX arranged in a plurality of rows may be read out in an interleaved manner. In addition, since pixels arranged in two rows are read out simultaneously, the frame rate can be increased.

Fig. 12A and 12B illustrate connections between pixels and CDS circuits in an image sensor according to various exemplary embodiments, and fig. 12C is a timing chart illustrating readout of the pixels of fig. 12A and 12B.

Referring to fig. 12a, the adc circuit 130a may be disposed at one side of the pixel array 110a and include a first CDS circuit CDS1, a second CDS circuit CDS2, and a third CDS circuit CDS3. Two pairs of the first to third CDS circuits CDS1, CDS2 and CDS3 may be arranged for each pixel pitch PPC.

In the pixel array 110a, the pixels PX arranged in the same column may be alternately connected to four adjacent column lines CL. The switching circuit SWC may be disposed between the pixel array 110a and the ADC circuit 130a, and time-divisionally connects two column lines to the first to third CDS circuits CDS1, CDS2, and CDS3.

Referring to fig. 12b, adc circuits 130a and 130b may be disposed at opposite sides of the pixel array 110 a. In addition, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be disposed at one side of the pixel array 110a, and the third CDS circuit CDS3 may be disposed at the other side of the pixel array 110 a. The switching circuit SWCa may be disposed between the pixel array 110a and the ADC circuit 130a, and may connect two column lines to the first CDS circuit CDS1 and the second CDS circuit CDS2 in a time division manner. The switching circuit SWb may be disposed between the pixel array 110a and the ADC circuit 130b, and may connect two column lines to the third CDS circuit CDS3 in a time division manner.

Referring to fig. 12C, a plurality of rows (e.g., nth through n+3rd rows R) arranged in the pixel array 110a may be read out in an interleaved manner _N 、R _N+1 、R _N+2 And R is _N+3 ) Is included in the display panel.

In the period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be arranged in the nth row R from _N And row n+2R _N+2 The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode. In the period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS 2) may be arranged from the row R in the nth row _N And row n+2R _N+2 The pixel PX in (a) reads out the pixel signal SC in SC mode and the pixel signal SL in SLOF mode. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS 3) may be arranged in the n+1th row R from _N+1 And row n+3R _N+3 The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode.

In the period T3, the third CDS circuit CDS3 may be arranged in the n+1th row R from _N+1 And row n+3R _N+3 The pixel PX in (a) reads out the pixel signal SC in SC mode and the pixel signal SL in SLOF mode. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 can be formed from the circuit arranged in the n+4th row R _N+4 And row n+6R _N+6 The pixel PX in (a) reads out the pixel signal L in LCG mode and the pixel signal H in HCG mode.

In this way, the first CDS circuit CDS1 may be shared by two adjacent column lines CL, or the first to third CDS circuits CDS1, CDS2, and CDS3 may be shared by two adjacent column lines CL, and thus, the pixels PX arranged in a plurality of rows may be read out in an interleaved manner. Alternatively or additionally, the frame rate may be increased because pixels arranged in four rows are read out simultaneously.

Fig. 13A illustrates a connection between a pixel and a CDS circuit in an image sensor according to various example embodiments, and fig. 13B is a timing chart illustrating readout of the pixel of fig. 13A.

Referring to fig. 13a, the adc circuit 130 may be disposed at one side of the pixel array 110b and include a first CDS circuit CDS1, a second CDS circuit CDS2, and a third CDS circuit CDS3. The first to third CDS circuits CDS1, CDS2, and CDS3 may be set for every two pixel pitches PPC.

In the pixel array 110b, the pixels PX arranged in the same column may be connected to the same column line CL. The switching circuit SWC may be disposed between the pixel array 110c and the ADC circuit 130, and may connect two column lines to the first to third CDS circuits CDS1, CDS2, and CDS3 in a time division manner.

Referring to fig. 13B, a plurality of rows (e.g., nth through n+3rd rows R) arranged in the pixel array 110B may be read out in an interleaved manner _N 、R _N+1 、R _N+2 And R is _N+3 ) Is included in the display panel.

In the period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 may be arranged in the nth row R from _N Pixels PX in odd columns of (a) _O The pixel signal L of the LCG mode and the pixel signal H of the HCG mode are read out. In the period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS 2) may be arranged from the row R in the nth row _N Pixels PX in odd columns of (a) _O The pixel signal SC in SC mode and the pixel signal SL in SLOF mode are read out. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS 3) may be arranged from the row R in the nth row _N Pixels PX in even columns _E The pixel signal L of the LCG mode and the pixel signal H of the HCG mode are read out.

In the period T3, the third CDS circuit CDS3 may be arranged from the row R at the nth row _N The pixels PX in the even columns of (a) read out the pixel signals SC and SL in the SC and SLOF modes. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 can be formed from the circuit arranged in the n+1th row R _N+1 Pixels PX in odd columns of (a) _O Reading out pixel signals L of LCG mode and pixel signals of HCG modeNumber H.

In this way, the first CDS circuit CDS1 may be shared by two adjacent column lines CL (e.g., an odd column line and an even column line), or the first to third CDS circuits CDS1, CDS2, and CDS3 may be shared by two adjacent column lines CL, and thus, the pixels PX in odd columns arranged in a plurality of rows _O And pixels PX arranged in even columns thereof _E The readout may be staggered.

Fig. 14A and 14B illustrate a stacked structure of an image sensor according to various exemplary embodiments.

Referring to fig. 14A, an image sensor 1 according to various example embodiments may include a plurality of stacked chips. For example, the image sensor 1 may include an upper chip 40 including a pixel array area or a sensing area SA, a middle chip 50 including a circuit area LC, and a lower chip 60 including a memory area MC. In various example embodiments, the lower chip 60 may include a dummy (dummy) area DC. Dummy cells may be provided in the dummy region DC. In some example embodiments, the upper chip 40 and the intermediate chip 50 may be stacked on each other at a wafer level, and the lower chip 60 may be attached to the bottom of the intermediate chip 50 at a chip level.

The upper chip 40 may include: a sensing region SA in which a plurality of pixels PX are arranged, and a first pad region PA1 surrounding the sensing region SA. The plurality of upper PADs PAD may be arranged in the first PAD area PA1. The plurality of upper PADs PAD may be connected to PADs arranged in the second PAD area PA2 of the intermediate chip 50 through vias or the like to be connected to circuits in the circuit area LC.

The intermediate chip 50 may include: a circuit area LC in which an analog circuit and a digital circuit are arranged, and a second pad area PA2 around the circuit area LC. The circuit of the circuit region LC may include a circuit for driving a pixel circuit provided in the upper chip 40, for example, a row driver (e.g., the row driver 120 in fig. 1), an ADC circuit (e.g., the ADC circuit 130 in fig. 1), and a timing controller (e.g., the timing controller 150 in fig. 1).

The lower chip 60 may include a memory region MC and a dummy region DC. In some embodiments, the dummy region DC may be omitted. Additionally, in some embodiments, the lower chip 60 may have a package structure. For example, each of the memory region MC and the dummy region DC may be manufactured or fabricated as chips and sealed together with a sealing material, and thus, the lower chip 60 may have a package structure including two chips. Memory elements such as Dynamic Random Access Memory (DRAM) elements and/or Static Random Access Memory (SRAM) elements may be arranged in the memory region MC. However, the memory elements arranged in the memory region MC are not limited to the DRAM elements or the SRAM elements. The memory elements may not be arranged in the dummy region DC. The dummy region DC may have a function of supporting the intermediate chip 50 and the lower chip 60 instead of a function of storing data. The memory elements of the memory region MC may be electrically connected to at least some of the circuit regions LC of the intermediate chip 50 through bumps or through electrodes.

Referring to fig. 14B, the image sensor 2 according to various example embodiments may include an upper chip 70 and a lower chip 80. The upper chip 70 may include a sensing region SA in which a plurality of pixels PX are provided, a circuit region LC in which devices for driving the plurality of pixels PX are provided, and a pad region surrounding the sensing region SA and the circuit region LC. The plurality of upper PADs PAD may be arranged in the PAD area PA, and the plurality of upper PADs PAD may be connected to the memory element of the memory area MC provided in the lower chip 80 through a via or the like. The lower chip 80 may include a memory region MC and a dummy region DC. The lower chip 80 may be substantially the same as the lower chip 60 of the image sensor 1 of fig. 14A. Therefore, a detailed description of the lower chip 80 is omitted.

Referring to fig. 15, an electronic device 1000 may include an image sensor 1100 and an Application Processor (AP) 1200. The electronic device 1000 may also include various sensors, such as an illuminance sensor and/or a communication module.

The application processor 1200 may provide control signals for controlling the operation of the image sensor 1100 to the image sensor 1100. The transmission of the control signal may be performed based on an interface (e.g., an I2C-based interface). The control signals may also include configuration data for the image sensor 1100, such as one or more of lens shading correction values, crosstalk coefficients, analog gains, digital gains, and frame rate settings. The application processor 1200 may include an HDR module 141, the HDR module 141 for performing HDR processing on an image.

The image sensor 1100 can generate image data IDT by capturing an image of an object based on a received control signal. The image data IDT may include a still image and a moving image. The image sensor 1100 can perform signal processing such as one or more of image quality compensation, merging, and downsizing on the image data IDT, and the image quality compensation can include signal processing such as one or more of black level compensation, lens shading compensation, crosstalk compensation, and bad pixel correction.

The image sensor 100 described with reference to fig. 1 to 14B may be applied as the image sensor 1100. Each of the plurality of pixels included in the pixel array (e.g., the pixel array 110 in fig. 1) of the image sensor 1100 may include a first photodiode (e.g., a large photodiode) and a second photodiode (e.g., a small photodiode), and may operate in a first mode and a second mode (e.g., an LCG mode and an HCG mode) based on the first photodiode, and in a third mode and a fourth mode (e.g., an SC mode and an SLOF mode) based on the second photodiode.

The first to third CDS circuits 131, 132 and 133 in fig. 1 may read out pixels connected to two adjacent column lines, and the two column lines may share the first CDS circuit 131 reading out pixel signals of the LCG mode, or may share the first to third CDS circuits 131, 132 and 133.

Since one CDS circuit does not read out all pixel signals of the LCG mode, the HCG mode, the SC mode, and the SLOF mode, but the first CDS circuit 131 reads out pixel signals of the LCG mode, the pixel signals of the LCG mode can be read out in the full CDS method, and thus, SNR characteristics of the LCG mode can be improved. According to the staggered readout method, the first CDS circuit 131 can be shared by two column lines, and thus, the circuit size, that is, the layout area of the CDS circuit can be reduced as compared with the case where the first CDS circuit 131 is connected to each column line. Alternatively or additionally, when the first to third CDS circuits 131, 132 and 133 in fig. 1 are shared by two adjacent column lines, each of the first to third CDS circuits 131, 132 and 133 operates to correspond to a specific pattern and thus may be customized according to the corresponding pattern, and thus, performance of the first to third CDS circuits 131, 132 and 133 may be improved and/or circuit size may be reduced.

The image sensor 1100 may transmit the image data IDT or the signal-processed image data IDT to the application processor 1200. The image sensor 1100 may transmit image data IDT including first to fourth mode images corresponding to the first to fourth modes to the application processor 1200.

The transmission of the image data IDT may be performed using, for example, a Camera Serial Interface (CSI) based on a Mobile Industrial Processor Interface (MIPI), but example embodiments are not limited thereto.

The application processor 1200 may perform image processing such as one or more of bad pixel correction, 3A adjustment (auto focus correction, auto white balance, and auto exposure), noise reduction, sharpening, gamma control, reconstruction mosaic (demosaic), demosaic, and resolution scaling (video/preview) on the received image data IDT.

Alternatively or additionally, the application processor 1200 may generate an image having a high dynamic range by performing a High Dynamic Range (HDR) process on the first to fourth mode images.

According to various exemplary embodiments, according to an image sensor and a method of operating the image sensor, in an image sensor having a pixel structure in which several photoelectric conversion elements share a driving transistor, an increase in a readout circuit size may be reduced or minimized, and/or full CDS may be supported in a low conversion gain mode. Thus, in the low conversion gain mode, SNR characteristics may be improved, thereby improving image quality and/or High Dynamic Range (HDR) performance of the image sensor.

Any of the above disclosed elements and/or functional blocks may be included or implemented in processing circuitry, such as hardware including logic circuitry; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like. The processing circuitry may include electronic components such as at least one of transistors, resistors, capacitors, and the like. The processing circuitry may include electronic components, such as logic gates, including at least one of AND (AND) gates, OR (OR) gates, NAND (NAND) gates, NOT (NOT) gates, AND the like.

While the present inventive concept has been particularly shown and described with reference to various exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims. Furthermore, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

Claims

1. An image sensor, comprising:

a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first and second pixels including a first photodiode PD and a second PD sharing a driving transistor, the first and second pixels configured to operate in a first mode and a second mode according to a conversion gain based on the respective first PD, the first and second pixels configured to operate in a third mode and a fourth mode based on the respective second PD; and

an analog-to-digital converter including a first correlated double sampling CDS circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals output through the first column line and the second column line,

wherein the first CDS circuit is configured to be connected to the first column line and the second column line in a time division manner.

2. The image sensor according to claim 1, wherein the first CDS circuit is configured to read the first pattern pixel signal of the first pixel output through the first column line in a first period, and to read the first pattern pixel signal of the second pixel output through the second column line in a second period after the first period.

3. The image sensor of claim 2, wherein

The first mode pixel signals include a reset level and a signal level

The first CDS circuit is configured to read the signal level after reading the reset level.

4. The image sensor according to claim 2, wherein the second CDS circuit is configured to read the second mode pixel signal of the first pixel output through the first column line in the first period, and to read the second mode pixel signal of the second pixel output through the second column line in the second period.

5. The image sensor of claim 4, wherein the first period includes a first sub-period, a second sub-period, a third sub-period, and a fourth sub-period, the first CDS circuit is configured to read a reset level of the first mode pixel signal in the first sub-period, the second CDS circuit is configured to read a reset level of the second mode pixel signal in the second sub-period, the second CDS circuit is configured to read a signal level of the second mode pixel signal in the third sub-period, the first CDS circuit is configured to read a signal level of the first mode pixel signal in the fourth sub-period, and the first conversion gain of the first mode is smaller than the second conversion gain of the second mode.

6. The image sensor according to claim 2, wherein the third CDS circuit is configured to read the third mode pixel signal of the first signal output through the first column line and the fourth mode pixel signal of the first pixel in the second period.

7. The image sensor according to claim 1, wherein a layout area of at least one of the first CDS circuit, the second CDS circuit, and the third CDS circuit is different from another at least one of the first CDS circuit, the second CDS circuit, and the third CDS circuit.

8. The image sensor of claim 1, wherein the light receiving area of the first PD is larger than the light receiving area of the second PD.

9. The image sensor of claim 1, wherein each of the first pixel and the second pixel further comprises:

a first transfer transistor connected to the first PD and the first floating diffusion node FD;

a gain control transistor connected to the first FD and the second FD;

a reset transistor connected to the second FD and having one end configured to receive a first power supply voltage;

a second transfer transistor connected to the second PD and the third FD;

a switching transistor connected to the second FD and the third FD; and

a capacitor connected to the third FD and having one end configured to receive the first supply voltage.

10. The image sensor of claim 9, wherein the capacitor is configured to store charge spilled from the second PD.

11. The image sensor of claim 9, wherein,

in a first mode, the gain control transistor is configured to be on, and the switching transistor and the reset transistor are configured to be off,

in a second mode, the gain control transistor, the switching transistor and the reset transistor are configured to be turned off,

in a third mode, the gain control transistor and the switching transistor are configured to be on, and the reset transistor is configured to be off, and

in the fourth mode, the control transistor and the switching transistor are configured to be turned on, and the reset transistor is configured to be switched once.

12. The image sensor of claim 1, wherein the first pixel and the second pixel are in the same column and adjacent rows.

13. The image sensor of claim 1, wherein the first pixel and the second pixel are in adjacent columns and the same row.

14. An image sensor, comprising:

a pixel array including a plurality of pixels, a plurality of row lines configured to provide control signals to the plurality of pixels, and a plurality of column lines configured to output a plurality of pixel signals generated from the plurality of pixels, each of the plurality of pixels including a first photodiode PD and a second PD sharing a driving transistor;

An analog-to-digital converter configured to convert a plurality of pixel signals output through the column lines, the analog-to-digital converter including a first correlated double sampling CDS circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received through a first column line and a second column line among the plurality of column lines; and

a switching circuit configured to connect the first column line to the first CDS circuit and the second column line to the third CDS circuit in time division in the first period, and to connect the second column line to the first CDS circuit and the second CDS circuit and the first column line to the third CDS circuit in time division in the second period.

15. The image sensor of claim 14, wherein each of the plurality of pixels is configured to operate in a first mode and a second mode according to a conversion gain based on the first PD, and in a third mode and a fourth mode according to an output order based on a reset level and a signal level of the second PD.

16. The image sensor of claim 15 wherein,

in the first period, the first CDS circuit is configured to read a first mode signal of a first pixel received through a first column line, the second CDS circuit is configured to read a second mode signal of the first pixel received through the first column line, and the third CDS circuit is configured to read a third mode signal and a fourth mode signal of a second pixel received through a second column line; and

In the second period, the first CDS circuit is configured to read the first mode signal of the third pixel received through the second column line, the second CDS circuit is configured to read the second mode signal of the third pixel received through the second column line, and the third CDS circuit is configured to read the third mode signal and the fourth mode signal of the first pixel received through the first column line.

17. The image sensor of claim 14, wherein the first CDS circuit and the second CDS circuit are on a first side of the pixel array, the third CDS circuit is on a second side of the pixel array, and the first side and the second side are sides perpendicular to a direction in which the first column line and the second column line extend.

18. An electronic device, comprising:

an image sensor configured to generate a first pattern image, a second pattern image, a third pattern image, and a fourth pattern image, each of the first pattern image to the fourth pattern image configured to be generated based on one exposure; and

an application processor configured to receive each of the first, second, third, and fourth mode images from the image sensor and generate an image having a high dynamic range by synthesizing the first, second, third, and fourth mode images,

Wherein the image sensor comprises a light source, a light receiving device and a light emitting device,

a pixel array comprising a plurality of pixels, each of the plurality of pixels comprising a first photodiode PD and a second PD, the first PD and the second PD sharing a drive transistor and configured to: in the first mode and the second mode, a first mode signal and a second mode signal generated based on the charge from the first PD are output as pixel signals; and outputting, as pixel signals, a third mode signal and a fourth mode signal generated based on the electric charge from the second PD in the third mode and the fourth mode, a light receiving area of the first PD being larger than a light receiving area of the second PD, and

a first correlated double sampling CDS circuit, a second CDS circuit, and a third CDS circuit configured to time-divisionally read out a first pixel connected to a first column line and a second pixel connected to a second column line, the first pixel and the second pixel being among the plurality of pixels.

19. The electronic device according to claim 18, wherein the first CDS circuit is configured to read a first mode signal of a first pixel output through the first column line in a first period and read a first mode signal of a second pixel output through the second column line in a second period, and the first mode is a low conversion gain mode.

20. The electronic device of claim 19, wherein the first mode signal includes a reset level and a signal level, and the first CDS circuit is configured to read the signal level after reading the reset level.