KR20220047140A - Pixel array and image sensor comprising thereof - Google Patents

Abstract

Disclosed are a pixel array to generate images of improved quality and an image sensor including the same. According to an exemplary embodiment of the present invention, the pixel array comprises: a first pixel including a first floating diffusion node and a first select transistor outputting a first pixel signal according to a voltage of the first floating diffusion node; a second pixel including a second floating diffusion node and a second select transistor outputting a second pixel signal according to a voltage of the second floating diffusion node; and a column line connected to the first select transistor and the second select transistor. In low conversion gain mode, the first floating diffusion node and the second floating diffusion node are electrically connected and the first selection transistor, the second selection transistor are turned on, and thus the first pixel signal and the second pixel signal are output to the column line.

Description

A pixel array and an image sensor including the same

The technical idea of the present disclosure relates to an image sensor, and more particularly, to a pixel array having pixels sharing floating diffusion nodes and an image sensor including the same.

An image sensor is a device for capturing a two-dimensional or three-dimensional image of an object. The image sensor generates an image of an object using a photoelectric conversion element that responds to the intensity of light reflected from the object. Recently, with the development of complementary metal-oxide semiconductor (CMOS) technology, a CMOS image sensor using CMOS has been widely used. Recently, in order to increase the dynamic range of an image sensor, a dual conversion gain technology in which one pixel has two conversion gains has been studied, and a pixel array sharing a floating diffusion node between pixels has been studied. is becoming

An object of the present disclosure is to provide a pixel array having a pixel structure having a dual conversion gain by sharing a floating diffusion node between pixels, and generating an image of improved image quality, and an image sensor including the same .

In order to achieve the above object, the pixel array provided in the image sensor according to the technical idea of the present disclosure includes a first floating diffusion node and a first pixel signal outputting a first pixel signal according to a voltage of the first floating diffusion node. A first pixel including a first selection transistor, a second floating diffusion node and a second pixel including a second selection transistor outputting a second pixel signal according to a voltage of the second floating diffusion node, and the first selection transistor and a column line connected to the second selection transistor, wherein the first floating diffusion node and the second floating diffusion node are electrically connected to each other in a low conversion gain mode, the first selection transistor and the second selection transistor is turned on to output the first pixel signal and the second pixel signal to the column line.

The pixel array provided in the image sensor according to the technical spirit of the present disclosure includes a plurality of pixels arranged in a matrix and a plurality of column lines each of which is connected in common to pixels arranged in the same column among the plurality of pixels, , each of the plurality of pixels includes one or more photoelectric conversion elements for converting a received optical signal into electric charge, one or more transfer transistors for transferring the electric charge to a first floating diffusion node, and the first floating diffusion node and a second floating diffusion node. A gain control transistor connected between nodes, a driving transistor generating a pixel signal according to a voltage of the first floating diffusion node, and a corresponding column line among the plurality of column lines, the pixel signal is transmitted to the corresponding column line and a selection transistor that outputs , select transistors of the first pixel and the second pixel may be turned on.

An image sensor according to the technical spirit of the present disclosure includes a plurality of pixels arranged in a matrix, a pixel array in which a first pixel and a second pixel connected to a first column line are connected to each other, and drives the plurality of pixels, , in the low conversion mode, the floating diffusion node of the first pixel and the floating diffusion node of the second pixel are connected to each other, and the first pixel and the second pixel respectively output a pixel signal. It may include a row driver for driving a pixel, and an analog-to-digital conversion circuit for analog-to-digital conversion of a plurality of pixel signals output from a plurality of column lines of the pixel array.

According to the pixel array and the image sensor including the same according to the technical concept of the present disclosure, a plurality of pixels share floating diffusion nodes through transistors controlling a conversion gain, and a plurality of pixels in a low conversion gain mode in which the floating diffusion nodes are shared Since the source followers of the pixels are connected in parallel to the same column line, a characteristic deviation of the source follower may be reduced. Accordingly, a Pixel Response Non-Uniformity (PRNU) of an image generated in the pixel array may be reduced, and a Signal to Noise Ratio (SNR) may be improved.

1 is a block diagram illustrating an image sensor according to an embodiment of the present disclosure.
2 illustrates a pixel array according to an exemplary embodiment of the present disclosure.
3A and 3B show one implementation of a pixel array according to an exemplary embodiment of the present disclosure.
4A and 4B are diagrams and timing diagrams for explaining an LCG mode operation of a pixel array according to an exemplary embodiment of the present disclosure.
5 is a timing diagram of a pixel array according to an exemplary embodiment of the present disclosure.
6A and 6B are timing diagrams illustrating operations according to shutter methods of a pixel array according to an exemplary embodiment of the present disclosure.
7A and 7B are vertical cross-sectional views according to implementations of a pixel array according to an exemplary embodiment of the present disclosure.
8 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure.
9A shows an implementation example of a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 9B is a timing diagram of the pixel array of FIG. 9A .
10 illustrates a pixel array according to an exemplary embodiment of the present disclosure.
11 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure.
12 illustrates a pixel array according to an exemplary embodiment of the present disclosure.
13 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure.
14A, 14B, and 14C illustrate color filters disposed in a pixel array according to an exemplary embodiment of the present disclosure.
15 is a block diagram of an electronic device including a multi-camera module.
16 is a detailed block diagram of the camera module of FIG. 15 .

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an image sensor according to an embodiment of the present disclosure.

The image sensor 100 may be mounted on an electronic device having an image or light sensing function. For example, the image sensor 100 may include a camera, a smartphone, a wearable device, the Internet of Things (IoT), a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (portable multimedia player), It may be mounted in an electronic device such as a navigation device. In addition, the image sensor 100 may be mounted in an electronic device provided as a component in a vehicle, furniture, manufacturing equipment, door, various measurement devices, and the like.

The image sensor 100 includes a pixel array 110 , a row driver 120 , a ramp signal generator 130 , an analog-to-digital conversion circuit 140 (hereinafter referred to as an ADC circuit), and a data output circuit 150 . ) and a timing controller 160 . The image sensor 100 may further include a signal processing unit 170 .

The pixel array 110 is connected to a plurality of row lines RL, a plurality of column lines CL, and a plurality of row lines RL and a plurality of column lines CL, and a plurality of pixels PX arranged in a matrix. ) is included. Pixels PX arranged in the same column may be connected to the same column line CL.

The pixel PX may sense light by using a photoelectric conversion element, and may output an image signal that is an electrical signal according to the sensed light. The photoelectric conversion element may be a photo-sensing element made of an organic material or an inorganic material, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode. can

In the pixel array 110 according to the embodiment of the present disclosure, floating diffusion nodes provided in each of the at least two pixels PX may be shared between at least two pixels PX connected to the same column line and disposed adjacent to each other. . The pixel PX may have a dual conversion gain, and at least two pixels PX may share floating diffusion nodes through a gain control transistor for controlling the conversion gain in the low conversion gain mode. In this case, the selection transistor provided in each of the at least two pixels PX may be turned on. In other words, the plurality of selection transistors of the at least two pixels PX may be turned on. Accordingly, at least two source followers included in the at least two pixels PX may operate, and at least two pixel signals generated from the at least two source followers may be simultaneously provided to a column line. An average value of at least two pixel signals may be output to the ADC circuit 140 through the column line CL. Accordingly, noise caused by a characteristic variation between pixels PX of a transistor constituting a source follower between pixels PX may be reduced, and image quality generated by the image sensor 100 may be improved. .

In an embodiment, at least two pixels PX sharing the floating diffusion nodes may be arranged in different rows and in the same column. However, the present invention is not limited thereto, and at least two pixels PX may be disposed in the same row and different columns.

In an embodiment, color filters of the same color or color filters of different colors may be disposed on at least two pixels PX.

The pixel array 110 and the pixel PX provided in the pixel array 110 according to an embodiment of the present disclosure will be described later in detail with reference to FIGS. 2 to 14B .

The row driver 120 drives the pixel array 110 in a row unit. The row driver 120 decodes a row control signal (eg, an address signal) received from the timing controller 190 , and responds to the decoded row control signal in response to at least one of row lines constituting the pixel array 110 . You can select the line of the line. For example, the row driver 120 may generate a selection signal for selecting one of a plurality of rows. In addition, the pixel array 110 outputs a pixel signal, eg, a pixel voltage, from a row selected by the selection signal provided from the row driver 120 . The pixel signal may include a reset signal and an image signal.

The row driver 120 may transmit control signals for outputting a pixel signal to the pixel array 110 , and the pixel PX may output a pixel signal by operating in response to the control signals.

The ramp signal generator 130 may generate a ramp signal (eg, ramp voltage) whose level rises or falls with a predetermined slope under the control of the timing controller 160 . The ramp signal RAMP may be provided to a plurality of CDS circuits 141 included in the ADC circuit 140 , respectively.

The ADC circuit 140 includes a plurality of ADCs 141 , and each of the plurality of ADCs 141 may include a CDS circuit 142 (correlated double sampling circuit) and a counter 143 . The ADC circuit 140 may convert a pixel signal (eg, a pixel voltage) input from the pixel array 110 into a pixel value that is a digital signal. Each pixel signal received through each of the plurality of column lines CL is converted into a pixel value that is a signal at the corresponding ADC 141 among the plurality of ADCs 141 .

The CDS circuit 142 may compare a pixel signal, eg, a pixel voltage, received through the column line CL with the ramp signal RAMP, and output the comparison result as a comparison result signal. The CDS circuit 142 may output a comparison signal transitioning from the first level (eg, high level) to the second level (eg, low level) when the level of the ramp signal RAMP and the level of the pixel signal are the same. . The timing at which the level of the comparison signal transitions may be determined according to the level of the pixel signal.

The CDS circuit 142 may sample a pixel signal provided from the pixel PX according to a correlated double sampling (CDS) method. The CDS circuit 142 may generate a comparison signal according to the reset signal by sampling the reset signal received as a pixel signal and comparing the reset signal with the ramp signal RAMP. The CDS circuit 142 may store a reset signal. Thereafter, the CDS circuit 142 may generate a comparison signal according to the image signal by sampling the image signal correlated with the reset signal and comparing the image signal with the ramp signal RAMP.

The counter 143 may count a level transition time of the comparison result signal output from the CDS circuit 142 , and output the count value as a pixel value.

In some embodiments, the counter 143 includes an up-counter and arithmetic circuit that sequentially increases a count value based on a counting clock signal provided from the timing controller 160 , an up/down counter, or a bit-wise inversion It may be implemented as a counter (bit-wise inversion counter). In an embodiment, the image sensor 100 further includes a code generator generating a plurality of code values having a resolution according to the set number of bits as a counting code, and the counter 143 is a counting code based on the comparison result signal. It may include a latch circuit for latching a value and an arithmetic circuit.

The data output circuit 150 may temporarily store the pixel value output from the ADC circuit 140 and then output it. The data output circuit 150 may include a plurality of column memories 151 and a column decoder 152 . The column memory 151 stores pixel values received from the counter 142 . In an embodiment, each of the plurality of column memories 151 may be provided in the counter 142 . A plurality of pixel values stored in the plurality of column memories 151 may be output as image data IDT1 under the control of the column decoder 152 .

The timing controller 160 outputs a control signal to each of the row driver 120 , the ramp signal generator 130 , the ADC circuit 140 , and the data output circuit 150 , and the row driver 120 , the ramp signal generator ( 130 ), the ADC circuit 140 , and the data output circuit 150 may control operations or timing.

The signal processing unit 170 may perform image processing, for example, noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, and binning, on the image data IDT1. In an embodiment, the signal processing unit 170 may be provided in an external processor of the image sensor 100 .

The image-processed image data IDT2 may be provided to an external processor, for example, a central processor unit (CPU), a graphic processing unit (GPU), an application processor (AP) of an electronic device provided with the image sensor 100, and the like.

2 illustrates a pixel array according to an exemplary embodiment of the present disclosure. The pixel array 110a of FIG. 2 may be applied as the pixel array 110 to the image sensor 100 of FIG. 1 .

Referring to FIG. 2 , the pixel array 110a may include a plurality of pixels PX arranged in a matrix. The plurality of pixels PX may be arranged in a plurality of rows and columns. For example, the plurality of pixels PX may be arranged in first to mth rows (R1 to Rm, m is a positive integer) and first to nth columns C1 to Cn.

A plurality of row lines (RL in FIG. 1 ) may extend in a first direction, for example, an X-axis direction, and pixels disposed in the same row may be connected to the same row line. A plurality of column lines CL may extend in a second direction, for example, a Y-axis direction, and pixels disposed in the same column may be connected to the same column line CL.

A current source CS is connected to each of the plurality of column lines CL, and at least one of the pixels PX connected to the column line CL is selected based on the driving current I _L provided by the current source CS. A pixel signal may be generated from one pixel, for example, at least one pixel PX in which a selection transistor is turned on, and the pixel signal may be provided to the ADC 141 of the ADC circuit 140 through a column line CL. .

The pixel array 110a is driven in a row unit, and a plurality of pixel signals generated from the pixels PX arranged in the same row are simultaneously provided to the ADC circuit 140 through a plurality of column lines CL to be converted into ADC. can

In the pixel array 110a of FIG. 2 , at least two pixels PX disposed in the same column and adjacent to each other may be electrically connected through an internal device. For example, as shown in FIG. 2 , two pixels PX disposed in a first row R1 and a second row R2 are connected, and a third row R3 and a fourth row R4 are connected. ) may be connected to each other, and two pixels PX connected to the m−1 th row Rm−1 and the mth row Rm may be connected to each other. In this way, each of the two pixels PX may be connected to share the floating diffusion nodes.

3A and 3B show one implementation of a pixel array according to an exemplary embodiment of the present disclosure. 3A and 3B are exemplary implementations of the pixel array 110a of FIG. 2 . For convenience of description, two pixels PX1 and PX2 are illustrated.

Referring to FIG. 3A , the pixel array 110a may include a first pixel PX1 and a second pixel PX2 disposed in a first row R1 and a second row R2 , respectively. The first pixel PX1 and the second pixel PX2 may be connected to the same column line CL and may be internally connected to each other.

The first pixel PX1 includes a photoelectric conversion element PD1 and a plurality of transistors such as a transfer transistor TX1, a reset transistor RX1, a gain control transistor CGX1, a driving transistor DX1, and a selection transistor ( SX1) may be included.

The photoelectric conversion element PD1 may convert light incident on the first pixel PX1 into an electric signal. The photoelectric conversion element PD1 may be, for example, a photodiode. The photoelectric conversion element PD1 generates electric charges according to light intensity. The amount of electric charge generated by the photoelectric conversion element PD1 varies according to the photographing environment (low or high light) of the object. For example, the amount of charge generated by the photoelectric conversion element PD1 in a high illuminance environment may reach a full well capacity (FWC) of the photoelectric conversion element PD1, but this may not be the case in a low illuminance environment.

The transfer transistor TX1 , the reset transistor RX1 , the driving transistor DX1 , the selection transistor SX1 , and the gain control transistor CGX1 each receive control signals provided from the row driver ( 120 of FIG. 1 ), for example, reset It may operate in response to the control signal RS1 , the transmission control signal TS1 , the selection signal SEL1 , and the gain control signal CGS1 .

The reset transistor RX1 may reset the first floating diffusion node FD11 and the second floating diffusion node FD12 . The reset transistor RX1 may be turned on in response to the reset control signal RS1 applied to the gate terminal to provide the pixel power voltage VDDP as a reset voltage to the second floating diffusion node FD12 . In this case, as the gain control transistor CGX1 is turned on together based on the gain control signal CGS1 received at the gate terminal, the pixel power voltage VDDP may be applied to the first floating diffusion node FD11 . Accordingly, the first floating diffusion node FD11 and the second floating diffusion node FD12 may be reset.

The transfer transistor TX1 may be turned on in response to the transfer signal TS1 , and may transfer charges generated in the photoelectric conversion element PD1 to the first floating diffusion node FD11 . Charges transferred to the first floating diffusion node FD11 may be stored. In other words, the capacitor C _H1 may be formed in the first floating diffusion node FD11 , and electric charges may be stored in the capacitor C _H1 of the first floating diffusion node FD11 . As charges are accumulated in the capacitor C _H1 , the voltage of the first floating diffusion node FD11 may be lowered. Accordingly, the voltage of the first floating diffusion node FD11 may be determined according to the amount of charge generated by the photoelectric conversion element PD1 and stored in the capacitor C _H1 . In other words, the charge accumulated in the first floating diffusion node FD11 may be converted into a voltage. The unit of the conversion gain may be, for example, uV/e.

The conversion gain is determined by the capacitance of the first floating diffusion node FD11 and may be inversely proportional to the capacitance. When the capacitance of the first floating diffusion node FD11 increases, the conversion gain decreases, and when the capacitance decreases, the conversion gain increases.

The driving transistor DX1 may generate a pixel signal (eg, a pixel voltage) based on the voltage of the first floating diffusion node FD11 applied to the gate. The driving transistor DX1 may generate a pixel signal by amplifying the voltage of the first floating diffusion node FD11 . The driving transistor DX1 may operate as a source follower.

The selection transistor SX1 may select the first pixel PX1 . The selection transistor SX1 is turned on in response to the selection signal SEL1 applied to the gate terminal, and may output the pixel signal output from the driving transistor DX1 to the column line CL.

The gain control transistor CGX1 may be connected between the first floating diffusion node FD11 and the second floating diffusion node FD12 . A capacitor C _L1 may be formed in the second floating diffusion node FD12 . The capacitor C _L1 is a passive element having a fixed or variable capacitance, or a parasitic capacitor formed by the source/drain of the gain control transistor CGX1 or another pixel that may be connected to the source/drain of the gain control transistor CGX1, For example, it may be a parasitic capacitor formed in the second pixel PX. The gain control transistor CGX1 may be turned on in response to the gain control signal CGS1 to connect the second floating diffusion node FD12 to the first floating diffusion node FD11 .

The second pixel PX2 includes a photoelectric conversion element PD2, and a plurality of transistors such as a transfer transistor TX2, a reset transistor RX2, a gain control transistor CGX2, a driving transistor DX2, and a selection transistor ( SX2) may be included.

The transfer transistor TX2 , the reset transistor RX2 , the driving transistor DX2 , the selection transistor SX2 , and the gain control transistor CGX1 each receive control signals provided from the row driver ( 120 of FIG. 1 ), for example, reset The operation may be performed in response to the control signal RS2 , the transmission control signal TS2 , the selection signal SEL2 , and the gain control signal CGS2 .

The operation of the transfer transistor TX2 , the reset transistor RX2 , the driving transistor DX2 , the selection transistor SX2 , and the gain control transistor CGX2 of the second pixel PX2 is the transfer transistor of the first pixel PX1 . Operations of TX1, reset transistor RX1, driving transistor DX1, selection transistor SX1, and gain control transistor CGX1 are the same as or similar to those of operation.

As illustrated in FIG. 3A , the second floating diffusion node FD22 of the second pixel PX2 may be connected to the second floating diffusion node FD12 of the first pixel PX1 . Accordingly, when the gain control transistor CGX1 of the first pixel PX1 and the gain control transistor CGX2 of the second pixel PX2 are turned on, the first floating diffusion node FD11 of the first pixel PX1 ) and the second floating diffusion node FD12 , and the first floating diffusion node FD21 and the second floating diffusion node FD22 of the second pixel PX2 may be electrically connected to each other. Since capacitances of the first floating diffusion node FD11 of the first pixel PX1 and the first floating diffusion node FD21 of the second pixel PX2 are increased, a conversion gain may be increased. When the gain control transistor CGX1 of the first pixel PX1 and the gain control transistor CGX2 of the second pixel PX2 are turned off, the high conversion gain (HCG) mode is turned on to the low conversion gain. (LCG) mode.

As such, the first pixel PX1 and the second pixel PX2 may operate in one of the HCG mode and the LCG mode according to the turn-on and turn-off of the gain control transistors CGX1 and CGX2 . In the HCG mode, since the conversion gain of pixels, for example, the first pixel PX may increase, the gain of circuits (eg, the ADC circuit 140 ) for processing the pixel signal output from the first pixel PX This relative can be reduced. Accordingly, the signal to noise ratio (SNR) of the image sensor ( 100 of FIG. 1 ) may be increased, so that the minimum detectable light amount may be lowered, and the low light amount sensing performance of the image sensor 100 may be improved. In the LCG mode, since the capacitance of the first floating diffusion node FD11 of the first pixel PX is increased, full well capacity (FWC) may be increased. Accordingly, the high light amount detection performance of the image sensor 100 may be improved.

Referring to FIG. 3B , the first pixel PX1a includes a plurality of photoelectric conversion elements, for example, first and second photoelectric conversion elements PD1a and PD1b and a plurality of transfer transistors connected to each of the plurality of photoelectric conversion elements, for example, a first and second transfer transistors TX1a and TX1b. The first and second transfer transistors TX1a and TX1b may be turned on or off in response to the first and second transfer control signals TS1a and TS1b. The first and second transmission control signals TS1a and TS1b may be the same or different signals.

The second pixel PX2a may also include first and second photoelectric conversion elements PD2a and PD2b and first and second transfer transistors TX2a and TX2b. The first and second transfer transistors TX2a and TX2b may be turned on or off in response to the first and second transfer control signals TS2a and TS2b.

In FIG. 3B , the first pixel PX1a and the second pixel PX1a are illustrated as including two photoelectric conversion elements and two transfer transistors, respectively, but are not limited thereto, and the first pixel PX1a and the second pixel PX1a are not limited thereto. Each of the pixels PX1a may include three or more photoelectric conversion elements and three or more transfer transistors.

4A is a diagram for explaining an LCG mode operation of a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 4B is a timing diagram of FIG. 4A . 4A and 4B illustrate operations of the first pixel PX1 and the second pixel PX2 when a pixel signal is read out from the first pixel PX1 .

4A and 4B , the gain control transistors CGX1 and CGX2 of the first pixel PX1 and the second pixel PX2 have an inactive level, for example, the control signals CGS1 having a high level H. It can be turned on in response to CGS2). Accordingly, the first pixel PX1 and the second pixel PX2 may operate in the LCG mode. The transfer transistor TX2 of the second pixel PX2 may be turned off in response to the transfer control signal TS2 having an inactive level, for example, a low level L.

In the reset period RST, the reset transistors RX1 and RX2 of the first and second pixels PX1 and PX2 are turned on in response to the high-level reset control signals RS1 and RS2, and the first floating diffusion The pixel power voltage VDDP is applied to the nodes FD11 and FD21 and the second floating diffusion nodes FD12 and FD22, so that the first floating diffusion nodes FD11 and FD21 and the second floating diffusion nodes FD12 and FD22 are applied. ) can be reset. The reset of the first floating diffusion nodes FD11 and FD21 and the second floating diffusion nodes FD12 and FD22 is stored in the first floating diffusion nodes FD11 and FD21 and the second floating diffusion nodes FD12 and FD22. It means that the (accumulated) charge has been discharged.

At a time t1 , the transmission control signal TS1 applied to the first pixel PX1 may transition from an inactive level, for example, a low level, to an active level, for example, a high level. The first transfer transistor TX1 may be turned on in response to the transfer control signal TS1 to transfer (discharge) the charge remaining in the photoelectric conversion element PD1 to the first floating diffusion node PD1 . Thereafter, the first transfer transistor TX1 is turned off in response to the low-level transfer control signal TS1 , and the reset transistors RX1 and RX2 are turned on, so that the first floating diffusion node PD1 An electric charge may be discharged.

A charge generation and accumulation operation according to light incident from the photoelectric conversion element PD1 may be started. During the exposure period EP, a charge generation and accumulation operation may be performed in the photoelectric conversion device PD1 . Specifically, charge generation and accumulation operations may be performed in the photoelectric conversion element PD1 until the selection transistor SX1 is turned on at time t2.

At time t2 , the selection transistor SX1 of the first pixel PX1 may be turned on in response to the high level selection signal SEL1 . The selection transistor SX1 may be turned on during the read period RO (or referred to as a horizontal read period). In this case, the selection transistor SX2 of the second pixel PX2 may also be turned on in response to the high level selection signal SEL2 . In other words, during the read period RO for the first pixel PX1 , the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 may be turned on. During the read period RO, the reset transistors RX1 and RX2 may be turned off.

Since the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 are turned on, pixel signals may be output to the column line CL. a pixel signal output from the first pixel PX1;

At time t3 , the transfer transistor TX1 may be turned on in response to the high level transfer control signal TS1 . Charges generated in the photoelectric conversion element PD1 during the exposure period EP may be transferred to the first floating diffusion node FD11 . The first floating diffusion node FD11 is connected to the second floating diffusion node FD12 and the first and second floating diffusion nodes FD21 and FD22 of the second pixel, and electric charges are applied to the first pixel and the second pixel. and the second floating diffusion nodes FD11, FD12, FD21, and FD22, and the first and second floating diffusion nodes FD11, FD12, FD21, and FD22 may have the same voltage.

In the read period RO, the driving transistors DX1 of the first and second pixels PX1 and PX2 transmit pixel signals according to voltages of the first floating diffusion nodes FD1 and FD2, for example, the first pixel voltage Vpx1 ) and the second pixel voltage Vpx2 may be output. When the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 are turned on, the first pixel voltage Vpx1 and the second pixel voltage Vpx2 are transferred to the column line CL. can be output.

Since voltages of the first and second floating diffusion nodes FD11 , FD12 , FD21 , and FD22 are the same, the first pixel voltage Vpx1 and the second pixel voltage Vpx2 may be the same. However, due to a characteristic deviation between the driving transistor DX1 of the first pixel PX1 and the driving transistor DX2 of the second pixel PX2, there is a difference in the first pixel voltage Vpx1 and the second pixel voltage Vpx2. there may be In the column line CL), the first pixel voltage Vpx1 and the second pixel voltage Vpx2 are averaged, and the average pixel signal corresponding to the average value of the first pixel voltage Vpx1 and the second pixel voltage Vpx2 is generated by the CDS circuit (142 in FIG. 1), and the average pixel signal may be sampled in the CDS circuit 142.

As described above with reference to FIG. 1 , the pixel signal may include a reset signal and an image signal, and the CDS circuit ( 142 of FIG. 1 ) connected to the column line CL1 samples the pixel signal twice according to the CDS method. By doing so, the reset signal and the image signal can be sampled. Before time t3, the reset signal RL (which is a reset signal in the LCG mode, hereinafter referred to as the LCG reset signal) is sampled, and after the transfer transistor TX1 is toggled at time t3, the image signal SL (LCG) image signal in mode, hereinafter referred to as an LCG image signal) may be sampled.

As described above, in the pixel array 110a, an output deviation of pixels may occur due to a characteristic deviation of the driving transistors DX1 and DX2 of the pixels, for example, the first and second pixels PX1 and PX2. For example, even if the first floating diffusion node FD11 of the first pixel PX1 and the first floating diffusion node FD21 of the second pixel PX2 have the same voltage, the first and second pixels PX1 and PX2 A deviation may occur in the first pixel voltage Vpx1 and the second pixel voltage Vpx2 output from the . The output deviation between the pixels generates noise in the image generated by the image sensor ( 100 in FIG. 1 ), which is referred to as pixel response non-uniformity (PRNU).

However, as described with reference to FIGS. 4A and 4B , in the pixel array 110a according to the embodiment of the present disclosure, when the pixel array 110a operates as an LCG, at least two pixels connected to the same column line, for example, the second The floating diffusion nodes of the first pixel PX1 and the second pixel PX2 are connected to each other, and when a pixel signal is read from one pixel, a pixel signal is output from at least one other connected pixel, and at least two pixel signals are averaged By sampling the averaged pixel signal, PRNU can be reduced and high luminance SNR can be improved. Accordingly, the image quality of the image generated by the image sensor 100 in the LCG mode may be improved.

5 is a timing diagram of a pixel array according to an exemplary embodiment of the present disclosure. FIG. 5 shows an intra scene dual conversion gain (DCG) mode operation in which a pixel of a pixel array (110a in FIG. 3A ), eg, a first pixel PX1 , operates in an LCG mode and an HCG mode during a read period in one frame.

3A and 5 , the gain control transistor CGX2 of the second pixel PX2 is turned on in response to the high-level gain control signal CGS1, and the transfer transistor CGX2 of the second pixel PX2 is turned on. TX2) may be turned off in response to the high level transmission control signal TS1.

At time t1 , the first transfer transistor TX1 of the first pixel PX1 is turned on in response to the high-level transfer control signal TS1 , so that the charge remaining in the photoelectric conversion element PD1 is transferred to the first floating diffusion It can transmit (discharge) to the node PD1. Thereafter, the first transfer transistor TX1 is turned off in response to the low-level transfer control signal TS1 , and the reset transistors RX1 and RX2 are turned on, so that the first floating diffusion node PD1 An electric charge may be discharged.

A charge generation and accumulation operation according to light incident from the photoelectric conversion element PD1 may be started. During the exposure period EP, a charge generation and accumulation operation may be performed in the photoelectric conversion device PD1 .

At time t2 , the selection transistor SX1 of the first pixel PX1 may be turned on in response to the high-level selection signal SEL1 . The selection transistor SX1 of the first pixel PX1 may be turned on during the read period RO (or referred to as a horizontal read period). The reset transistors RX1 and RX2 may also be turned off during the read period RO in response to the low-level reset control signals RS1 and RS2 . At time t2 , the selection transistor SX2 of the second pixel PX2 may also be turned on in response to the high level selection signal SEL2 . The gain control transistor CSX1 of the first pixel PX2 may be turned on in response to the high level gain control signal CGS1 . The first pixel PX1 may be in the LCG mode, and the first pixel PX1 and the second pixel PX2 output a first pixel voltage Vpx1 and a second pixel voltage Vpx2 corresponding to a reset signal, respectively. can do. After time t2, the LCG reset signal RL may be sampled in the LCG mode. The sampled LCG reset signal RL may correspond to an average value of the reset signals of the first and second pixels PX1 and PX2.

At time t3 , the gain control transistor CSX1 of the first pixel PX2 may be turned off in response to the low-level gain control signal CGS1 . Accordingly, the first pixel PX1 may be changed to the HCG mode. The selection transistor SX2 of the second pixel PX2 may also be turned off in response to the low-level selection signal SEL2 . Accordingly, the first pixel PX1 may output the first pixel voltage PX1 corresponding to the reset signal to the column line CL.

After time t3, the HCG reset signal RL may be sampled in the HCG mode. The sampled HCG reset signal RH may correspond to a reset signal output from the first pixel PX1 .

At time t4 , the transfer transistor TX1 may be turned on in response to the high level transfer control signal TS1 . Charges generated in the photoelectric conversion element PD1 during the exposure period EP may be transferred to the first floating diffusion node FD11 . The driving transistor DX1 of the first pixel PX1 may generate a pixel signal according to the voltage of the first floating diffusion node FD11 , that is, an image signal. The first pixel PX1 may generate, for example, a first pixel voltage Vpx1 corresponding to a pixel corresponding to an image signal. The first pixel voltage Vpx1 may output the first pixel voltage Vpx1 corresponding to the image signal to the column line CL.

After time t4, the HCG image signal SH may be sampled in the HCG mode. The sampled HCG image signal SH is an image signal output from the first pixel PX1 .

At time t5 , the gain control transistor CSX1 of the first pixel PX2 may be turned on in response to the high level gain control signal CGS1 . Accordingly, the floating diffusion nodes FD11 , FD12 , FD21 , and FD22 of the first pixel PX1 and the second pixel PX2 may be connected to each other. The capacitance of the first floating diffusion node FD11 of the first pixel PX1 may be increased. The first pixel PX1 may be changed to the LCG mode. At time t5 , the selection transistor SX2 of the second pixel PX2 may also be turned on in response to the high level selection signal SEL2 .

At time t6, the transfer transistor TX1 may be turned on in response to the high-level transfer control signal TS1. Charges remaining in the photoelectric conversion element PD1 may be transferred to the first floating diffusion node FD11 .

After time t6, the LCG image signal SL may be sampled in the LCG mode. In this case, the first pixel PX1 and the second pixel PX2 may output a first pixel voltage Vpx1 and a second pixel voltage Vpx2 corresponding to an image signal, respectively. Accordingly, the LCG image signal SL may correspond to an average value of the image signals of the first pixel PX1 and the second pixel PX2 .

In this way, the LCG reset signal RL, the HCG reset signal RH, the HCG image signal SH, and the LCG image signal SL for the plurality of pixels PX of the pixel array 110a during the read period RO. ) can be sampled sequentially. An LCG image is generated based on an LCG reset signal RL and an LCG image signal SL of each of the plurality of pixels PX, and an HCG reset signal RH and an HCG image signal of each of the plurality of pixels PX An HCG image may be generated based on (SH). The signal processing unit (170 in FIG. 1) of the image sensor (100 in FIG. 1) or the signal processing unit of the external host merges the LCG image and the HCG image to generate an image having a high dynamic range. there is.

6A and 6B are timing diagrams illustrating operations according to shutter methods of a pixel array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6A , the pixel array ( 110 of FIG. 1 ) may operate according to a rolling shutter method. During one frame period FRM, a reset operation and charge generation are respectively performed in the reset period RST, the exposure period EP, and the read period RO for each of a plurality of rows, for example, the first to mth rows R1 to Rm. and an accumulation operation and a read operation may be performed, and a reset, exposure, and read operation may be sequentially performed with respect to the first to mth rows R1 to Rm. The read periods RO of the first to mth rows R1 to Rm do not overlap.

Referring to FIG. 6B , the pixel array ( 110 of FIG. 1 ) may operate according to a global shutter method. During one frame period FRM, reset, exposure, and readout are respectively performed in the reset period RST, the exposure period EP, and the read period RO for each of the plurality of rows, for example, the first to mth rows R1 to Rm. The operation may be performed, and the reset operation of the first to mth rows R1 to Rm and the charge generation and accumulation operation may be simultaneously performed. The read operations of the first to mth rows R1 to Rm may be sequentially performed, and the read periods RO of the first to mth rows R1 to Rm do not overlap.

Two rows adjacent to the read period RO of FIGS. 6A and 6B , for example, the first row R1 and the second row R2 , the third row R3 and the fourth row R4 , and the m−1th row The operations of the two pixels PX provided in (Rm-1) and the mth row Rm and connected to the same column line are the first pixel PX1 and the second pixel PX1 of FIG. 4A described with reference to FIGS. 4B or 5 . The operation of the pixel PX2 may be the same.

For example, when the read operation of the first row R1 is performed, the operations of the first pixel PX1 of the first row R1 and the second pixel R2 of the second row R2 are The operations of the pixel PX1 and the second pixel PX2 are the same, respectively, and when the read operation of the second row R1 is performed, the first pixel PX1 and the second row R1 of the first row R1 The operation of the second pixel R2 of R2 may be the same as that of the second pixel PX2 and the first pixel PX1 of FIG. 4A , respectively. When the read operation of the third row R3 is performed, the operation of the third pixel PX3 of the third row R3 and the fourth pixel R4 of the fourth row R4 is the first pixel of FIG. 4A . The operations of the PX1 and the second pixel PX2 are the same, respectively, and when the read operation of the third row R1 is performed, the first pixel PX3 and the fourth row R4 of the third row R3 are the same. ), the operation of the fourth pixel R4 may be the same as that of the second pixel PX2 and the first pixel PX1 of FIG. 4A , respectively.

7A and 7B are vertical cross-sectional views according to implementations of a pixel array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7A , the pixel array 110 includes a semiconductor substrate 111 (hereinafter referred to as a substrate) having a first surface 111B and a second surface 111F opposite to each other, and a first surface of the substrate 111 . It may include an incident layer 112 disposed on the 111B and a wiring layer 113 (or referred to as a wiring structure) disposed on the second surface 111F of the substrate 111 .

The substrate 111 may include, for example, at least one selected from among Si, Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 111 may be doped with an impurity of the first conductivity type. For example, the first conductivity type may be P-type, and the impurity of the first conductivity type may be boron.

A deep trench isolation (DTI) (DTI) may be disposed on the substrate 111 . The DTI may pass through the substrate 111 from the first surface 111B to the second surface 111F. The DTI disposed between the first pixel PX1 and the second pixel PX2 may extend from the first surface 111B toward the second surface 111F, but may be spaced apart from the second surface 111F. The DTI may include at least one of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, and a polysilicon film doped with impurities. The DTI may have one single-layer or multi-layer structure.

The DTI may separate the pixels, for example, the first pixel PX1 and the second pixel PX2 . The DTI may prevent cross-talk between the pixels, for example, the first pixel PX1 and the second pixel PX2 .

Photoelectric conversion elements PD1 and PD2 may be disposed in the substrate 111 . Each of the photoelectric conversion elements PD1 and PD2 may include a region doped with an impurity of a second conductivity type opposite to the first conductivity type. For example, the second conductivity type is N-type, and the impurities of the second conductivity type may include impurities such as phosphorus, arsenic, bismuth, and/or antimony. The photoelectric conversion elements PD11, PD12, PD21, and PD22 may be formed by forming a PN junction with a region doped with an impurity of the first conductivity type of the substrate 111 adjacent to a region doped with an impurity of the second conductivity type. there is.

The first surface 111B of the substrate 111 may be an incident surface of light, and light may be incident through the incident layer 112 and the first surface 111B. The incident layer 112 may include a micro lens ML and a color filter CF. In an embodiment, an anti-reflection layer AF may be disposed between the first surface 111B of the substrate 111 and the color filter CF. In some embodiments, the anti-reflection layer AF, the color filter CF, and the micro lens ML may be sequentially stacked and disposed on the first surface 110c of the semiconductor substrate 111 .

The color filter CF may transmit light of a specific spectrum band, that is, light of a specific color. A plurality of color filters CF may constitute a color filter array. In an embodiment, the color filter array may have a Bayer pattern. The plurality of color filters may include a red filter, a blue filter, and two green filters, wherein the red filter, the blue filter, and the two green filters are arranged in 2 X 2, wherein the two green filters are diagonally arranged. can be placed. In an embodiment, the plurality of color filters may include a red filter, a blue filter, a green filter, and a white filter arranged in a 2×2 configuration. However, the present invention is not limited thereto, and the plurality of color filters may include filters combined with different colors. For example, the plurality of color filters may include a yellow filter, a cyan filter, and a green filter.

A first color filter CF1 may be disposed on the first pixel PX1 , and a second color filter CF2 may be disposed on the second pixel PX2 . The first color filter CF1 and the second color filter CF2 may transmit light of the same color or different colors. A color detectable by the corresponding pixel (the first pixel PX1 or the second pixel PX2 ) may be determined according to the color of the light transmitted by the color filter CF.

A floating diffusion region, for example, the first floating diffusion regions FD1 and FD2 may be formed adjacent to the second surface 111F of the substrate 111 . The first floating diffusion regions FD1 and FD2 may be regions doped with impurities of the second conductivity type.

Gate terminals of transistors, for example, transfer gates TG1 and TG2 and gain control gates CGG1 and CGG2 may be formed in the wiring layer 113 adjacent to the second surface 111F of the substrate 111 . The transfer gates TG1 and TG2 and the gain control gates CGG1 and CGG2 may be gate terminals of the transfer transistors TX1 and TX2 in FIG. 3A and the gain control transistors CGX1 and CGX2 in FIG. 3A . .

The transfer gates TG1 and TG2 and the gain control gates CGG1 and CGG2 may be formed adjacent to the first floating diffusion regions FD1 and FD2. A well region WLL may be formed in the substrate 111 adjacent to the control gates CGG1 and CGG2 , and the well region WLL may be shared by the first pixel PX1 and the second pixel PX2 . there is. The well region WLL is a drain terminal of the gain control transistors CGX1 and CGX2 , and may also be the second floating diffusion regions FD12 and FD22 of the first pixel PX1 and the second pixel PX2 . In FIG. 7A , the second floating diffusion regions FD12 and FD22 of the first pixel PX1 and the second pixel PX2 may be connected to each other by sharing the well region WLL.

The wiring layer 113 may include multi-layered conductive lines 113 - 2 disposed in the interlayer insulating layer 113 - 1 . The conductive line 113 - 2 may transmit a control signal supplied to each transistor or a signal between the pixel and the outside. The conductive line 111 - 2 may be formed by patterning a conductive material including, for example, a metal material such as copper or aluminum, and may be formed in a first direction, such as an X-axis direction and a second direction, such as a Y-axis direction. can be extended to

Referring to FIG. 7B , well regions WLL1 and WLL2 may be formed adjacent to the control gates CGG1 and CGG2 in the substrate 111 , and the well regions WLL1 and WLL2 may include gain control transistors ( They may be drain terminals of CGX1 and CGX2 and may be second floating diffusion regions FD12 and FD22 of the first pixel PX1 and the second pixel PX2. The well regions WLL1 and WLL2 may be connected to each other through the contact CT and the conductive line 113 - 1 . As described above, the second floating diffusion regions FD12 and FD22 of the first pixel PX1 and the second pixel PX2 are formed through the contact CT and the conductive line 113 - 1 formed in the wiring layer 113 . can be connected to each other.

8 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8 , in the pixel array 110 , the first pixel PX1 is connected to the same column line CL and disposed in different rows, for example, first to fourth rows R1 , R2 , and R3 . , second floating diffusion nodes FD12 , FD22 , and FD32 of the second pixel PX2 and the third pixel PX3 may be electrically connected to each other. In the LCG mode, the gain control transistors CGS1 , CGS2 , and CGS3 are turned on, so that the first floating diffusion nodes FD11 , FD21 , FD31 and the second floating diffusion nodes FD12 , FD22 , FD32 are electrically connected can be connected to In the LCG mode, during the read operation of the first pixel PX1 , the operations of the first pixel PX1 and the second pixel PX2 are the same as those described with reference to FIGS. 4A and 4B , and the third pixel PX3 . The operation of is the same as that of the second pixel PX2 . The selection transistors SX1 , SX2 , and SX3 of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 are turned on to turn on the first pixel PX1 and the second pixel PX2 . and the third pixel PX3 may each output a pixel signal, and the pixel signals of the first pixel PX1 , the second pixel PX2 and the third pixel PX3 are averaged on the column line CL, The average pixel signal may be analog-digital converted by the ADC ( 141 of FIG. 1 ) to be converted into a pixel value for the first pixel PX1 .

Meanwhile, in FIG. 8 , the second floating diffusion nodes FD12 , FD22 , and FD32 of three pixels, for example, the first pixel PX1 , the second pixel PX2 and the third pixel PX3 are electrically connected to each other and , in the LCG mode, it has been described that each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 outputs a pixel signal when a read operation is performed on one pixel. it is not The second floating diffusion nodes of four or more pixels connected to the same column line CL are connected to each other, and when a read operation for one pixel is performed in the LCG mode, each of the four or more pixels outputs a pixel signal, , the pixel signals may be averaged.

9A shows an implementation example of a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 9B is a timing diagram of the pixel array of FIG. 9A .

9A is a modified example of the pixel array 110a of FIG. 3A . Accordingly, overlapping descriptions will be omitted and descriptions will be made focusing on differences.

Referring to FIG. 9A , the first pixel PX1 may further include a connection transistor CS connected between the second floating diffusion nodes F12 and FD22. The connection transistor CS may be turned on or off in response to the connection control signal CS provided from the row driver ( 120 of FIG. 1 ).

9B illustrates control signals applied to the first pixel PX and the second pixel PX in the read period RO of the first pixel PX1 in the LCG mode.

Referring to FIG. 9B , in the LCG mode, in response to the high-level connection signal CS and the gain control signals CGS1 and CGS2, the control transistor CX and the gain control transistors CGX1 and CGX2 are turn- can be come Accordingly, the floating diffusion nodes FD11 , FD12 , FD21 , and FD22 of the first pixel PX1 and the second pixel PX2 may be connected to each other and have the same voltage level.

In response to the high-level selection signals SEL1 and SEL2 , the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 may be turned on. Accordingly, each of the first pixel PX1 and the second pixel PX2 may output a pixel signal. The pixel signal of the first pixel PX1 and the pixel signal of the second pixel PX2 may be averaged on the column line CL.

10 illustrates a pixel array according to an exemplary embodiment of the present disclosure. The pixel array 110d of FIG. 10 may be applied as the pixel array 110 to the image sensor 100 of FIG. 1 .

Referring to FIG. 10 , the pixel array 110d may include a plurality of pixels PX arranged in a matrix. The plurality of pixels PX may be arranged in a plurality of rows and columns. For example, the plurality of pixels PX may be arranged in first to mth rows (R1 to Rm, m is a positive integer) and first to nth columns C1 to Cn.

Pixels PX disposed in at least two adjacent columns may be connected to the same column line CL. For example, the pixels PX disposed in the first column CL1 and the second column CL2 may be connected to the same column line CL. However, the present invention is not limited thereto, and pixels arranged in three or more columns may be connected to the same column line CL.

At least two pixels PX disposed in the same row and connected to the same column line CL may be electrically connected through an internal device. For example, as shown in FIG. 10 , two pixels PX disposed in the first column C1 and the second column C2 are connected, and the n−1th row Cn−1 and the n−th row Cn−1 and the second pixel PX are connected. Two pixels PX disposed in n rows Cn may be connected. In this way, each of the two pixels PX may be connected to share the floating diffusion nodes.

As described with reference to FIGS. 6A and 6B , a plurality of columns may be sequentially driven and a read operation may be sequentially performed on the plurality of columns. In the present embodiment, since the pixels PX arranged in two columns are connected to the same column, when a read operation is sequentially performed on a plurality of columns and a read operation is performed on one column, A read operation may be sequentially performed on the pixels PX arranged in two columns.

11 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure. 11 is an implementation example of the pixel array 110d of FIG. 10 . For convenience of description, two pixels PX1 and PX2 are illustrated.

Referring to FIG. 11 , the pixel array 110d may include a first pixel PX1 and a second pixel PX2 disposed in a first column C1 and a second column C2 , respectively. The first pixel PX1 and the second pixel PX2 may be connected to the same column line CL and may be internally connected to each other.

The first pixel PX1 includes a photoelectric conversion element PD1, and a plurality of transistors, for example, a transfer transistor TX1, a reset transistor RX1, a gain control transistor CGX1, a driving transistor DX1, and a selection transistor ( SX1) may be included.

The second pixel PX2 includes a photoelectric conversion element PD2 and a plurality of transistors, for example, a transfer transistor TX2, a reset transistor RX2, a gain control transistor CGX2, a driving transistor DX2, and a selection transistor ( SX2) may be included.

The second floating diffusion node FD22 of the second pixel PX2 may be connected to the second floating diffusion node FD12 of the first pixel PX1 . In an embodiment, as described with reference to FIG. 9A , the first pixel PX1 or the second pixel PX2 may further include a connection transistor CS, and the connection transistor CS is turned on in the LCG mode. - can be turned on

When the gain control transistor CGX1 of the first pixel PX1 and the gain control transistor CGX2 of the second pixel PX2 are turned on in the LCG mode, the first floating diffusion node FD11 of the first pixel PX1 ) and the second floating diffusion node FD12 , and the first floating diffusion node FD21 and the second floating diffusion node FD22 of the second pixel PX2 may be electrically connected to each other.

In the LCG mode, the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 are turned on, so that the first pixel PX1 and the second pixel PX2 receive pixel signals, respectively. may be output, the pixel signals of the first pixel PX1 and the second pixel PX2 may be averaged on the column line CL, and the average pixel signal may be analog-digital converted by the ADC ( 142 of FIG. 1 ) .

12 illustrates a pixel array according to an exemplary embodiment of the present disclosure. The pixel array 110e of FIG. 12 may be applied as the pixel array 110 to the image sensor 100 of FIG. 1 .

Referring to FIG. 12 , the pixel array 110e may include a plurality of pixels PX arranged in a matrix.

Pixels disposed in at least two adjacent columns may be connected to the same column line CL. For example, the pixels PX disposed in the first column CL1 and the second column CL2 may be connected to the same column line CL. However, the present invention is not limited thereto, and pixels arranged in three or more columns may be connected to the same column line CL.

At least four pixels PX disposed in at least two adjacent rows and connected to the same column line CL may be electrically connected through an internal device to share the floating diffusion nodes.

13 shows an implementation of a pixel array according to an exemplary embodiment of the present disclosure. 13 is an implementation example of the pixel array 110e of FIG. 12 . For convenience of description, two pixels PX1 and PX2 are illustrated.

Referring to FIG. 13 , the pixel array 110e includes first to fourth columns arranged in a first column C1 and a second column C2 , and a first row R1 and second row R2 in a matrix. It may include pixels PX1 to PX4. The first to fourth pixels PX1 to PX4 may be connected to the same column line CL and may be internally connected to each other.

Each of the first to fourth pixels PX1 to PX4 includes a photoelectric conversion element PD1, PD2, PD3, and PD4, and a plurality of transistors, for example, transfer transistors TX1, TX2, TX3, TX4, reset transistor RX1, RX2, RX3, RX4), gain control transistor (CGX1, CGX2, CGX3, CGX4), drive transistor (DX1, DX2, DX2, DX3, DX4), and select transistor (SX1, SX2, SX3, SX4) there is.

The second floating diffusion nodes FD12 , FD22 , FD32 , and FD42 of the first to fourth pixels PX1 to PX4 may be connected to each other. In an embodiment, as described with reference to FIG. 9A , each of the first to fourth pixels PX1 to PX4 may further include a connection transistor CS, and in the LCG mode, the connection transistor CS is turned- can be come

When the gain control transistors CGX1 , CGX2 , CGX3 , and CGX4 of the first to fourth pixels PX1 to PXP4 are turned on in the LCG mode, the first to fourth pixels PX1 to PXP4 first floating diffusion node The nodes FD11 , FD21 , FD31 , and FD41 and the second floating diffusion nodes FD12 , FD22 , FD32 , and FD42 may be electrically connected to each other.

In the LCG mode, the selection transistors SX1 , SX2 , SX3 , and SX4 of the first to fourth pixels PX1 to PX4 are turned on, so that each of the first to fourth pixels PX1 to PX4 outputs pixel signals The pixel signals of the first to fourth pixels PX1 to PX4 may be averaged on the column line CL, and the average pixel signal may be analog-digital converted by the ADC ( 142 of FIG. 1 ).

14A, 14B, and 14C illustrate color filters disposed in a pixel array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 14A , in the pixel array 110a, at least two pixels PX disposed in two adjacent rows and connected to the same column line CL may be electrically connected to each other. A blue color filter CF_B, two green color filters CF_R, and a red color filter CF_R may be disposed in four pixels PX arranged in a 2 X 2 matrix. A pattern PT of color filters arranged in four pixels PX arranged in a 2 X 2 matrix may be referred to as a Bayer pattern, and in the pixel array 110, the Bayer pattern may be repeated in a matrix. .

Referring to FIG. 14B , color filters of the same color may be disposed in four pixels PX arranged in a 2×2 matrix. In this case, color filters of the same color may be disposed in the two electrically connected pixels PX. For example, the blue color filter CF_B, the green color filter CF_R, and the red color filter CF_R may be respectively disposed in four pixels PX arranged in a 2×2 matrix. The green color filter CF_R may be disposed in a diagonal direction. The pattern PT of the color filters arranged in the 16 pixels PX arranged in a 4 X 4 matrix may be referred to as a tetra pattern, and in the pixel array 110 , the tetra pattern may be repeated in a matrix. .

Referring to FIG. 14C , at least three pixels PX disposed in three adjacent rows in the pixel array 110b and connected to the same column line CL may be electrically connected to each other. Color filters of the same color may be disposed in nine pixels PX arranged in a 3 X 3 matrix. In this case, color filters of the same color may be disposed in three electrically connected pixels PX. For example, the blue color filter CF_B, the green color filter CF_R, and the red color filter CF_R may be respectively disposed in nine pixels PX arranged in a 3×3 matrix. The green color filter CF_R may be disposed in a diagonal direction. A pattern PT of color filters arranged in 36 pixels PX arranged in a 6 X 6 matrix may be referred to as a nona pattern, and in the pixel array 110, the nona pattern may be repeated in a matrix. .

The arrangement of the blue color filter CF_B, the green color filter CF_R, and the red color filter CF_R in the pixel array has been described with reference to FIGS. 14A to 14C . However, the present invention is not limited thereto, and a color combination of the color filters may be variously changed. For example, a blue color filter CF_B, a green color filter CF_R, a red color filter CF_R, and a white color filter may be disposed in the pixel array. Alternatively, in an embodiment, a blue color filter CF_B, a yellow color filter CF_R, and a red color filter CF_R may be disposed in the pixel array.

15 is a block diagram of an electronic device including a multi-camera module. 16 is a detailed block diagram of the camera module of FIG. 15 .

Referring to FIG. 15 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. 15 shows an embodiment in which three camera modules 1100a, 1100b, and 1100c are disposed, but the embodiments are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 may be modified to include k (k is a natural number greater than or equal to 4) camera modules.

Hereinafter, a detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 16 , but the following description may be equally applied to other camera modules 1100a and 1100b according to an embodiment.

Referring to FIG. 16 , the camera module 1100b includes a prism 1105 , an optical path folding element (hereinafter, “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and storage. A unit 1150 may be included.

The prism 1105 may include the reflective surface 1107 of the light reflective material to change the path of the light L incident from the outside.

In some embodiments, the prism 1105 may change the path of the light L incident in the first direction X to the second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light reflective material in the A direction about the central axis 1106 or rotates the central axis 1106 in the B direction in the first direction (X). The path of the incident light L may be changed in the second vertical direction Y. At this time, the OPFE 1110 may also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

In some embodiments, as shown, the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction. However, embodiments are not limited thereto.

In some embodiments, the prism 1105 is movable in a positive (+) or negative (-) B direction around 20 degrees, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees, where the angle of movement is positive It can move at the same angle in the (+) or minus (-) B direction, or it can move to a nearly similar angle in the range of 1 degree or less.

In some embodiments, the prism 1105 may move the reflective surface 1106 of the light reflective material in a third direction (eg, the Z direction) parallel to the extension direction of the central axis 1106 .

The OPFE 1110 may include, for example, an optical lens consisting of m (here, m is a natural number) number of groups. The m lenses may move in the second direction Y to change an optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom magnification of the camera module 1100b is Z, when m optical lenses included in the OPFE 1110 are moved, the optical zoom magnification of the camera module 1100b is 3Z or 5Z or It can be changed to an optical zoom magnification of 5Z or higher.

The actuator 1130 may move the OPFE 1110 or an optical lens (hereinafter, referred to as an optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at a focal length of the optical lens for accurate sensing.

The image sensing device 1140 may include an image sensor 1142 , a control logic 1144 , and a memory 1146 . The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The pixel array described with reference to FIGS. 1 to 14B may be applied to the image sensor 1142 . A plurality of pixels connected to the same column line may be connected to each other, and in the LCG mode, the plurality of pixels may share floating diffusion nodes. When the pixel signal of one pixel among the plurality of pixels is read in the LCG mode, each of the plurality of pixels may output a pixel signal. Pixel signals output from the plurality of pixels may be averaged, and the average pixel signal may be analog-digital converted to generate a pixel value for a pixel to be read. Accordingly, noise, for example, PRNU due to a characteristic deviation of a driving transistor between pixels may be reduced. Accordingly, the image quality of the image generated in the LCG mode may be improved.

The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

The memory 1146 may store information necessary for the operation of the camera module 1100b, such as calibration data 1147 . The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using the light L provided from the outside. The calibration data 1147 may include, for example, information about a degree of rotation described above, information about a focal length, information about an optical axis, and the like. When the camera module 1100b is implemented in the form of a multi-state camera in which the focal length is changed according to the position of the optical lens, the calibration data 1147 is a focal length value for each position (or state) of the optical lens and Information related to auto focusing may be included.

The storage unit 1150 may store image data sensed by the image sensor 1142 . The storage unit 1150 may be disposed outside the image sensing device 1140 , and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140 .

In some embodiments, the storage unit 1150 may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but embodiments are not limited thereto. In some embodiments, the image sensor 1142 is configured as a pixel array, and the control logic 1144 may include an analog to digital converter and an image signal processing unit for processing a sensed image.

15 and 16 together, in some embodiments, each of the plurality of camera modules 1100a , 1100b , and 1100c may include an actuator 1130 . Accordingly, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

In some embodiments, one camera module (eg, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c is a folded lens including the prism 1105 and the OPFE 1110 described above. It is a camera module in the form of a camera module, and the remaining camera modules (eg, 1100a and 1100b) may be a vertical camera module in which the prism 1105 and the OPFE 1110 are not included, but embodiments are limited thereto. it is not going to be

In some embodiments, one camera module (eg, 1100c) of the plurality of camera modules 1100a, 1100b, and 1100c uses, for example, IR (Infrared Ray) to extract depth information. It may be a depth camera of the form. In this case, the application processor 1200 merges the image data provided from the depth camera and the image data provided from another camera module (eg, 1100a or 1100b) to obtain a 3D depth image. can create

In some embodiments, at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view (Field of View). In this case, for example, optical lenses of at least two camera modules (eg, 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but is not limited thereto.

Also, in some embodiments, a viewing angle of each of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other. For example, the camera module 1100a may be an ultrawide camera, the camera module 1100b may be a wide camera, and the camera module 1100c may be a tele camera, but is limited thereto not. In this case, the optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different, but is not limited thereto.

In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be disposed to be physically separated from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c do not divide and use the sensing area of one image sensor 1142, but an independent image inside each of the plurality of camera modules 1100a, 1100b, 1100c. A sensor 1142 may be disposed.

Referring back to FIG. 15 , the application processor 1200 may include an image processing device 1210 , a memory controller 1220 , and an internal memory 1230 . The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented separately as separate semiconductor chips.

The image processing apparatus 1210 may include a plurality of sub image processors 1212a , 1212b , and 1212c , an image generator 1214 , and a camera module controller 1216 .

The image processing apparatus 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c in a number corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

Image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through image signal lines ISLa, ISLb, and ISLc separated from each other. For example, image data generated from the camera module 1100a is provided to the sub-image processor 1212a through an image signal line ISLa, and image data generated from the camera module 1100b is an image signal line ISLb. The image data may be provided to the sub-image processor 1212b through , and image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on a Mobile Industry Processor Interface (MIPI), but embodiments are not limited thereto.

Meanwhile, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are not implemented separately from each other as shown, but are integrated into one sub-image processor, and the camera module 1100a and the camera module 1100c. After the image data provided from the is selected through a selection element (eg, a multiplexer) or the like, it may be provided to the integrated sub-image processor. In this case, the sub-image processor 1212b is not integrated and may receive image data from the camera module 1100b.

Also, in some embodiments, image data generated from the camera module 1100a is provided to the sub-image processor 1212a through an image signal line ISLa, and image data generated from the camera module 1100b is an image signal line The image data may be provided to the sub image processor 1212b through the ISLb, and image data generated from the camera module 1100c may be provided to the sub image processor 1212c through the image signal line ISLc. In addition, the image data processed by the sub-image processor 1212b is directly provided to the image generator 1214, but the image data processed by the sub-image processor 1212a and the image data processed by the sub-image processor 1212c are selected by the selection element. After any one is selected through (eg, a multiplexer), it may be provided to the image generator 1214 .

Each of the sub-image processors 1212a, 1212b, and 1212c performs bad pixel correction and 3A auto-focus correction (Auto-white balance) for image data provided from the camera modules 1100a, 1100b, and 1100c. , auto-exposure, noise reduction, sharpening, gamma control, remosaic, etc. image processing may be performed.

In some embodiments, remosaic signal processing may be performed in each of the camera modules 1100a, 1100b, and 1100c, and then provided to the sub-image processors 1212a, 1212b, and 1212c.

Image data processed by each of the sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214 . The image generator 1214 may generate an output image using image data provided from each of the sub-image processors 1212a, 1212b, and 1212c according to image generating information or a mode signal.

Specifically, the image generator 1214 merges at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to merge the output image. can create In addition, the image generator 1214 may generate an output image by selecting any one of image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal. .

In some embodiments, the image generation information may include a zoom signal or zoom factor. Also, in some embodiments, the mode signal may be, for example, a signal based on a mode selected by a user.

When the image generation information is a zoom signal (zoom factor), and each of the camera modules 1100a, 1100b, and 1100c has different viewing fields (viewing angles), the image generator 1214 operates differently depending on the type of zoom signal. can be performed. For example, when the zoom signal is the first signal, among the image data output from the sub-image processor 1212a and the image data output from the sub-image processor 1212c, the image data output from the sub-image processor 1212a; An output image may be generated using the image data output from the sub-image processor 1212b. If the zoom signal is a second signal different from the first signal, the image generator 1214 selects the sub image processor ( An output image may be generated using the image data output from the 1212c and the image data output from the sub-image processor 1212b. If the zoom signal is a third signal different from the first and second signals, the image generator 1214 does not perform the image data merging, but image data output from each of the sub image processors 1212a, 1212b, and 1212c You can select any one to create an output image. However, the embodiments are not limited thereto, and the method of processing image data may be modified and implemented as needed.

In some embodiments, the image processing apparatus 1210 may further include a selector that selects the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmits them to the image generator 1214. In the embodiment The selection unit may be implemented as a multiplexer, for example, a 3 X 1 multiplexer.

In this case, the selector may perform different operations according to the zoom signal or the zoom factor. For example, when the zoom signal is the fourth signal (eg, the zoom magnification is the first magnification), the selector selects one of the outputs of the sub-image processors 1212a, 1212b, and 1212c to select the image generator 1214 ) can be passed to

Also, when the zoom signal is a fifth signal different from the fourth signal (eg, the zoom magnification is the second magnification), the selector p (p is 2) among the outputs of the sub-image processors 1212a, 1212b, and 1212c The output of the above natural number) may be sequentially transmitted to the image generator 1214 . For example, the selector may sequentially transmit outputs of the sub-image processor 1212b and the sub-image processor 1212c to the image generator 1214 . Also, the selector may sequentially transmit outputs of the sub-image processor 1212a and the sub-image processor 1212b to the image generator 1214 . The image generator 1214 may generate one output image by merging the sequentially provided p outputs.

Here, image processing such as demosaic, downscaling to a video/preview resolution size, gamma correction, and high dynamic range (HDR) processing is performed by the sub image processors 1212a, 1212b, 1212c), the processed image data is transmitted to the image generator 1214 . Accordingly, even if the processed image data is provided to the image generator 1214 as one signal line through the selection unit 1213 , the image merging operation of the image generator 1214 may be performed at high speed.

In some embodiments, the image generator 1214 receives a plurality of image data having different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and performs high dynamic range (HDR) with respect to the plurality of image data. ) processing, it is possible to generate merged image data having an increased dynamic range.

The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. Control signals generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other.

Any one of the plurality of camera modules (1100a, 1100b, 1100c) is designated as a master camera (eg, 1100b) according to image generation information or a mode signal including a zoom signal, and the remaining camera modules (eg, For example, 1100a and 1100c may be designated as slave cameras. Such information may be included in the control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through the control signal lines CSLa, CSLb, and CSLc separated from each other.

A camera module operating as a master and a slave may be changed according to a zoom factor or an operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom factor, the camera module 1100b operates as a master, and the camera module 1100a is a slave can operate as Conversely, when the zoom factor indicates a high zoom magnification, the camera module 1100a may operate as a master and the camera module 1100b may operate as a slave.

In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b receiving such a sync enable signal generates a sync signal based on the received sync enable signal, and transmits the generated sync signal to the camera modules ( 1100a, 1100c) can be provided. The camera module 1100b and the camera modules 1100a and 1100c may be synchronized with the sync signal to transmit image data to the application processor 1200 .

In some embodiments, the control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in the first operation mode and the second operation mode in relation to the sensing speed.

The plurality of camera modules 1100a, 1100b, and 1100c generates an image signal at a first rate (eg, generates an image signal at a first frame rate) at a first speed in a first operation mode to generate the image signal at a second speed higher than the first speed. The encoding speed (eg, encoding an image signal of a second frame rate higher than the first frame rate) may be performed, and the encoded image signal may be transmitted to the application processor 1200 . In this case, the second speed may be 30 times or less of the first speed.

The application processor 1200 stores the received image signal, that is, the encoded image signal, in the memory 1230 provided therein or the storage 1400 external to the application processor 1200, and thereafter, the memory 1230 or the storage An image signal encoded from the 1400 may be read and decoded, and image data generated based on the decoded image signal may be displayed. For example, a corresponding subprocessor among the plurality of subprocessors 1212a , 1212b , and 1212c of the image processing apparatus 1210 may perform decoding, and may also perform image processing on the decoded image signal.

The plurality of camera modules 1100a, 1100b, and 1100c generate an image signal at a third rate lower than the first rate in the second operation mode (eg, an image signal of a third frame rate lower than the first frame rate) generated), and transmit the image signal to the application processor 1200 . The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 may perform image processing on the received image signal or store the image signal in the memory 1230 or the storage 1400 .

The PMIC 1300 may supply power, eg, a power supply voltage, to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300 supplies first power to the camera module 1100a through the power signal line PSLa under the control of the application processor 1200, and the camera module ( The second power may be supplied to 1100b) and the third power may be supplied to the camera module 1100c through the power signal line PSLc.

The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to the power control signal PCON from the application processor 1200, and also adjust the power level. . The power control signal PCON may include a power adjustment signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and in this case, the power control signal PCON may include information about a camera module operating in the low power mode and a set power level. Levels of powers provided to each of the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Also, the level of power can be changed dynamically.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and not used to limit the meaning or scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

100: image sensor 110, 110a, 110b, 110c, 110d: pixel array
120: low driver 140: analog-digital conversion circuit

Claims (20)

In the pixel array provided in the image sensor,
a first pixel including a first floating diffusion node and a first selection transistor for outputting a first pixel signal according to a voltage of the first floating diffusion node;
a second pixel including a second floating diffusion node and a second selection transistor for outputting a second pixel signal according to a voltage of the second floating diffusion node; and
a column line connected to the first selection transistor and the second selection transistor;
In the low conversion gain mode, the first floating diffusion node and the second floating diffusion node are electrically connected, and the first selection transistor and the second selection transistor are turned on to transmit the first pixel signal to the column line and outputting the second pixel signal. According to claim 1,
the first pixel is disposed in a first row of the pixel array;
and the second pixel is disposed in a second row closest to the first row in the pixel array. According to claim 1,
The first pixel is
a first photoelectric conversion element generating a first charge based on the light incident on the first pixel; and
Further comprising a first transfer transistor for transferring the charge generated by the first photoelectric conversion element to the first floating diffusion node,
The second pixel is
a second photoelectric conversion element generating a second charge based on the light incident on the second pixel; and
Further comprising a second transfer transistor for transferring the charge generated by the second photoelectric conversion element to the second floating diffusion node,
Storing the first charge in the first floating diffusion node and the second floating diffusion node by turning on the first transfer transistor among the first transfer transistor and the second transfer transistor in the first horizontal read period Characterized in a pixel array. According to claim 1,
The first pixel is
a first reset transistor to which a reset voltage is applied; and
a first gain control transistor connected in series between the first reset transistor and the first floating diffusion node;
The second pixel is
a second reset transistor to which the reset voltage is applied; and
a second gain control transistor coupled in series between the second reset transistor and the second floating diffusion node and coupled to the first gain control transistor;
and in the low conversion gain mode, the first gain control transistor and the second gain control transistor are turned on. 5. The method of claim 4,
and the first gain control transistor and the second gain control transistor are directly connected. The method of claim 4, wherein the first pixel comprises:
Further comprising a connection transistor connected between the first gain control transistor and the second gain control transistor,
and in the low conversion gain mode, the connecting transistor is turned on. The method of claim 1 , wherein
Each of the first pixel and the second pixel,
a plurality of photoelectric conversion elements; and
and a plurality of transfer transistors for transferring charges generated by a corresponding one of the plurality of photoelectric conversion elements to a corresponding one of the first and second floating diffusion nodes. According to claim 1,
In a first horizontal read period in which a pixel signal is read from the first pixel, the first pixel sequentially operates in the low conversion gain mode, the high conversion gain mode, and the low conversion gain mode;
In the high conversion gain mode, the first floating diffusion node and the second floating diffusion node are electrically separated, the first selection transistor is turned on, and the second selection transistor is turned off. , which is a pixel array. According to claim 1,
A third pixel comprising: a third floating diffusion node; and a third selection transistor for outputting a third pixel signal according to a voltage of the third floating diffusion node;
In the low conversion gain mode, the first floating diffusion node, the second floating diffusion node, and the third floating diffusion node are electrically connected to each other, and the first selection transistor, the second selection transistor, and the third selection transistor is turned on to output the first pixel signal, the second pixel signal, and the third pixel signal to the column line. The pixel array according to claim 1, wherein a color filter of the same color is disposed on the first pixel and the second pixel. In the pixel array provided in the image sensor,
a plurality of pixels arranged in a matrix; and
Each of the plurality of pixels includes a plurality of column lines commonly connected to pixels disposed in the same column,
Each of the plurality of pixels,
one or more photoelectric conversion elements for converting a received optical signal into electric charge;
one or more transfer transistors to transfer the charge to a first floating diffusion node;
a gain control transistor coupled between the first floating diffusion node and the second floating diffusion node;
a driving transistor configured to generate a pixel signal according to a voltage of the first floating diffusion node; and
a selection transistor connected to a corresponding one of the plurality of column lines and outputting the pixel signal to the corresponding column line;
In the low conversion gain mode, first floating diffusion nodes and second floating diffusion nodes of a first pixel and a second pixel connected to the same column line among the plurality of pixels are electrically connected, and the first pixel and the second pixel are electrically connected. A pixel array, wherein the select transistors of the pixel are turned on. 12. The pixel array of claim 11, wherein the first pixel and the second pixel are arranged in different rows and in the same column. 12. The pixel array of claim 11, wherein the first pixel and the second pixel are arranged in the same row and in different columns. 12. The method of claim 11,
In the low conversion gain mode, the first floating diffusion nodes and the second floating diffusion nodes of a third pixel and a fourth pixel connected to the same column line as the first pixel and the second pixel among the plurality of pixels are the and electrically connected to the first floating diffusion nodes and the second floating diffusion nodes of a first pixel and a second pixel, wherein select transistors of the third pixel and the fourth pixel are turned on. 15. The pixel array of claim 14, wherein the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in a 2 X 2 matrix. In the image sensor,
a pixel array including a plurality of pixels arranged in a matrix, wherein first and second pixels connected to a first column line are connected to each other;
drive the plurality of pixels, and in a row conversion mode, the floating diffusion node of the first pixel and the floating diffusion node of the second pixel are connected to each other, and the first pixel and the second pixel respectively output a pixel signal a row driver driving the first and second pixels; and
and an analog-to-digital conversion circuit for analog-to-digital conversion of a plurality of pixel signals output from a plurality of column lines of the pixel array. The image sensor of claim 16 , wherein the first pixel and the second pixel are disposed adjacent to each other in a column direction of the pixel array. 17. The method of claim 16, wherein each of the first pixel and the second pixel,
one or more photoelectric conversion elements for converting a received optical signal into electric charge;
one or more transfer transistors to transfer the charge to a first floating diffusion node;
a gain control transistor coupled between the first floating diffusion node and the second floating diffusion node;
a reset transistor providing a reset voltage to the first floating diffusion node and the second floating diffusion node;
a driving transistor configured to generate a pixel signal according to a voltage of the first floating diffusion node; and
and a selection transistor connected to the first column line and configured to output the pixel signal to the first column line. The method of claim 18, wherein the first pixel comprises:
and a connection transistor connected between a second floating diffusion node of the first pixel and a second floating diffusion node of the second pixel. The image sensor of claim 16 , wherein a color filter of the same color is disposed on the first pixel and the second pixel.

Images