JP2004007781A - Image pickup device and image pickup system using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of an image pickup device provided with a sensor block having a scanning section for selecting pixel sections and pixels and a signal processing block for processing the signal outputted from the sensor block. <P>SOLUTION: The image pickup device is integrated in a semiconductor substrate having a sensor block 1 comprising a pixel section 1a composed of a plurality of pixels each having a light receiving element, and scanning sections 1b and 1c for selecting the pixels in the pixel section 1a; and a signal processing block 2 for processing the signal outputted from the sensor block 1. The power supply voltage or the amplitude or high level of a clock signal used in the sensor block 1 is higher than the power supply voltage of the signal processing block 2. An image pickup system has this image pickup device and an optical system which forms an optical image in the sensor block of the device. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an imaging device having a sensor block having a photoelectric conversion function and a signal processing block for processing a signal from a pixel portion, and an imaging system using the same.

A pixel unit including a plurality of pixels each having a light receiving element such as a photodiode, a sensor block having a scanning unit for selecting a pixel in the pixel unit, and a signal processing unit for processing a signal output from the sensor block. There is an imaging device in which a signal processing block having an amplifier and the like are integrated on the same semiconductor substrate. Note that a sensor in which a pixel portion is formed by a CMOS manufacturing process is called a CMOS sensor.

In recent years, imaging devices with a wide dynamic range, a high S / N ratio, and low power consumption have been demanded due to the demand for digital cameras and the like.

Conventionally, a single power supply is used in an imaging device having a pixel block and a sensor block having a scanning unit for selecting a pixel, and a signal processing block for processing a signal output from the sensor block. When importance is placed on the signal processing block, the power supply voltage of the sensor block is lowered in accordance with the signal processing block, and as a result, the dynamic range is sacrificed.

On the other hand, a buried photodiode used for a CCD or the like can obtain a signal having a high S / N ratio, but generally has a high power supply voltage and causes an increase in clock noise of a signal processing block. In addition, when the power supply voltage increases, the electric field applied to the insulated gate transistor represented by each MOS transistor in the signal processing block increases, and the impact ionization phenomenon easily occurs. When the pixel portion is a buried photodiode, this noise is likely to occur because the power supply voltage is high.

In addition, when the same power supply voltage as that of the sensor block is used for the signal processing block, the use of a high power supply voltage for the signal processing block causes an increase in power consumption.

An object of the present invention is to provide an imaging device and an imaging system that can reduce power consumption.

In order to achieve the above object, the present invention provides a pixel unit including a plurality of pixels each having a light receiving element for each pixel, a sensor block including a scanning unit for selecting a pixel of the pixel unit, and a sensor block. A signal processing block for processing the output signal; and a unit for setting the amplitude or high level of a power supply voltage or a clock signal used in the sensor block to be higher than the power supply voltage of the signal processing block. An imaging device integrated on a semiconductor substrate and an imaging system using the same are provided.

As described above, according to the present invention, an imaging device and an imaging system with low power consumption can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of an imaging device integrated in the same semiconductor substrate. As shown in FIG. 1, the imaging apparatus has a sensor block 1 and a signal processing block 2. The sensor block 1 includes a pixel unit 1a, a vertical scanning unit 1b that scans the pixel unit 1a in the vertical direction, and a horizontal scanning unit 1c that scans the pixel unit 1a in the horizontal direction. The signal processing block 2 includes an amplifier unit 2a including an automatic gain control and the like, an A / D (analog / digital) conversion circuit 2b, and a signal processing unit 2c that processes signals from the A / D conversion circuit 2b. ing.

FIG. 2 is a schematic configuration diagram showing a configuration of one pixel of the pixel unit. FIG. 7 is a schematic configuration diagram showing another configuration of one pixel of the pixel portion. In FIG. 1, PD is a buried photodiode, TX is a transfer MOS transistor that transfers signal charges from the buried photodiode PD, and FD is a floating diffusion (charge-to-voltage converter) that holds the transferred signal charges. .), SF is an amplification MOS transistor whose gate is connected to the FD, SEL is a selection MOS transistor, and RES is a reset MOS transistor for resetting the FD and the amplification MOS transistor SF. The selection MOS transistor SEL forms a source follower circuit with the MOS transistor M forming a constant current source. FIG. 7 shows a configuration example when the arrangement of the selection MOS transistor SEL and the amplification MOS transistor SF is changed.

When a buried photodiode is used as the light receiving element in the pixel portion, the buried photodiode is depleted and the accumulated charge is transferred to the FD (floating diffusion) in the pixel. It is required to set the FD to be equal to or higher than the depletion voltage. As a result, the power supply voltage needs to be 5 V (volt) or more.

In this example, the power supply voltage of the sensor block 1 was 5 V, and the power supply voltage of the signal processing block 2 was 4 V.

Hereinafter, the embedded photodiode will be described with reference to FIG.

As shown in FIG. 3, the buried photodiode includes an n-type region 12 formed in a p-well 11 and ap ⁺ -type region 14 formed on a substrate surface of the n-type region 12.

The charges accumulated in the n-type region 12 can be transferred to the floating diffusion region (n ⁺ -type region) 13 when a voltage is applied to the gate electrode 15. In embedded photodiode reverse bias the junction between the junction and the p-well 11 and the n-type region 12 and p ⁺ -type region 14 and the n-type region 12 is applied, the n-type region 12, p ⁺ -type region A depletion layer (dotted line in the figure) spreads from the junction between 14 and n-type region 12, and a depletion layer (dotted line in the figure) spread from the junction between p-well 11 and n-type region 12. When the depletion layers come into contact with each other and the voltage (VFD) of the floating diffusion region 13 is made higher than the depletion voltage (Vdep) at that time (VFD> Vdep), the electric charge accumulated in the n-type region 12 is reduced. All can be transferred to the floating diffusion region (n ⁺ type region) 13.

As shown in FIG. 4, the signal processing unit 2c includes a Y / C separation circuit 112a, a luminance signal processing circuit 112b, a color signal processing circuit 112c, a color suppression circuit 112d, a digital output conversion circuit 112e, and a microcomputer 115. .

The microcomputer controls the Y / C separation circuit 112a and the like, receives a luminance signal and a chrominance signal, and performs focus adjustment, exposure control, and the like based on the received signals.

When the power supply voltage of the sensor block is set to 5 V and the power supply voltage of the signal processing block is reduced from 5 V to 4 V, the clock noise becomes 4/5 because it is proportional to the amplitude. In addition, since the power consumption of the digital circuit is represented by ・ · f · C · V ² , when the power supply voltage becomes 4/5, the power consumption is reduced to 64%. On the other hand, the power consumption of an analog circuit represented by an amplifier is represented by I · V, and the through current I does not change unless the form is changed. Therefore, the power consumption is reduced to 4/5 according to the decrease in the power supply voltage. Decrease.

In an imaging device that outputs only a sensor output, the power consumption of a logic circuit is very small, and since most of the circuit is an analog circuit, the power consumption is only about 80%. However, in an imaging device equipped with a large-scale digital signal processing, a digital circuit is used. Power consumption occupies a large proportion, so the reduction in power consumption is greater.

Further, in the case of an image pickup apparatus having a pixel having a buried photodiode as shown in FIG. 3 shown in the above-described embodiment, the present embodiment particularly improves the S / N ratio as compared with the conventional one, This has an effect of reducing power consumption and the like, but the configuration of the pixel is not limited to this, and another pixel structure having a function of converting an optical signal into electric charge and outputting the electric charge may be used.

Next, a specific circuit configuration for making the power supply voltage of the sensor block different from that of the signal processing block will be described with reference to FIG.

5 In FIG. 5, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. Reference numeral 100 denotes an imaging device in which the sensor block 1 and the signal processing block 2 are integrated on the same semiconductor substrate, and provided with voltage supply terminals 5a and 5b for applying power supply voltages having different voltage values to the sensor block and the signal processing block. ing. The vertical scanning unit 1b includes a vertical shift register 1f, an AND circuit, and pulse supply lines 1h to 1j. The AND circuit 1g switches a transistor when a pulse is input from the vertical shift register and the pulse supply line. A pulse for turning on is output. The horizontal scanning unit 1c includes a horizontal shift register 1k, an AND circuit 1g, and a pulse supply line 11. The AND circuit 1g turns on the transistor when a pulse is input from the horizontal shift register and the pulse supply line. Is output.

(4) The voltage from the voltage supply unit 3 is set to 5V and 4V by the step-down circuits 4a and 4b, respectively. The voltage applied to the voltage supply terminal 5a is transmitted through the voltage supply line 6a, and the voltage applied to the voltage supply terminal 5b is transmitted through the voltage supply line 6b.

In this embodiment, the voltage of the voltage supply line 6a is supplied as the power supply voltage from the drain of the amplification MOS transistor of each pixel, and is supplied as the reset voltage from the reset MOS transistor. Further, the voltage of the voltage supply line 6a is configured to be a driving voltage of the AND circuit 1g, and the AND circuit outputs a pulse of 5V which is the voltage of the voltage supply line 6a.

(4) The voltage of the voltage supply line 6b is configured to be supplied as the power supply voltage of the amplifier 2a, the A / D converter 2b, and the signal processor 2c in the signal processing block.

(Second embodiment)
FIG. 6 shows a specific circuit configuration for making the power supply voltages of the sensor block and the signal processing block different.

The second embodiment is different from the first embodiment in that a voltage supply terminal 5c for supplying a voltage is provided and a step-down circuit 4d is provided in the imaging device 100, so that the voltage supply line 6c The point is that the value of the supplied voltage is reduced to be the power supply voltage of the amplifier unit and the like included in the signal processing unit. The other points are the same as in the first embodiment.

(5) The voltage from the voltage supply unit is set to 5 V by the step-down circuit 4c, and a voltage of 5 V is applied to the sensor block by the voltage supply line 6c. Further, the voltage value of 5V of the voltage supply line 6c is set to 4V by the step-down circuit 4d and is applied to the signal processing block.

In the first and second embodiments described above, the power supply voltage of the same voltage value is used for each circuit unit in the signal processing block. For example, the power supply voltage of the sensor block is 6.5 V, and the signal processing block is , The A / D converter of the signal processing block and the signal processing unit may have a configuration of 3.3V.

As a specific circuit configuration, three voltage supply terminals may be provided, and different voltages may be applied from the respective terminals. Alternatively, by providing one voltage supply terminal and providing two step-down circuits in the imaging device, A configuration in which three different voltages are formed may be employed.

In the case of an image pickup apparatus having a pixel having a diode, the present embodiment has an effect of improving the S / N ratio and reducing the power consumption as compared with the conventional apparatus, but the configuration of the pixel is not limited to this. Instead, another pixel structure having a function of converting an optical signal into a charge and outputting the charge may be used.

(Third embodiment)
In the first and second embodiments, the power supply voltage of 5 V is supplied to the entire sensor block. In the present embodiment, a high voltage of 6.5 V is applied only to the reset signal line and the row selection signal line of the pixel portion of the sensor block shown in FIG. And a power supply voltage of 5.0 V was supplied to the other components of the sensor block. In this embodiment, the dynamic range can be expanded by applying a high voltage of 6.5 V to the gates of the selection transistor SEL and the reset transistor RES. Note that a similar effect can be obtained with the pixel configuration of FIG.

(4) When the readout circuit of the sensor block is constituted by, for example, a source follower circuit as shown in FIG. 7, one factor for determining the dynamic range of the sensor is the upper limit of the source follower circuit. The upper limit is generally the power supply voltage Vdd, but when the same voltage Vdd is applied to the gate of the selection transistor SEL, the upper limit is a voltage further lower than the power supply voltage Vdd by the threshold voltage of the selection transistor SEL. By applying a voltage higher than the power supply voltage Vdd to the gate voltage of the selection transistor SEL, the upper limit of the source follower circuit can be raised to the power supply voltage Vdd. For this reason, in the present embodiment, a voltage of 6.5 V was supplied to the row selection signal line of the pixel portion of the sensor block connected to the gate of the selection transistor SEL.

Another factor that suppresses the dynamic range is the upper limit of the reset voltage. The input range of the source follower circuit ranges from the reset voltage to GND. Therefore, the dynamic range can be expanded by increasing the reset voltage. When the same voltage as the reset voltage is applied to the gate of the reset transistor RES similarly to the selection transistor SEL, the reset voltage can be reset only by a voltage lower than the reset power supply by the threshold voltage. In order to improve this, by inputting a sufficiently high voltage to the gate voltage of the reset transistor RES, the reset can be performed at a voltage substantially equal to the reset voltage. For this reason, in the present embodiment, a voltage of 6.5 V was supplied to the reset signal line of the pixel portion of the sensor block connected to the gate of the reset transistor RES.

FIG. 8 is a specific circuit configuration diagram in which a voltage of 6.5 V is supplied only to the reset signal line and the row selection signal line and a voltage of 5.0 V is supplied to other components of the sensor block. Show.

In the present embodiment, the voltage from the voltage supply unit 3 is set to 5 V by the step-down circuit 4c and applied to the voltage supply terminal 5c. The voltage of the voltage supply line 6c set to 5V as it is is supplied as a power supply voltage to the drain of the selection MOS transistor, and is also supplied as a drive voltage for the AND circuit 1g. The voltage raised to 6.5V by the booster circuit 4e is supplied to the AND circuit 1g ', and the voltage raised to 3.3V by the voltage lowering circuit 4d is supplied to each component in the signal processing block as a power supply voltage. Supplied.

(Fourth embodiment)
In the first to third embodiments, the power supply voltage of the sensor block is set higher than the power supply voltage of the signal processing block. However, in the present embodiment, the power supply voltage of the sensor block and the signal processing block is set to be the same and used in the sensor block. In this configuration, the high level of the clock signal is higher than the power supply voltage of the signal processing block.

(4) A specific circuit configuration diagram will be described with reference to FIG.

(4) The voltage from the voltage supply unit 3 is set to 3.3 V by the step-down circuit 4c and supplied from the voltage supply terminal 5c. The voltage of the voltage supply line set to 3.3 V is supplied as a power supply voltage to the drain of the amplifying MOS transistor, and is also supplied as a reset voltage to the drain of the reset MOS transistor. In addition, it is also supplied as a power supply voltage of each component of the signal processing block.

In this embodiment, a booster circuit is provided in the imaging device. Thus, the voltage of the voltage supply line is set to 5 V by the booster circuit 4e, and this voltage is used as the drive voltage of the AND circuit 1g.

With the above configuration, the clock signal output from the AND circuit 1g has a high level of 5 V, which is higher than the power supply voltage of the signal processing block.

(Fifth embodiment)
In the first to third embodiments, the power supply voltage of the sensor block is set higher than the power supply voltage of the signal processing block. However, in the present embodiment, the power supply voltage of the sensor block and the signal processing block is set to be the same and used in the sensor block. In this configuration, the amplitude of the clock signal is higher than the power supply voltage of the signal processing block.

(4) A specific circuit configuration diagram will be described with reference to FIG.

(4) The voltage from the voltage supply unit 3 is set to 3.3 V by the step-down circuit 4c and supplied from the voltage supply terminal 5c. The voltage of the voltage supply line set to 3.3 V is supplied as a power supply voltage to the drain of the amplifying MOS transistor, and is also supplied as a reset voltage to the drain of the reset MOS transistor. In addition, it is also supplied as a power supply voltage of each component of the signal processing block.

In this embodiment, two step-down circuits are provided in the imaging device. Thereby, the voltage of the voltage supply line is set to -2 V by the step-down circuit 4f, and this voltage is used as the drive voltage of the AND circuit 1g. The voltage of the voltage supply line is set to 3 V by the step-down circuit 4g, and this voltage is used as the drive voltage of the AND circuit 1g.

With the above configuration, the amplitude of the clock signal output from the AND circuit 1g is 5 V, which is higher than the power supply voltage of the signal processing block.

(Sixth embodiment)
The power supply voltage of the sensor block 1 was 6.5 V, and the power supply voltage of the signal processing block 2 was 3.3 V. In this embodiment, since there is a difference in the power supply voltage between the sensor block 1 and the signal processing block 2, as shown in FIG. 11, a level shift circuit 1d for level-shifting the signal from the horizontal scanning unit 1c is provided. The output of the level shift circuit 1d was connected to the amplifier 2a. Note that the level shift circuit does not necessarily need to be provided in the sensor block 1, and may be provided between the sensor block 1 and the signal processing block 2 or in the signal processing block 2. However, the degree of freedom in design is higher when the power supply voltage is higher and the sensor block has a wider input range and output range.

As a simple configuration example, the level shift circuit can be configured by a source follower circuit including a MOS transistor and a constant current source as shown in FIG. 12, for example. A specific configuration for making the power supply voltage of the sensor block higher than the power supply voltage of the signal processing block can be achieved by configuring as in the first to third embodiments. The high level or the amplitude of the clock signal used in the sensor block can be made higher than the power supply voltage of the signal processing block by configuring as in the fourth and fifth embodiments.

(Seventh embodiment)
In the sixth embodiment, the power supply voltage of the sensor block is set to 6.5 V, and the power supply voltage of the signal processing block is set to 3.3 V. In this case, in order to increase the withstand voltage of the MOS transistor used in the sensor block, the power supply voltage of the signal processing block is increased. The thickness of the gate oxide film of the MOS transistor was made thicker or the well concentration was lowered as compared with the MOS transistor used. It is also possible to control both the gate oxide film thickness and the well concentration. The threshold voltage of the MOS transistor used in the sensor block having a thick gate oxide film becomes higher than the threshold voltage of the MOS transistor used in the signal processing block.

Specifically, the breakdown voltage of the MOS transistor used in the sensor block was increased by setting the oxide film thickness of the MOS transistor used in the sensor block to 20 nm and the oxide film thickness of the MOS transistor used in the signal processing block to 8 nm. .

Also, by setting the well concentration of the MOS transistor used in the sensor block to 4 × 10 ¹⁶ / cm ³ and the well concentration of the MOS transistor used in the signal processing block to 8 × 10 ¹⁶ / cm ³ , the sensor block is similarly formed. The breakdown voltage of the MOS transistor used could be increased.

Also, in the first to third embodiments, the breakdown voltage of the MOS transistor used in the sensor block may be increased.

The configurations of the sensor block and the signal processing block according to the present invention are not particularly limited to those of the above-described embodiments.

For example, as shown in FIG. 13, the configuration of the signal processing block may include only the amplifier unit 2a, and the sensor block reads a noise signal and includes the noise signal in the sensor signal as described below. Means for subtracting noise components may be provided.

FIG. 14 shows a circuit configuration for removing a noise component from a sensor signal from each pixel. The configuration of one pixel shown in FIG. 14 is the same as that shown in FIG.

As shown in FIG. 14, a MOS transistor MN for transferring a noise signal and a MOS transistor MS for transferring a sensor signal are connected to a vertical output line to which a plurality of pixels are connected, and accumulate the noise signal and the sensor signal, respectively. The data is stored in the capacitors CN and CS. The noise signal and the sensor signal stored in the storage capacitors CN and CS are subjected to the difference processing by the subtracter A to output a sensor signal from which the noise component has been removed. In an area sensor in which pixels are arranged in a matrix, MOS transistors MN and MS and storage capacitors CN and CS are provided for each vertical output line. The difference processing is performed by sequentially transmitting the signal to the subtracter A for each vertical output line.

Note that φTX, φRES, φSEL, φN, and φS are respectively a pulse signal for controlling the transfer MOS transistor TX, a pulse signal for controlling the reset MOS transistor RES, a pulse signal for controlling the selection MOS transistor SEL, and a noise signal transfer. A pulse signal for controlling the use MOS transistor MN and a pulse signal for controlling the sensor signal transfer MOS transistor MS.

FIG. 15 is a timing chart illustrating the operation of the circuit of FIG. First, φRES is set to a high level to reset the floating diffusion region (FD). Thereafter, φN is set to a high level to transfer a noise signal to the storage capacitor CN. Next, the signal charge is transferred from the photodiode PD to the floating diffusion region by setting φTX to the high level, and the sensor signal (including noise component) is transferred to the storage capacitor CS by setting φS to the high level. Thus, the noise signal and the sensor signal stored in the storage capacitors CN and CS are subjected to the difference processing by the subtractor A, and the sensor signal from which the noise component has been removed is output.

(Eighth embodiment)
FIG. 16 is a block diagram illustrating an imaging system using the imaging device 100 described above.

16, reference numeral 101 denotes a lens system; 102, a stop; 103, 105, and 107 motors; 104, a variable-magnification lens driving unit that controls the motor 103; and 106, a stop that controls the motor 105 to drive the stop 102. A mechanism driving unit 108 is a focus competition lens driving unit that controls the motor 107. An imaging apparatus 100 photoelectrically converts an optical signal incident from the lens system 101 and performs predetermined signal processing.

The variable magnification lens driving unit 104, the aperture mechanism driving unit 106, and the focus compensation lens driving unit 108 are controlled by a microcomputer 115 in the imaging apparatus.

The output from the image pickup device 100 is sent to the monitor means 114 through the digital decoder and the DA converter 113 to be displayed as an image, and is sent to the VTR.

(Ninth embodiment)
FIG. 17 is a block diagram illustrating an imaging system using the imaging device 100 in which the signal processing block described above includes only an amplifier unit.

17, reference numeral 101 denotes a lens system, 102 denotes an aperture, 103, 105, and 107 motors, 104 denotes a variable-magnification lens driving unit that controls the motor 103, and 106 denotes an aperture that controls the motor 105 to drive the aperture 102. A mechanism driving unit 108 is a focus competition lens driving unit that controls the motor 107. An imaging apparatus 100 photoelectrically converts an optical signal incident from the lens system 101, amplifies the signal, and outputs the amplified signal. Reference numeral 111 denotes an AD converter.

Reference numeral 112 denotes a camera signal processing circuit, which is a signal processing unit 2c in this embodiment. Reference numeral 112a denotes a Y / C separation circuit; 112b, a luminance signal processing circuit; 112c, a color signal processing circuit; 112d, a color suppression circuit; Is a digital output conversion circuit. The luminance signal and the color signal are input to the microcomputer 115, and the microcomputer 115 controls the variable-magnification lens driving unit 104, the aperture mechanism driving unit 106, and the focus compensating lens driving unit 108 based on these signals.

(4) The output from the camera signal processing circuit 112 is sent to the monitor means 114 through the digital decoder and the DA converter 113 to be displayed as an image and sent to the VTR.

In the above embodiment, the area sensor has been described, but the present invention can be applied to a line sensor. In the case of a line sensor, the pixel configuration is the same except that the selection switch is omitted in the pixel.

As described above, according to this embodiment, the dynamic range can be increased, noise can be reduced, and power consumption can be reduced.

In the first to eighth embodiments, the power consumption can be particularly reduced by integrating the sensor block and the signal processing block in the same semiconductor substrate by the CMOS process.

It is a figure showing an imaging device. It is a figure showing a pixel. It is a figure showing a pixel. It is a figure showing a signal processing part. It is a figure showing the 1st Example. It is a figure showing the 2nd Example. It is a figure showing a pixel. It is a figure showing the 3rd Example. It is a figure showing the 4th Example. It is a figure showing the 5th Example. It is a figure showing an imaging device. It is a figure showing an imaging device. It is a figure showing an imaging device. It is a figure showing a pixel part. FIG. 4 is a diagram illustrating a timing chart illustrating pixel reading. It is a figure showing an imaging system. It is a figure showing an imaging system.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Sensor block 2 Signal processing block 1a Pixel part 1b Vertical scanning part 1c Horizontal scanning part 1d Level shift circuit 1f Vertical shift register 1g AND circuit 1h-1j Pulse supply line 1k Horizontal shift register 11l Pulse supply line 2a Amplifier part 2b A / D (Analog / Digital) conversion circuit 2c Signal processing unit 3 Voltage supply unit 4a to d, 4f, 4g Step-down circuit 4e Step-up circuit 5a, 5b, 5c Voltage supply terminal 6a, 6b, 6c Voltage supply line 100 Image pickup device

Claims (10)

A pixel unit including a plurality of pixels having a light receiving element for each pixel, a sensor block including a scanning unit for selecting a pixel of the pixel unit,
A signal processing block for processing a signal output from the sensor block,
Means for making the power supply voltage or the amplitude or the high level of the clock signal used in the sensor block higher than the power supply voltage of the signal processing block, integrated in the same semiconductor substrate. 2. The imaging device according to claim 1, wherein a gate insulating film thickness of at least a part of the insulated gate transistor of the sensor block is larger than a gate insulating film thickness of the insulated gate transistor used in the signal processing block. An imaging device characterized by the following. 2. The imaging apparatus according to claim 1, wherein a well concentration of at least a part of the insulated gate transistor of the sensor block is lower than a well concentration of the insulated gate transistor used in the signal processing block. apparatus. 2. The imaging apparatus according to claim 1, wherein a threshold voltage of at least a part of the insulated gate transistor of the sensor block is higher than a threshold voltage of the insulated gate transistor used in the signal processing block. apparatus. The imaging device according to claim 1, wherein the light receiving element is a buried photodiode. The imaging device according to claim 5, wherein the pixel has a charge-voltage converter, and is connected to the embedded photodiode via a transfer switch. 2. The imaging device according to claim 1, wherein the sensor block and the signal processing block shift a signal level by level and are connected via each level shift unit. 2. The imaging apparatus according to claim 1, wherein the signal processing block includes an A / D conversion circuit for converting an analog signal into a digital signal. 9. The imaging device according to claim 8, wherein the signal processing block includes signal processing means for forming a luminance signal and a chrominance signal. An imaging system, comprising: the imaging device according to claim 1; and an optical system that forms light on a sensor block of the imaging device.

Images