JP3592107B2 - Solid-state imaging device and camera - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging deviceAnd cameraIn particular, a solid-state imaging device including a photoelectric conversion unit, and a charge-voltage conversion unit that converts a signal charge transferred from the photoelectric conversion unit into a signal voltageAnd cameraAbout.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a solid-state imaging device, to expand the dynamic range, for example, two types of signals having different accumulation times are read from the same pixel, and the two types of signals are combined to expand the dynamic range. There is a method of expanding the dynamic range by combining a signal having a high sensitivity but a small dynamic range and a signal having a low sensitivity but a large dynamic range.
[0003]
[Problems to be solved by the invention]
However, in the above method, after accumulating signal charges for a certain accumulation time, it is necessary to again accumulate signal charges by changing the accumulation time, so that the obtained signal is an image signal in a different accumulation period. .
[0004]
An object of the present invention is to provide a solid-state imaging device capable of changing sensitivity in accordance with signal charges stored in a photoelectric conversion unit.And cameraIs provided.
[0005]
[Means for Solving the Problems]
A solid-state imaging device according to an embodiment of the present invention includes a plurality of pixels each including a photoelectric conversion unit and a charge-voltage conversion unit configured to convert a signal charge transferred from the photoelectric conversion unit into a signal voltage in a first semiconductor region of one conductivity type. A solid-state imaging device having
The charge-voltage converter includes an impurity diffusion region of a conductivity type opposite to the one conductivity type formed in the first semiconductor region, and an impurity diffusion region of the opposite conductivity type embedded in the first semiconductor region. A buried semiconductor region,
The one conductivity type second semiconductor region is formed on the buried semiconductor region, and the buried semiconductor region and the first and second semiconductor regions constitute a junction.
The impurity diffusion region and the buried semiconductor region are adjacent and in contact with each other;
The charge-voltage converter has a capacitance formed in the impurity diffusion region and a capacitance formed in the buried semiconductor region that depends on a depletion layer width changed by a reverse bias voltage applied to the junction. It is characterized by the following.
[0014]
The camera of the present inventionOf the present inventionSolid-state imaging deviceA lens system that forms an image of light on the solid-state imaging device, an AD converter that converts a signal from the solid-state imaging device into a digital signal, and a signal processing circuit that processes a signal from the AD converter. It is characterized by having.
[0015]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic diagram illustrating the configuration of a solid-state imaging device according to the present invention. In FIG. 1, 1 is an N-type semiconductor substrate, 2 is a P-type well region formed on the N-type semiconductor substrate 1, 3 is an N-type diffusion region, and 4 is a P-type formed on the surface of the N-type diffusion region 3. A P-type well region 2, an N-type diffusion region 3, and a P-type region 4 constitute a photodiode. Reference numeral 5 denotes a charge-to-voltage converter for transferring the signal charges stored in the photodiode. This charge-to-voltage converter comprises an impurity diffusion region or the like, and the voltage conversion is achieved with all the capacitors connected to this node. You. Generally, it is an area generally called a floating diffusion (FD) area including all the capacitance components.
[0016]
Reference numeral 6 denotes a transfer gate electrode for transferring signal charges from the photodiode to the FD region 5. The N-type diffusion region 3 and the FD region 5 also serve as source / drain regions of a transfer MOS transistor (MTX). The FD region 5 is electrically connected to the gate of the output MOS transistor MSF and the drain of the reset MOS transistor MRES. The drain of the MOS transistor MSF is connected to the source of the MOS transistor MSEL serving as a selection switch, and the source is connected to a constant current source, forming a source follower circuit. The signal charge transferred to the FD region 5 is applied as a voltage signal to the gate of the MOS transistor MSF, and a signal is output from the source follower circuit. The FD region 5 is set to a reset potential when the reset MOS transistor MRES is turned on.
[0017]
The FD region 5 has a capacitance due to a junction capacitance with the P-type well region 2, a capacitance between wirings, and the like. As shown in FIG. 2, MOS components 7 and 8 are connected in series to the FD region 5, and a MOS capacitance is connected to the capacitance of the FD region 5. Here, the MOS capacitors are connected in series, but may be connected in parallel.
[0018]
The FD region 5 and the MOS components 7 and 8 constitute a charge-to-voltage converter. The MOS components 7 and 8 adjust the well concentration, the thickness of the gate oxide, the fixed voltage applied to the gate electrode, and the like to adjust the capacitance. Has a different voltage dependency from the FD region. Note that the capacitance formed by the junction capacitance between the FD region 5 and the P-type well region 2, the capacitance between wirings, and the like actually has voltage dependence, but the change in the capacitance is small in the range of use.
[0019]
FIGS. 3A to 3C are explanatory diagrams of the operation when the FD region and the MOS component have a step-like potential structure. FIG. 4A is a diagram showing a characteristic of VFD (floating diffusion voltage) -Q (signal charge amount), FIG. 4B is a diagram showing a characteristic of VFD-Cap (capacitance), and FIG. FIG. 4 is a diagram showing a light quantity-output characteristic (sensitivity characteristic). 4 (a) and 4 (b), a, b, and c show the characteristics of the operation states of FIGS. 3 (a), (b), and (c), respectively. Such a potential structure can be configured by connecting MOS capacitors in series or in parallel.
[0020]
In FIG. 3, PD denotes a photodiode unit, TX denotes a transfer MOS transistor unit, FD denotes a floating diffusion unit, MOS1 denotes a first MOS component, and MOS2 denotes a second MOS component. 3A to 3C, the transfer MOS transistor is turned on, the energy level falls below the level of the photodiode PD, and all the charges accumulated in the PD can be transferred to the FD region. The potential of the FD region is reset to VDD-Vth (Vth is a source-drain voltage drop by the transfer MOS transistor) by a reset MOS transistor MRES (not shown).
[0021]
When a step-like potential structure (FD section, MOS component section) is formed, as shown in FIG. 3A, when signal charges accumulated in the photodiode section (PD) are small (light quantity is small), the potential is low. The signal charge is transferred to the deep part of the well. At this time, the floating diffusion voltage VFD is high, the signal charge amount Q to be stored is small (FIG. 4A), the capacitance Cap is small (FIG. 4B), the output change rate with respect to the light amount is large, and the sensitivity is low. (FIG. 4C).
[0022]
Then, as shown in FIGS. 3 (b) and 3 (c), as the signal charges accumulated in the photodiode unit (PD) increase, the step-like potential of the MOS component units (MOS1, MOS2) increases. The signal charges are transferred stepwise also to a shallow portion. At this time, the floating diffusion voltage VFD decreases, the signal charge amount Q to be stored increases (FIG. 4A), the capacitance Cap increases stepwise (FIG. 4B), and the output with respect to the light amount increases. Becomes smaller, and the sensitivity becomes lower (FIG. 4C). In this way, the sensitivity can be changed according to the amount of signal charge transferred.
[0023]
In addition, as shown in FIGS. 5A to 5C, it is possible to form an inverted “concave” potential structure. Such a potential structure can be configured by connecting MOS capacitors in series.
[0024]
In this case, when the signal charge stored in the photodiode unit (PD) is small, the signal charge is transferred to the potential well in the FD region as shown in FIG. When the signal charge accumulated in the photodiode portion increases, as shown in FIG. 5B, the signal charge is transferred to the potential well formed by the MOS capacitor of the MOS2, and the signal charge further increases. Then, as shown in FIG. 5C, the signal charges are transferred to the MOS capacitance portion of the MOS1. FIG. 6A shows the characteristic of VFD (floating diffusion voltage) -signal charge amount at this time, FIG. 6B shows the characteristic of VFD-Cap, and FIG. 6B shows the light amount-output characteristic (sensitivity characteristic). FIG. 6C shows this. 6 (a) and 6 (b), a, b, and c show the characteristics of the operation states of FIGS. 5 (a), (b), and (c), respectively.
[0025]
In this embodiment, the case where the potential structure has a step-like shape and the case where the potential structure is an inverted “concave” shape has been described, but the present invention is not particularly limited to such a potential structure.
[0026]
Next, FIGS. 7 and 8 show schematic plan views of the solid-state imaging device having the MOS capacitance.
[0027]
7 and 8, reference numeral 11 denotes a photodiode (PD), reference numeral 12 denotes a gate of a transfer MOS transistor, reference numeral 13 denotes a floating diffusion region (FD), reference numeral 14 denotes a gate of a reset MOS transistor, and reference numerals 15 and 16 denote MOS capacitors. Gate electrode.
(Second embodiment)
An example in which the step-like potential structure in FIG. 3 and the inverted “concave” potential structure in FIG. 5 are formed using a buried PN junction instead of a MOS capacitor will be described below.
[0028]
FIG. 9 is a schematic sectional view showing the FD region and the buried PN junction. In the figure, 21 is an FD region, 22 is a high-concentration surface P region (PSR), 26 is an N-type diffusion region DN forming a PN junction with the PSR 22, 25 is an N-type diffusion region (DN1, DN2) 26 and a PN junction. Is a PWL (P-well region). When a reverse bias voltage is applied to the PN junction, the depletion layer expands. As shown in FIG. 9, the depletion layer extends from the PN junction between the PSR 22 and the N-type diffusion region DN26 (depletion layer width a), and the depletion layer extends from the PN junction between the N-type diffusion region DN26 and the PWL 25 (depletion layer). Width b). Now, as both depletion layers spread, no charge is stored in the depletion layer, so that no charge is accumulated and the capacitance becomes smaller. Then, when the reverse bias voltage increases and the depletion layers come into contact with each other (w = a + b; w is the depth of the N-type diffusion region DN26), the capacitance in this portion is almost eliminated. Therefore, as shown in FIG. 10, when the floating diffusion voltage VFD is high and the reverse bias voltage VR is high, the capacitance is substantially composed of only the capacitance CFD in the FD region, but the floating diffusion voltage VFD decreases and the reverse bias voltage decreases. When the voltage VR becomes smaller than the threshold value V1, the width (a + b) of the depletion layer becomes (a + b) <w, and the capacitance CBPN of the buried PN junction is added to the capacitance CFD. The threshold value V1 can be arbitrarily changed by changing the impurity concentration and the depth w of the N-type diffusion region. Then, by providing another N-type diffusion region in which the impurity concentration and the depth w of the N-type diffusion region are changed, the step-like potential structure in FIG. 3 and the inverted “concave” potential structure in FIG. Can be.
[0029]
FIG. 11 is a schematic cross-sectional view showing the FD region and the buried PN junction when a step-like potential structure or an inverted “concave” shape potential structure is formed. In the figure, 21 is an FD region, 22 is a high-concentration surface P region (PSR), 23 and 24 are N-type diffusion regions (DN1, DN2) forming a PN junction with the PSR 22, and 25 is a PWL (P-well region). is there. The N-type diffusion region 23 and the N-type diffusion region 24 are set to have different impurity concentrations, and the impurity concentration is appropriately set so that a step-like potential structure or an inverted “concave” potential structure can be formed. When forming a step-like potential structure, the N-type diffusion regions may be connected in series or in parallel. However, when forming an inverted “concave” shape potential structure, the N-type diffusion regions are connected in series. Connect to Note that the depth w of the N-type diffusion region may be changed instead of or in addition to the impurity concentration.
[0030]
FIG. 12 is a schematic plan view of the solid-state imaging device having the embedded PN junction. The same components as those in FIG. 7 are denoted by the same reference numerals. In FIG. 12, 21 to 23 indicate PN junctions, respectively.
[0031]
The threshold value V1 can be arbitrarily changed by changing not only the impurity concentration and the depth w of the N-type diffusion region but also the planar shape (for example, the width) of the N-type diffusion region.
[0032]
Looking at the DN region 26 in FIG. 9, if the DN region 26 is closer to the FD region 21, only the P region exists above and below, but if the DN region 26 is closer to the tip, the P region is also in contact with the side surface of the DN region 26. It is likely to be depleted. That is, since the vicinity of the side surface of the N-type diffusion region is more likely to be depleted, if the width of the N-type diffusion region is small, the threshold value V1 becomes small due to the influence of the side surface PN junction.
[0033]
Specifically, FIG. 14 shows a planar shape of the N diffusion region when the inverted “concave” potential structure of FIG. 5 is formed. FIG. 13 shows the planar shape of the N diffusion region in the case of the voltage-capacitance characteristics as shown in FIG. In the N diffusion region DN1 in FIG. 13, the width d2 of the region closer to the tip is smaller than the width d1 of the region closer to the FD region, and the region closer to the tip is easily depleted (depletion). Activation voltage is lower). In the N diffusion region DN1 in FIG. 14, the width d2 of the constricted portion is smaller than the width d1 of the region closer to the FD region, and the constricted portion is easily depleted.
(Third embodiment)
In the first and second embodiments described above, the signal charge is transferred with the reset voltage being a predetermined fixed potential (VDD). However, the sensitivity can be switched by appropriately changing the reset voltage. it can.
[0034]
First, the operation of the solid-state imaging device according to the present invention will be described with reference to FIGS. FIG. 15 is a schematic configuration diagram of a solid-state imaging device including a reset MOS transistor. FIGS. 16A to 16D are potential diagrams showing a light accumulation operation, a reset operation, a noise read operation, and a signal transfer / signal read operation, respectively.
[0035]
As shown in FIG. 16A, light is incident on the photodiode PD in a state where the transfer transistor MTX and the reset MOS transistor MRES are off, and optical signal charges are accumulated.
[0036]
Next, as shown in FIG. 16B, the reset MOS transistor MRES is turned on to reset the FD region. Here, the reset voltage is VDD, and the FD region is set to the potential of (VDD-Vth). The signal charge overflowing from the photodiode is discharged via the reset MOS transistor MRES.
[0037]
Next, as shown in FIG. 16C, the reset MOS transistor MRES is turned off to read a noise signal.
[0038]
Next, as shown in FIG. 16D, the transfer transistor MTX is turned on, the signal charge is transferred from the photodiode PD to the FD region, and the signal charge is read as a voltage signal. By performing a process of subtracting the noise signal previously read from this signal, a signal from which noise has been removed can be obtained.
[0039]
In such a solid-state imaging device, the sensitivity can be changed by appropriately changing the reset potential. Hereinafter, a case where the FD region and the MOS component have a step-like potential structure will be described as an example.
[0040]
For example, assuming that the reset voltage is VRES1 (= VDD), signal charges are accumulated in a deep portion of the potential well of the FD region as shown in FIG. On the other hand, assuming that the reset voltage is VRES2 (<VRES1), as shown in FIG. 17B, signal charges are accumulated in a shallower portion of the FD region and the potential well of the MOS component MOS1. That is, when the reset voltage is lowered, the charge corresponding to the reset voltage is stored in advance in a deep portion of the potential well of the FD region, so that the signal charge is stored in a larger capacity state. Therefore, the sensitivity can be switched by controlling the reset voltage. FIG. 18 is a characteristic diagram showing a light quantity-output characteristic (sensitivity characteristic). In the figure, a shows the characteristic when the reset voltage is VRES1, and b shows the characteristic when the reset voltage is VRES2.
[0041]
Hereinafter, a method of applying a reset voltage when the solid-state imaging device is one pixel and the pixels are arranged in a matrix will be described. The components of the pixel described below are the same as those shown in FIG.
[0042]
To make all the pixels have the same sensitivity, a fixed reset voltage is applied to all the pixels. In this case, as shown in FIG. 19, the sources of the transfer MOS transistors MRES of all the pixels are connected to a voltage source that supplies the reset voltage VRES.
[0043]
In order to arbitrarily set the sensitivity of each pixel, an arbitrary reset voltage is set and applied to each pixel. In this case, the reset voltage may be applied for each column, and the reset may be scanned for each row. In the pixel of FIG. 20, a power supply line for applying a reset voltage is provided for each column, the sources of the transfer MOS transistors MRES arranged in the same column are commonly connected, and the reset signal is connected to the gate of the transfer MOS transistor MRES for each row. , An arbitrary reset voltage can be applied to each pixel. In the pixel of FIG. 21, a power supply line for applying a reset voltage is also used as an output signal line. Since the reset operation and the signal read operation are performed at different timings, the output signal line is connected to the source of the transfer MOS transistor MRES as described above, and the reset signal is applied to the gate of the transfer MOS transistor MRES for each row. By doing so, an arbitrary reset voltage can be applied to each pixel.
[0044]
In this embodiment, since the sensitivity can be switched by changing the reset voltage, a solid-state imaging device that samples the amount of light incident on the pixel in advance and sets the reset voltage according to the sampling result is configured. be able to. In the pixel configuration of FIG. 19, the reset voltage is changed for all pixels, but in the pixel configurations of FIGS. 20 and 21, the reset voltage of a part of the pixel can be changed.
[0045]
FIG. 22 is a block diagram of a camera device using a solid-state imaging device that sets a reset voltage according to a sampling result. In the figure, 31 is a solid-state imaging device (sensor) whose reset voltage can be set arbitrarily, 32 is a CDS (correlated double sampling circuit) and AGC (auto gain control circuit), 33 is an A / D converter, and 34 is A camera signal processing IC 35 for performing signal processing such as outputting as an NTSC signal is a saturated bit memory.
[0046]
In the camera device, the camera signal processing IC 34 performs a saturation determination to determine that the input signal is saturated when the input value is equal to or greater than a certain value, and stores a saturated bit in a saturated bit memory 35 according to a result of the determination. To enter. Based on the saturation bit signal, it is determined whether or not the pixel is saturated. Based on the result, the reset voltage is controlled (in this case, the signal one frame before is used as the sampling signal).
[0047]
Further, as shown in FIG. 23, during the accumulation period of the signal charge, the reset MOS transistor MRES is closed, and the signal overflowing from the photodiode PD, that is, the overflow drain (OFD) signal (or the smear signal) is supplied to the FD region. The signal is stored, the signal is used as a sampling signal, a saturation determination is performed based on the sampling signal, and the reset voltage can be switched based on the result before the signal charge transfer from the PD. In this case, the saturation determination can be performed in the sensor chip.
[0048]
Further, a signal having a short storage time is transferred from the PD to the FD area before storing the signal charge, the signal is held on the FD area during the storage period, and the signal held in the FD area is read before reading the signal charge. Is read as a sampling signal, the saturation is determined, and the reset voltage is switched based on the result. In this case, the saturation determination can be performed in the sensor chip.
[0049]
Next, a configuration of an area sensor in which the pixel cells described above are arranged in a matrix will be described.
[0050]
FIG. 24 is a schematic configuration diagram showing the configuration of the area sensor. As shown in the figure, scanning of pixel cells arranged in a matrix in the row direction is performed by a vertical scanning circuit 100, and signals φRES, φTX, and φSEL are sent for each row, and a noise signal and a sensor are sent for each row. The signal is output to the vertical output line, and is stored in a noise signal storage capacitor and a sensor signal storage capacitor connected to the vertical output line via a switching MOS transistor. The noise signal and the sensor signal accumulated in each capacitor are scanned for each column by the horizontal scanning circuit 101, and the noise signal N and the sensor signal S are sequentially output for each column via the horizontal output line to the inverted input of the differential amplifier A. The signal is sent to the terminal (−) and the non-inverting input terminal (+), and a subtraction process is performed to obtain a signal SN for each pixel. Note that MCHR1 and MCHR2 are MOS transistors controlled by the signal φCHR and resetting the horizontal output line to a predetermined potential. φTN and φTS are signals for controlling a switching MOS transistor that transfers a noise signal and a sensor signal to respective capacitors.
[0051]
FIG. 25 is a block diagram illustrating a video camera device using the solid-state imaging device according to the present embodiment.
[0052]
In FIG. 25, 41 is a lens system, 42 is a stop, 43, 45, and 47 are motors, 44 is a variable-magnification lens driving unit that controls the motor 43, and 46 is a stop that controls the motor 45 to drive the stop 42. A mechanism driving means 48 is a focus competition lens driving means for controlling the motor 47. Reference numeral 49 denotes a solid-state imaging device for photoelectrically converting an optical signal incident from the lens system 41. The solid-state imaging device 49 capable of switching the reset voltage of the present embodiment described above is used. The reset voltage is set by the output selection signal. 50 is a CDS / AGC and 51 is an AD converter. 52 is a camera signal processing circuit, 52a is a Y / C separation circuit, 52b is a luminance signal processing circuit, 52c is a color signal processing circuit, 52d is a color suppression circuit, 52e is a digital output conversion circuit, and 52f is a saturated pixel determination measurement. Circuit. The determination of a saturated pixel by the saturated pixel determination measurement circuit 52f is performed based on the luminance signal and the color signal. The determination result of the saturated pixel is input to the microcomputer 55, and an output selection signal is output based on the determination result. The microcomputer 55 controls the variable-magnification lens driving unit 44, the aperture mechanism driving unit 46, and the focus compensation lens driving unit 48 based on the signal from the camera signal processing circuit 52.
[0053]
The output from the camera signal processing circuit 52 is sent to a monitor means 54 through a digital decoder and a DA converter 53 to be displayed as an image and sent to a VTR.
[0054]
FIG. 26 is a block diagram showing a conventional video camera apparatus, which is different from the present embodiment in that the saturated pixel determination and measurement circuit 12f is not provided and an output selection signal is not output.
(Fourth embodiment)
FIG. 27 is a block diagram showing the configuration of the fourth embodiment of the solid-state imaging device according to the present invention. FIG. 28 is a timing chart showing the operation of the solid-state imaging device.
[0055]
In the present embodiment, in a circuit similar to that of the above-described embodiment, a noise signal from a sensor unit and a noise + optical signal are temporarily held in a signal holding unit and are read out by the following reading method.
(1) As shown in FIG. 28, the reset switch (reset MOS transistor MRES) is turned off during the accumulation period before the signal is read.
(2) Before reading the noise signal, a light quantity sampling signal, which is a signal corresponding to the incident light quantity accumulated in the FD area, is read ((1) in FIG. 28). This signal uses an optical signal that enters the FD region. In a CCD, such an optical signal is prevented by a layout or shading, but in this embodiment, a light amount sampling signal is obtained by positively using the optical signal. In some cases, the upper part of the FD region is opened, and a signal is further taken in, so that a larger sampling signal can be obtained.
(3) After turning on / off the reset switch to reset the FD area, read out a noise signal ((2) in FIG. 28).
(4) Using the signals (1) or (1) and (2) in FIG. 28, the amount of incident light is determined in the reset voltage control circuit, and the reset voltage is determined accordingly.
(5) Set the reset voltage determined in (4) above and reset the FD area again. Here, the voltage V2 was selected as the reset voltage among the voltages V1 to V4 shown in FIG.
(6) Read out the noise signal after reset ([3] in FIG. 28).
(7) The transfer switch (transfer transistor MTX) is turned on / off by the transfer pulse, the signal charge is transferred from the photodiode to the FD region, and the noise + optical signal is read ([4] in FIG. 28). Using the signals (3) and (4) in FIG. 28, the main signal, which is an image signal, was read.
[0056]
As described above, in the present embodiment, it is possible to obtain a wide variety of image signals by controlling the sensitivity according to the light amount by the reset voltage using the sampling signal.
[0057]
Note that the present invention is not limited to an area sensor, and can be used for a line sensor.
[0058]
【The invention's effect】
As described above, according to the present invention, the sensitivity can be changed in accordance with the signal charges stored in the photoelectric conversion unit, and a signal having an expanded dynamic range can be obtained.
[0059]
Further, the sensitivity can be switched by appropriately changing the reset voltage.
[0060]
For this reason, it is possible to switch between a signal having a high sensitivity but a small dynamic range and a signal having a low sensitivity but a large dynamic range as necessary. Therefore, the present invention can be used, for example, for backlight correction.
[Brief description of the drawings]
FIG. 1 is a schematic explanatory diagram showing a configuration of a solid-state imaging device according to the present invention.
FIG. 2 is a schematic explanatory diagram illustrating a configuration of a solid-state imaging device according to the present invention.
FIG. 3 is an explanatory diagram in a case where an FD portion and a MOS component have a stepped potential structure.
4A is a diagram illustrating VFD-Q characteristics, FIG. 4B is a diagram illustrating VFD-Cap characteristics, and FIG. 4C is a diagram illustrating light amount-output characteristics.
FIG. 5 is an explanatory diagram in a case where the FD section and the MOS constituent section have an inverted “concave” shape potential structure.
6A is a diagram illustrating VFD-Q characteristics, FIG. 6B is a diagram illustrating VFD-Cap characteristics, and FIG. 6C is a diagram illustrating light amount-output characteristics.
FIG. 7 is a schematic plan view of a solid-state imaging device including a MOS capacitor.
FIG. 8 is a schematic plan view of another example of the solid-state imaging device including a MOS capacitor.
FIG. 9 is a schematic sectional view showing an FD region and a buried PN junction.
FIG. 10 is a characteristic diagram showing a relationship between a reverse bias voltage and a capacitance.
FIG. 11 is a schematic sectional view showing an FD region and a buried PN junction.
FIG. 12 is a schematic plan view of a solid-state imaging device having a buried PN junction.
FIG. 13 is a plan view showing a planar shape of an N diffusion region when a step-like potential structure is formed.
FIG. 14 is a plan view showing a planar shape of an N diffusion region when an inverted “concave” potential structure is formed.
FIG. 15 is a schematic configuration diagram of a solid-state imaging device including a reset MOS transistor.
FIGS. 16A to 16D are potential diagrams illustrating a light accumulation operation, a reset operation, a noise read operation, and a signal transfer / signal read operation, respectively.
FIG. 17 is a potential diagram showing an operation of changing sensitivity by changing a reset potential.
FIG. 18 is a characteristic diagram showing a light amount-output characteristic (sensitivity characteristic).
FIG. 19 is a pixel configuration diagram for explaining a method of applying a reset voltage.
FIG. 20 is a diagram illustrating a pixel configuration for describing a method of applying a reset voltage.
FIG. 21 is a diagram illustrating a pixel configuration for explaining a method of applying a reset voltage.
FIG. 22 is a block diagram of a camera device using a solid-state imaging device that sets a reset voltage according to a sampling result.
FIG. 23 is a potential diagram for explaining a detection operation of a sampling signal.
FIG. 24 is a schematic configuration diagram showing a configuration of an area sensor.
FIG. 25 is a block diagram illustrating a video camera device using the solid-state imaging device according to the present embodiment.
FIG. 26 is a block diagram showing a conventional video camera device.
FIG. 27 is a block diagram illustrating a configuration of a fourth embodiment of the solid-state imaging device according to the present invention;
FIG. 28 is a timing chart showing the operation of the solid-state imaging device of the embodiment.
FIG. 29 is a diagram showing characteristics of VFD-Cap.
[Explanation of symbols]
1 N-type semiconductor substrate
2 P-type well region
3 N-type diffusion region
4 P type area
5 Floating diffusion (FD) area
6 Transfer gate electrode
7,8 MOS component
11 Photodiode (PD)
12 Transfer MOS transistor gate
13 Floating diffusion area (FD)
14. Gate of reset MOS transistor
Gate electrodes for constructing 15, 16 MOS capacitors
21 FD area
22 High concentration surface P area (PSR)
23, 24 N-type diffusion regions (DN1, DN2)
25 PWL (P-well area)
26 N-type diffusion region (DN)
31 Solid-state image sensor (sensor)
32 CDS / AGC
33 A / D converter
34 Camera signal processing IC
35 Saturated bit memory

Claims (4)

In a solid-state imaging device including a plurality of pixels each including a photoelectric conversion unit and a charge-voltage conversion unit that converts a signal charge transferred from the photoelectric conversion unit into a signal voltage in a first semiconductor region of one conductivity type,
The charge-voltage converter includes an impurity diffusion region of a conductivity type opposite to the one conductivity type formed in the first semiconductor region, and an impurity diffusion region of the opposite conductivity type embedded in the first semiconductor region. A buried semiconductor region,
The one conductivity type second semiconductor region is formed on the buried semiconductor region, and the buried semiconductor region and the first and second semiconductor regions constitute a junction,
The impurity diffusion region and the buried semiconductor region are adjacent and in contact with each other;
The charge-voltage converter has a capacitance formed in the impurity diffusion region and a capacitance formed in the buried semiconductor region that depends on a depletion layer width that changes due to a reverse bias voltage applied to the junction. A solid-state imaging device characterized by the above-mentioned. The solid-state imaging device according to claim 1, characterized in that the voltage dependence of the capacitance formed in the junction is controlled by the impurity concentration or the depth of the buried semiconductor region constituting the joint portion. The solid-state imaging device according to claim 1, characterized in that the voltage dependence of the capacitance formed in the junction is controlled by the width of the embedded semiconductor region constituting the joint portion. A solid-state imaging device according to any one of claims 1 to 3 ,
A lens system that forms an image of light on the solid-state imaging device, an AD converter that converts a signal from the solid-state imaging device into a digital signal, and a signal processing circuit that processes a signal from the AD converter. A camera characterized by the following.

Images