JP2015100003A - Solid-state imaging element and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an S/N ratio at the time of reading out with high sensitivity while enabling enlargement of the dynamic range.SOLUTION: An element 4 includes: a plurality of pixel blocks BL having one photoelectric conversion part PD, a first node Pa, and one transfer switch which transfers electric charges to the first node Pa from one photoelectric conversion part PD; three or more second nodes Pb corresponding to the first nodes Pa of three or more pixel blocks BL, respectively; three or more first switch parts SWA which electrically connect and cut off between the first nodes Pa of three or more pixel blocks BL and three or more second nodes Pb, respectively; a plurality of second switch parts SWB which connect three or more second nodes Pb and each of which electrically connects and cuts off between two second nodes Pb.

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  In Patent Document 1 below, a plurality of pixels, each of which includes at least two pixels including (a) a photodetector, (b) a charge-voltage conversion region that forms a floating capacitance section, and (c) an input section to an amplifier. And a solid-state imaging device including a connection switch that selectively connects the charge-voltage conversion regions.

Special table 2008-546313 gazette

  In the conventional solid-state imaging device, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion region is expanded, so that the dynamic range is increased. Can be enlarged.

  In the conventional solid-state imaging device, the charge-voltage conversion capacity is reduced and the charge-voltage conversion coefficient is increased by turning off the connection switch and separating the charge-voltage conversion region from other charge-voltage conversion regions. Therefore, the SN ratio at the time of high sensitivity reading becomes high.

  However, in the conventional solid-state imaging device, even when the connection switch is turned off, the SN ratio at the time of high-sensitivity readout cannot be increased so much.

  The present invention has been made in view of such circumstances, a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the same. An object is to provide an apparatus.

The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect is provided corresponding to one photoelectric conversion unit, a first node, and the one photoelectric conversion unit, and transfers charges from the photoelectric conversion unit to the first node. A plurality of pixel blocks having one transfer switch, and three or more second nodes respectively corresponding to the first nodes of three or more pixel blocks;
Three or more first switch units that electrically connect and disconnect between the first node of the three or more pixel blocks and the three or more second nodes, respectively, and the three A plurality of second switch units that connect the second nodes described above and each electrically connect and disconnect between the two second nodes are provided.

  The pixel block may have only one photoelectric conversion unit and be configured by one pixel, or may have two or more photoelectric conversion units and be configured by a plurality of pixels. Good. This is the same for each aspect described later.

  In the solid-state imaging device according to a second aspect, in the first aspect, the plurality of second switch units connect the three or more second nodes in a daisy chain.

  In the first or second aspect, the solid-state imaging device according to the third aspect is the p-state (p is an integer of 1 or more) of the first switch sections in the predetermined operation mode. 1 switch unit and q (q is an integer greater than p) of the second switch units are ON pixels, and one of the three or more pixel blocks is one pixel. A control unit that controls each of the first switch units and each of the second switch units is provided so as to be electrically connected to the first node of the block.

  The solid-state imaging device according to the fourth aspect is the one in which the p is 1 in the third aspect.

  A solid-state imaging device according to a fifth aspect is the solid-state imaging device according to any one of the first to fourth aspects, wherein the control unit has one pixel block of the three or more pixel blocks in another predetermined operation mode. The first of the three or more pixel blocks is turned off so that the first switch unit that electrically connects and disconnects between the first node and the second node corresponding to the first node. The first switch section of one pixel block is controlled.

  In the solid-state imaging device according to the sixth aspect, in any one of the first to fifth aspects, each of the pixel blocks includes a plurality of the photoelectric conversion units and the transfer switches.

  An imaging apparatus according to a seventh aspect includes any one of the first to sixth solid-state imaging elements.

  In the seventh aspect, an imaging apparatus according to an eighth aspect includes control means for switching between the predetermined operation mode and the other predetermined operation mode according to a set value of ISO sensitivity.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to expand a dynamic range, the solid-state image sensor which can improve the S / N ratio at the time of highly sensitive reading, and an imaging device using the same can be provided.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 2 is an enlarged circuit diagram illustrating the vicinity of four pixel blocks in FIG. 1. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. It is a circuit diagram which shows schematic structure of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing the electronic camera 1 according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. The present invention can be applied to various imaging devices such as an electronic camera and an electronic camera such as a video camera that captures moving images.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. In normal main shooting (during still image shooting) or the like, the imaging control unit 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after, for example, a so-called global reset that resets all pixels simultaneously. The solid-state image sensor 4 is controlled. In the electronic viewfinder mode or moving image shooting, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined reading operation while performing a so-called rolling electronic shutter, for example. At these times, as will be described later, the imaging controller 5 controls the solid-state imaging device 4 so as to perform a read operation in each operation mode described later according to the ISO sensitivity setting value. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

  When the CPU 9 in the electronic camera 1 is instructed by the operation unit 14 to operate in the electronic viewfinder mode, moving image shooting, normal normal shooting (still image shooting), or the like, the CPU 9 drives the imaging control unit 5 accordingly. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of normal main shooting (during still image shooting) or the like, the CPU 9 processes the digital image signal from the solid-state imaging device 4 by the digital signal processing unit 6 and stores it in the memory 7, and then the operation unit 14. The image processing unit 13 or the image compression unit 12 performs a desired process based on the above command, outputs the processed signal to the recording unit 11 and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of four pixel blocks BL sequentially arranged in the column direction in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but is not limited thereto, and may be configured as, for example, another XY address type solid-state imaging device.

  As shown in FIGS. 2 and 3, the solid-state imaging device 4 includes a pixel block BL arranged in a two-dimensional matrix in N rows and M columns and having two pixels PX (PXA, PXB), respectively, and a first block described later. The first transistor SWA as the first switch unit that electrically connects and disconnects between the node Pa and the corresponding second node Pb, and the two second nodes Pb are electrically connected. And the second transistor SWB as the second switch section to be disconnected, the vertical scanning circuit 21, the control lines 22 to 27 provided for each row of the pixel block BL, and the column of the pixel PX (pixel block BL A plurality of (M) vertical signal lines 28 for receiving signals from the pixels PX (pixel blocks BL) in the corresponding column provided for each column, and a constant current source 29 provided for each vertical signal line 28. , Each vertical signal A column amplifier 30, CDS circuit (correlated double sampling circuit) 31 and A / D converter 32 provided corresponding to the 28, and a horizontal read circuit 33.

  The column amplifier 30 may be an analog amplifier or a so-called switched capacitor amplifier. Further, the column amplifier 30 is not necessarily provided.

  For convenience of drawing, FIG. 2 shows M = 2, but the number of columns M is actually a larger arbitrary number. Further, the number N of rows is not limited. When distinguishing the pixel block BL for each row, the pixel block BL in the j-th row is indicated by a symbol BL (j). This also applies to other elements and control signals described later. 2 and 3 show pixel blocks BL (n−1) to BL (n + 2) in the (n−1) th to n + 2th rows over four rows.

  In the drawing, the pixel of the pixel block BL is distinguished from the lower pixel in FIGS. 2 and 3 by PXA and the upper pixel in FIGS. 2 and 3 is PXB. When the description is made without distinction, the description may be made with the reference numeral PX attached to both. In the drawings, the photodiode of the pixel PXA is identified by PDA, and the photodiode of the pixel PXB is identified by PDB. However, when the description is made without distinguishing both, the PD is denoted by PD. May explain. Similarly, the transfer transistor of the pixel PXA is denoted by TXA and the transfer transistor of the pixel PXB is denoted by TXB. The two are distinguished from each other. There is a case. In the present embodiment, the photodiodes PD of the pixels PX are arranged in 2N rows and M columns in a two-dimensional matrix.

  In the present embodiment, each pixel PX is a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer switch that transfers charges from the photodiode PD to the first node Pa. Transfer transistor TX.

  In the present embodiment, the plurality of pixels PX form a pixel block BL for every two pixels PX (PXA, PXB) in which the photodiodes PD are sequentially arranged in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL include a set of first node Pa, amplification transistor AMP, and reset transistor. The RST and the selection transistor SEL are shared. A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa and the reference potential, and the charge transferred to the first node Pa is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the first node Pa. The reset transistor RST constitutes a reset switch that resets the potential of the first node Pa. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). 2 and 3, n indicates a row of the pixel block BL. For example, a pixel block BL in the first row is constituted by the pixel PX (PXA) in the first row and the pixel PX (PXB) in the second row, and the pixel PX (PXA) in the third row and the pixel PX in the fourth row. (PXB) constitutes the pixel block BL in the second row.

  For example, the transfer transistor TXA (n) of the pixel block BL (n) transfers charge from the photodiode PDA (n) to the first node Pa (n), and the transfer transistor TXB (n) is the photodiode PDB (n ) To the first node Pa (n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa (n) and the reference potential, and the charge transferred to the first node Pa (n) is converted into a voltage by the capacitance. The The amplification transistor AMP (n) outputs a signal corresponding to the potential of the first node Pa (n). The reset transistor RST (n) resets the potential of the first node Pa (n). The same applies to the rows of other pixel blocks BL.

  In the present invention, for example, the pixel block BL may be configured for each of three or more pixels PX in which the photodiodes PD are sequentially arranged in the column direction.

  Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color array on the light incident side of the photodiode PD of each pixel PX. (For example, a Bayer array). The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter.

  The first transistor SWA (n) constitutes a first switch unit that electrically connects and disconnects between the first node Pa (n) and the corresponding second node Pb (n). ing. Such a first switch unit can be configured by combining a plurality of switches such as transistors, but in order to simplify the structure, a single first transistor SWA is used as in the present embodiment. (N) is preferable. The same applies to the other first transistors SWA.

  Each second transistor SWB includes a second node Pb corresponding to the first node Pa of the one pixel block BL and the other of the two pixel blocks BL adjacent to each other in the column direction among the pixel blocks BL. The second switch unit is configured to be electrically connected to and disconnected from the second node Pb corresponding to the first node Pa of the pixel block BL. Thus, in the present embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy chain by a plurality of the second switch portions. The second switch portion as described above can be configured by combining a plurality of switches such as a plurality of transistors. However, in order to simplify the structure, a single second transistor is used as in the present embodiment. It is preferable to use SWB.

  For example, the second transistor SWB (n) includes the second node Pb (n) corresponding to the first node Pa (n) of the pixel block BL (n) in the nth row and the pixel in the n−1th row. The block BL (n−1) is provided so as to be electrically connected to and disconnected from the second node Pb (n−1) corresponding to the first node Pa (n−1) of the block BL (n−1). This also applies to the other second transistors SWB.

  The gate electrode of the amplification transistor AMP (n) of the pixel block BL (n), the source region of the reset transistor RST (n), the drain diffusion region of the transfer transistors TXA (n) and TXB (n), and the first transistor SWA The source diffusion regions (n) are electrically connected to each other by the wiring 71 (n) and are conductive. The first node Pa (n) corresponds to the wiring 71 (n) and the entire portion that is electrically connected to and conductive with the wiring 71 (n). The same applies to the rows of other pixel blocks BL.

  The wiring 72 (n) electrically connects the drain diffusion region of the first transistor SWA (n), the drain diffusion region of the second transistor SWB (n), and the source diffusion region of the second transistor SWB (n + 1). Connected and conducting. The second node Pb (n) corresponds to the wiring 72 (n) and the entire portion that is electrically connected to and conductive with the wiring 72 (n). The same applies to other first transistors SWA and other second transistors SWB.

  2 and 3, VDD is a power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWA, SWB are all nMOS transistors.

  The gate of the transfer transistor TXA is commonly connected to the control line 26 for each row, and a control signal φTXA is supplied from the vertical scanning circuit 21 to the gate. The gate of the transfer transistor TXB is commonly connected to the control line 25 for each row, and a control signal φTXB is supplied from the vertical scanning circuit 21 to the gate. The gates of the reset transistors RST are commonly connected to the control line 24 for each row, and a control signal φRST is supplied from the vertical scanning circuit 21 there. The gates of the selection transistors SEL are connected in common to the control line 23 for each row, and a control signal φSEL is supplied from the vertical scanning circuit 21 there. The gates of the first transistors SWA are commonly connected to the control line 22 for each row, and a control signal φSWA is supplied from the vertical scanning circuit 21 to the first transistor SWA. The gates of the second transistors SWB are commonly connected to the control line 27 for each row, and a control signal φSWB is supplied from the vertical scanning circuit 21 to the gate. For example, the control signal φTXA (n) is supplied to the gate of the transfer transistor TXA (n), the control signal φTXB (n) is supplied to the gate of the transfer transistor TXB (n), and the gate of the reset transistor RST (n). Is supplied with the control signal φRST (n), the gate of the selection transistor SEL (n) is supplied with the control signal φSEL (n), and the gate of the first transistor SWA (n) is supplied with the control signal φSWA (n). And a control signal φSWB (n) is supplied to the gate of the second transistor SWB (n).

  Each transistor TXA, TXB, RST, SEL, SWA, SWB is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSWA, φSWB is high level (H), and is low level (L). Turn off.

  The vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL under the control of the imaging control unit 5 in FIG. The first transistor SWA and the second transistor SWB are controlled to realize a still image reading operation, a moving image reading operation, and the like. In this control, for example, a read operation in each operation mode, which will be described later, is performed in accordance with the ISO sensitivity setting value. By this control, the signal (analog signal) of the pixel PX in the corresponding column is supplied to each vertical signal line 28.

  In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode to be described later according to a command (control signal) from the imaging control unit 5 in FIG.

  The signal read out to the vertical signal line 28 is amplified by the column amplifier 30 for each column, and further optical signals (signals including optical information photoelectrically converted by the pixels PX) and dark signals (light After being subjected to processing for obtaining a difference from the signal (difference signal including a noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Is done. The digital image signal held in each A / D converter 32 is horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ).

  The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is at a high level (H), The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is converted into an optical signal. Sampling as Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and optical signal based on the clock and pulse from the timing generation circuit. As the configuration of the CDS circuit 31, a known configuration can be adopted.

  2 and 3, CC (n) is a capacitance between the first node Pa (n) and the reference potential when the first transistor SWA (n) is off. The capacitance value of the capacitor CC (n) is Cfd1. CD (n) is between the second node Pb (n) and the reference potential when the first transistor SWA (n) and the second transistors SWB (n) and SWB (n + 1) are off. Capacity. Let Cfd2 be the capacitance value of the capacitance CD (n). The same applies to other first transistors SWA and other second transistors SWB.

  The capacitance CD (n) includes the wiring capacitance of the wiring 72 (n), the capacitance of the drain diffusion region of the first transistor SWA (n), the capacitance of the drain diffusion region of the second transistor SWB (n), And the capacitance of the source diffusion region of the two transistors SWB (n + 1). Since the capacitance of the source diffusion region and the drain diffusion region of the transistor changes the size of the depletion layer when the applied voltage changes, the capacitance value cfd2 of CD (n) changes when the voltage applied to CD (n) changes. However, the capacitance of the drain diffusion region of the first transistor SWA (n), the capacitance of the drain diffusion region of the second transistor SWB (n), and the capacitance of the source diffusion region of the second transistor SWB (n + 1) are: Since the wiring capacity of the wiring 72 (n) is small, the amount of change in the capacitance value cfd2 of CD (n) when the voltage applied to CD (n) changes is negligible. Therefore, the voltage dependence of the capacitance value cfd2 of CD (n) is negligible.

  The capacitance CC (n) includes the capacitance of the drain diffusion region of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the reset transistor RST (n), and the source of the first transistor SWA (n). The capacitance of the diffusion region, the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71 (n), and the sum of these capacitance values becomes the capacitance value Cfd1 of the capacitor CC (n). . Therefore, the capacitance of the source diffusion region of the transistor and the capacitance of the gate electrode change depending on the applied voltage, so that the dimension of the depletion layer changes. Therefore, the capacitance value Cfd1 of the capacitor CC (n) has voltage dependency. The same applies to the rows of other pixel blocks BL. Note that the capacitance of the source diffusion region of the second transistor SWB (n) does not become a constituent element of the capacitor CC (n), and accordingly, the capacitance value Cfd1 of the capacitor CC (n) becomes smaller.

  Here, the value of the channel capacitance when the first transistor SWA is on and the value of the channel capacitance when the second transistor SWB is on are both Csw. Usually, the capacitance value Csw is smaller than the capacitance values Cfd1 and Cfd2.

  Now, paying attention to the pixel block BL (n), the first transistor SWA (n) is turned off (that is, the on-state transistor among the first transistors SWA and the second transistors SWB is the first one). And a capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is a capacitance CC (n). It becomes. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1. This state corresponds to a state of a period T2 in FIG. 4 showing a first operation mode described later.

  When the first transistor SWA (n) is turned on by focusing on the pixel block BL (n), the first transistor SWA and the second transistor SWB other than the first transistor SWA (n) are turned on. Are not electrically connected to the first node Pa (n) (here, specifically, the second transistors SWB (n), SWB (n + 1) Is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CD (n) and the first transistor with respect to the capacitance CC (n). The channel capacity when SWA (n) is turned on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2. This state corresponds to a state of a period T2 in FIG. 5 showing a second operation mode described later.

  Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, among the first transistors SWA and the second transistors SWB, If the transistors other than the transistors SWA (n) and SWB (n + 1) are not electrically connected to the first node Pa (n) (here, specifically, the transistor SWB). (If (n), SWA (n + 1), SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is the capacitance CD (n), The capacitance CD (n + 1) and the channel capacitance when the transistors SWA (n) and SWB (n + 1) are turned on are added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 2 × Cfd2 + 2 × Csw≈Cfd1 + 2 × Cfd2. This state corresponds to a state of a period T2 in FIG. 6 showing a third operation mode described later.

  Furthermore, paying attention to the pixel block BL (n), when the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, the first transistors SWA and the second transistors SWA (n + 1) are turned on. Of the transistors SWB, transistors other than the transistors SWA (n), SWA (n + 1), and SWB (n + 1) must be in an electrically connected state with respect to the first node Pa (n). Here, specifically, if the transistors SWB (n) and SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is relative to the capacitance CC (n). Capacitance CD (n), capacitance CD (n + 1), capacitance CC (n + 1) and channel capacitance when the transistors SWA (n), SWA (n + 1) and SWB (n + 1) are turned on are added. The things. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2. This state corresponds to a state of a period T2 in FIG. 7 showing a fourth operation mode described later.

  Further, focusing on the pixel block BL (n), when the first transistor SWA (n) and the second transistors SWB (n + 1) and SWB (n + 2) are turned on, the first transistors SWA and the second transistors SWB (n + 1) and SWB (n + 2) are turned on. Of the transistors SWB, transistors in the on state other than the transistors SWA (n), SWB (n + 1), and SWB (n + 2) are not electrically connected to the first node Pa (n) ( Here, specifically, if the transistors SWA (n + 1), SWA (n + 2), SWB (n), and SWB (n + 3) are off), the charge-voltage conversion capacity of the first node Pa (n) is For the capacitor CC (n), the capacitor CD (n), the capacitor CD (n + 1), the capacitor CD (n + 2), and the transistors SWA (n), SWB (n + 1), SWB (n + 2) The obtained by adding the channel capacity when on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2. This state corresponds to a state of a period T2 in FIG. 8 showing a fifth operation mode described later.

  As described above, if there is no on-state transistor electrically connected to the first node Pa (n) among the first transistors SWA and the second transistors SWB, the first node Pa ( Since the capacitance value of the charge voltage conversion capacitor n) becomes the minimum capacitance value Cfd1, and the charge voltage conversion coefficient by the charge voltage conversion capacitor is increased, reading at the highest SN ratio is possible.

  On the other hand, among the first transistors SWA and the second transistors SWB, the number of ON-state transistors electrically connected to the first node Pa (n) is increased to one or more desired numbers. If so, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) can be increased to a desired value and a large amount of signal charge can be handled, so that the number of saturated electrons can be increased. it can. Thereby, the dynamic range can be expanded.

  The first node Pa (n) of the pixel block BL (n) has been described above, but the same applies to the first nodes Pa of other pixel blocks BL.

  FIG. 4 is a timing chart showing a first operation mode of the solid-state imaging device 4 shown in FIG. In the first operation mode, each pixel block BL is sequentially selected for each row, and the first node Pa of the selected pixel block BL among the first transistors SWA and the second transistors SWB is applied to the first node Pa. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state where there is no on-state transistor electrically connected to the transistor (a state where the charge-voltage conversion capacitance of the first node Pa is minimum). This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row. In the example illustrated in FIG. 4, signals of all the pixels PXA and PXB are read out. However, the present invention is not limited to this. For example, thinning out reading that reads out pixel rows may be performed. This also applies to the examples shown in FIGS. 5 to 8 described later.

  In FIG. 4, the pixel block BL (n-1) in the (n-1) th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixels in the (n + 1) th row in the period T3. This shows a situation where the block BL (n + 1) is selected. Since the operation when the pixel block BL of any row is selected is the same, only the operation when the pixel block BL (n) of the n-th row is selected will be described here.

  The exposure of the photodiodes PDA (n) and PDB (n) has already been completed in the predetermined exposure period before the start of the period T2. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and during electronic viewfinder mode or movie shooting. This is performed by a so-called rolling electronic shutter operation. Immediately before the start of the period T2, all the transistors SEL, RST, TXA, TXB, SWA, SWB are turned off.

  In the period T2, φSEL (n) in the nth row is set to H, the selection transistor SEL (n) in the pixel block BL (n) in the nth row is turned on, and the pixel block BL (n) in the nth row is turned on. Selected.

  Further, in the period T2, φSWA (n) is set to L, and the first transistor SWA (n) is turned off. Accordingly, in the period T2, there is no on-state transistor electrically connected to the first node Pa (n) of the selected pixel block BL (n) among the transistors SWA and SWB. . Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1, which is the minimum.

  For a certain period immediately after the start of the period T2, φRST (n) is set to H, the n-th row reset transistor RST (n) is once turned on, and the potential of the first node Pa (n) is once set to the power supply potential VDD. Reset to.

  The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time t1 in the period T2, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the n-th row. A signal amplified later by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXA (n) is set to H and the transfer transistor TXA (n) in the n-th row is turned on for a certain period from time t2 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDA (n) of the pixel block BL (n) in the nth row is transferred to the charge-voltage conversion capacitor of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n), excluding noise components.

  At a subsequent time t3 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is further sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t1 and the optical signal sampled in a certain time from time t3. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  Then, φRST (n) is set to H for a certain period from time t4 in the period T2, the reset transistor RST (n) in the n-th row is once turned on, and the potential of the first node Pa (n) is once set. Reset to power supply potential VDD.

  The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t5 in the period T2, and the potential appearing at the first node Pa (n) is amplified by the n-th amplification transistor AMP (n). A signal amplified later by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXB (n) is set to H and the transfer transistor TXB (n) in the n-th row is turned on for a certain period from time t6 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDB (n) of the pixel block BL (n) in the nth row is transferred to the charge-voltage conversion capacitor of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n), excluding noise components.

  At a subsequent time t7 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the n-th row, and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is further sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t5 and the optical signal sampled in a certain time from time t7. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  As described above, in the first operation mode, the transistor SWA and SWB are selected because there is no transistor in the on state that is electrically connected to the first node Pa of the selected pixel block BL. In addition, since the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the pixel block BL is minimized and the charge-voltage conversion coefficient by the charge-voltage conversion capacitance is increased, reading with the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 instructs to perform the first operation mode.

  FIG. 5 is a timing chart showing a second operation mode of the solid-state imaging device 4 shown in FIG. In the second operation mode, each pixel block BL is sequentially selected for each row, and one on-state transistor SWA is selected from each first transistor SWA and each second transistor SWB. In a state of being electrically connected to the first node Pa of the pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on sequentially, and each of the selected pixel blocks BL is selected. It is an example of the operation | movement which reads the signal of photodiode PDA, PDB sequentially for every line.

  Similarly to FIG. 4, in FIG. 5, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The second operation mode shown in FIG. 5 is different from the first operation mode shown in FIG. 4 in the following points.

  In the second operation mode shown in FIG. 5, in a period T2 in which the pixel block BL (n) in the n-th row is selected, φSWA (n) is set to H and φSWB (n), φSWB (n + 1) is set to L. The first transistor SWA (n) is turned on and the second transistors SWB (n) and φSWB (n + 1) are turned off. Thus, in the period T2, one of the transistors SWA and SWB that is in the on state is turned on by the first transistor SW (here, the first transistor SWA (n)) of the selected pixel block BL (n). The first node Pa (n) is electrically connected. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is one step larger than the first operation mode shown in FIG.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the second operation mode, one of the transistors SWA and SWB and the first transistor SWA in the on state are electrically connected to the first node Pa of the selected pixel block BL. Since they are connected, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is increased by one level, and the number of saturated electrons in the charge-voltage conversion capacitance of the first node Pa is increased by one level. Can be enlarged. Thereby, the dynamic range can be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 instructs the second operation mode to be performed.

  FIG. 6 is a timing chart showing a third operation mode of the solid-state imaging device 4 shown in FIG. In the third operation mode, each pixel block BL is sequentially selected for each row, and one of the first transistors SWA and 1 of the first transistors SWA and the second transistors SWB is turned on. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected while the two second transistors SWB in the on state are electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row.

  In FIG. 6, similarly to FIG. 4, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The third operation mode shown in FIG. 6 is different from the first operation mode shown in FIG. 4 in the following point.

  In the third operation mode shown in FIG. 6, φSWA (n) and φSWB (n + 1) are set to H and φSWA (n + 1), φSWB in the period T2 in which the pixel block BL (n) in the n-th row is selected. (N), φSWB (n + 2) are set to L, the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, and the first transistor SWA (n + 1) and the second transistor SWB are turned on. (N), SWB (n + 2) is turned off. Thus, in the period T2, one of the transistors SWA and SWB is turned on, the first transistor SWA in the on state (here, the first transistor SWA (n)) and one second transistor SWB in the on state ( Here, the second transistor SWB (n + 1)) is electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1 + 2 × Cfd2 + Csw≈Cfd1 + 2 × Cfd2, which is two stages compared to the first operation mode shown in FIG. growing.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the third operation mode, one of the transistors SWA and SWB is turned on by the first transistor SWA in the on state and the second transistor SWB in the on state of the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by two levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by two stages. Thereby, the dynamic range can be expanded by two stages. For example, when the ISO sensitivity setting value is two steps lower than the highest value, the imaging control unit 5 instructs the third operation mode to be performed.

  FIG. 7 is a timing chart showing a fourth operation mode of the solid-state imaging device 4 shown in FIG. In the fourth operation mode, each pixel block BL is sequentially selected for each row, and two on-state first transistors SWA and 1 of each first transistor SWA and each second transistor SWB are selected. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected while the two second transistors SWB in the on state are electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row.

  In FIG. 7, similarly to FIG. 4, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The fourth operation mode shown in FIG. 7 is different from the first operation mode shown in FIG. 4 in the following point.

  In the fourth operation mode shown in FIG. 7, φSWA (n), φSWA (n + 1), and φSWB (n + 1) are set to H and φSWB in the period T2 in which the pixel block BL (n) in the n-th row is selected. (N), φSWB (n + 2) are set to L, the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, and the second transistors SWB (n), SWB (n + 2) is turned off. Accordingly, in the period T2, two of the transistors SWA and SWB, the first transistor SWA in the on state (here, the first transistors SWA (n) and SWA (n + 1)) and the first transistor in the on state. The second transistor SWB (here, the second transistor SWB (n + 1)) is electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2, and the first operation mode shown in FIG. Compared to, it will be three steps larger.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the fourth operation mode, of the transistors SWA and SWB, two on-state first transistors SWA and one on-state second transistor SWB are included in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by three levels. As a result, the dynamic range can be expanded by three levels. For example, when the ISO sensitivity setting value is three steps lower than the highest value, the imaging control unit 5 instructs the fourth operation mode to be performed.

  FIG. 8 is a timing chart showing a fifth operation mode of the solid-state imaging device 4 shown in FIG. In the fifth operation mode, each pixel block BL is sequentially selected for each row, and one of the first transistors SWA and 2 of the first transistors SWA and the second transistors SWB is turned on. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected while the two second transistors SWB in the on state are electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row.

  Similarly to FIG. 4, in FIG. 8, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The fifth operation mode shown in FIG. 8 is different from the first operation mode shown in FIG. 4 in the following points.

  In the fifth operation mode shown in FIG. 8, φSWA (n), φSWB (n + 1), φSWB (n + 2) are set to H and φSWA in a period T2 in which the pixel block BL (n) in the n-th row is selected. (N + 1), φSWA (n + 2), φSWB (n), φSWB (n + 3) are set to L, and the first transistor SWA (n) and the second transistors SWB (n + 1), SWB (n + 2) are turned on. At the same time, the first transistors SWA (n + 1) and SWA (n + 2) and the second transistors SWB (n) and SWB (n + 3) are turned off. Thus, in the period T2, one of the transistors SWA and SWB is turned on, the first transistor SWA in the on state (here, the first transistor SWA (n)) and the two second transistors SWB in the on state ( Here, the second transistors SWB (n + 1) and SWB (n + 2)) are electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2, which is more than the first operation mode shown in FIG. Increase by 3 levels.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the fifth operation mode, one of the transistors SWA and SWB is turned on by the first transistor SWA in the on state and the second transistor SWB in the on state of the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by three levels. As a result, the dynamic range can be expanded by three levels. For example, when the ISO sensitivity setting value is three steps lower than the highest value, the imaging control unit 5 instructs to perform the fifth operation mode.

  Here, the fourth operation mode shown in FIG. 7 is compared with the fifth operation mode shown in FIG. As described above, in the fourth operation mode, two on-state first transistors SWA and one on-state second transistor SWB among the transistors SWA and SWB are selected by the selected pixel block BL. The capacitance value of the charge-voltage conversion capacitance of the first node Pa is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2. On the other hand, in the fifth operation mode, of the transistors SWA and SWB, one on-state first transistor SWA and two on-state second transistors SWB are included in the first pixel block BL. The capacitance value of the charge-voltage conversion capacitor of the first node Pa is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2.

  Therefore, if the capacitance value Cfd1 of the capacitor CC and the capacitance value Cfd2 of the capacitor CD are the same, the first pixel block BL of the selected pixel block BL is used in both the fourth operation mode and the fifth operation mode. The capacity values of the nodes Pa are the same, and the dynamic range can be expanded to the same extent.

  However, as described above, while the capacitance value Cfd1 has voltage dependency, the voltage dependency of the capacitance value Cfd2 is negligible. Therefore, the voltage dependency of the capacitance value of the charge-voltage conversion capacitor of the first node Pa of the pixel block BL selected in the fifth operation mode is the amount of the voltage dependency of the capacitance value Cfd1 of one capacitor CC. Only, the voltage dependency of the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the pixel block BL selected in the fourth operation mode is smaller.

  Therefore, according to the fifth operation mode, compared to the fourth operation mode, it is possible to reduce the influence of the voltage dependency of the capacitance at the time of dynamic range expansion, and thus increase the linearity of photoelectric conversion. be able to.

  In the fifth operation mode, p transistors (p is an integer of 1 or more) of the first transistors SWA and q transistors (q of the second transistors SWB). Each of the first transistors SWB in the ON state is electrically connected to the first node Pa of the selected one pixel block BL. This is an example of an operation mode in which the transistor SWA and the second transistor SWB are controlled, and is an example in which p = 1 and q = 2. As can be understood from the above description, in this operation mode, when the value of p + q is an arbitrary predetermined value of 3 or more, an operation mode in which q ≦ p (p = 2 and an example of the operation mode) Compared with the fourth operation mode in which q = 1, it is possible to reduce the influence of the voltage dependency of the capacitance when expanding the dynamic range. The p may be an integer equal to or greater than 1. However, it is preferable that the value of p + q is the same because the smaller the p, the more the influence of voltage dependency on the capacity can be reduced. In particular, p = 1 is most preferable because the influence of the voltage dependency on the capacitance can be minimized.

  In the present embodiment, the second transistor SWB is provided between all the two second nodes Pb sequentially adjacent in the column direction. However, the present invention is not necessarily limited to this. For example, between r second nodes Pb arranged in the column direction (r is an integer of 2 or more) and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb, The second transistor SWB may be left open without being provided. In this case, the smaller the number of r, the lower the degree of expansion of the dynamic range, but the SN ratio at the time of high sensitivity reading can be improved. Further, for example, between s second nodes Pb arranged in the column direction (s is an integer of 4 or more) and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. May be short-circuited electrically without providing the second transistor SWB.

  Note that, for example, by adjusting the width of the wiring 72, the capacitance value of the capacitor CD may be set to a value within a range of ± 20% with respect to the capacitance value of the capacitor CC. The value may be within a range of ± 10%. This also applies to a second embodiment described later.

  Each of the operation examples described with reference to FIGS. 4 to 8 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of another pixel PX. Met. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed and read with the signal charge of the photodiode PD of another pixel PX of the same color.

  For example, the first transistor SWA (n−1), SWA (n), SWA (n + 1) and the second transistor SWB (n), SWB (n + 1) are turned on and the first node Pa (n−1) is turned on. , Pa (n), Pa (n + 1) are connected to each other, and TXA (n-1), TXA (n), TXA (n + 1) are turned on at the same time, the three of the same color in the case of assuming the Bayer arrangement etc. First signal charges of the photodiodes PDA (n−1), PDA (n), and PDA (n−1) of the pixels PXA (n−1), PXA (n), and PXA (n−1) are connected to each other. The nodes Pa (n−1), Pa (n), and Pa (n + 1) are averaged, and the same color three-pixel mixed readout function can be realized. At this time, the second transistors SWB (n−2) and SWB (n + 2) are turned off and are electrically connected to the first nodes Pa (n−1), Pa (n) and Pa (n + 1). The charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) by minimizing the number of first or second transistors in the ON state And the same color three-pixel mixed readout can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA (n−1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1), each first transistor SWA and each second transistor If one or more of the transistors SWB are electrically connected to the first nodes Pa (n−1), Pa (n), Pa (n + 1), Depending on the number, the charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) increases, and the dynamic range of the same color three-pixel mixed readout is expanded. Can do.

[Second Embodiment]
FIG. 9 is a circuit diagram showing a schematic configuration of the solid-state imaging device 84 of the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. 9, elements that are the same as or correspond to elements in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment is different from the first embodiment in that the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the first embodiment. The pixel block BL is a pixel PXA. However, in the present embodiment, the density in the column direction of the photodiode PDA is set to be twice the density in the column direction of the photodiode PDA in the first embodiment, and the photodiode in the first embodiment. The density in the column direction of the entire PDA and PDB is the same. In the present embodiment, n indicates the row of the pixel block BL and simultaneously indicates the row of the pixel PXA.

  In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is one. Pixel PX (PXA). In the first embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share one set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in this embodiment, only PXA) has a set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. doing.

  Basically, the description of the first embodiment is applicable as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  As mentioned above, although each embodiment and modification of this invention were demonstrated, this invention is not limited to these.

4 solid-state imaging device BL pixel block PX pixel PD photodiode TXA, TXB transfer transistor Pa first node Pb second node AMP amplification transistor SWA first transistor SWB second transistor

Claims (8)

A plurality of pixel blocks having one photoelectric conversion unit, a first node, and one transfer switch provided corresponding to the one photoelectric conversion unit and transferring charges from the photoelectric conversion unit to the first node When,
Three or more second nodes respectively corresponding to the first nodes of three or more pixel blocks;
Three or more first switch units that electrically connect and disconnect between the first node of the three or more pixel blocks and the three or more second nodes, respectively;
A plurality of second switch units connecting the three or more second nodes, each electrically connecting and disconnecting between the two second nodes;
A solid-state imaging device comprising:   The solid-state imaging device according to claim 1, wherein the plurality of second switch units connect the three or more second nodes in a daisy chain.   In the predetermined operation mode, p (p is an integer of 1 or more) of the first switch units in the first switch units and q (q is the number of the second switch units). the second switch unit in the ON state (an integer greater than p) is electrically connected to the first node of one pixel block of the three or more pixel blocks. The solid-state imaging device according to claim 1, further comprising a control unit that controls each of the first switch units and each of the second switch units.   The solid-state imaging device according to claim 3, wherein the p is 1.   The controller electrically connects between the first node of one pixel block of the three or more pixel blocks and the second node corresponding thereto in another predetermined operation mode. 5. The first switch unit of the one pixel block among the three or more pixel blocks is controlled so that the first switch unit to be disconnected is turned off. The solid-state imaging device according to any one of the above.   6. The solid-state imaging device according to claim 1, wherein each of the pixel blocks includes a plurality of the photoelectric conversion units and the transfer switches.   An imaging apparatus comprising the solid-state imaging device according to claim 1.   8. The imaging apparatus according to claim 7, further comprising control means for switching between the predetermined operation mode and the other predetermined operation mode in accordance with a set value of ISO sensitivity.

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