JP7135167B2 - Imaging element and imaging device - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

2. Description of the Related Art Imaging apparatuses such as digital cameras and digital video cameras that use CMOSAPS (Complementary Metal Oxide Semiconductor Active Pixel Sensor) as an imaging device to record captured images have been developed. The imaging device has a pixel section and a peripheral circuit section. The peripheral circuit section reads the signals from the pixels and outputs them to the outside as image signals. A pixel portion performs photoelectric conversion with a photodiode, and a signal obtained by photoelectric conversion is read out to a peripheral circuit portion by a pixel circuit formed in the pixel portion.

In recent years, with the miniaturization of pixels, the number of circuits in pixels has been reduced as much as possible and the area of photodiodes has been increased to ensure the performance of imaging devices. In addition, the area of the peripheral circuit portion is becoming larger as the function is improved. Therefore, techniques for forming the pixel portion and the peripheral circuit portion on different chips are being developed. For example, in Japanese Unexamined Patent Application Publication No. 2002-100000, a pixel is made up of only a photodiode and some switches, and the other switches are configured on a separate chip.

FIG. 27 is a diagram for explaining a schematic configuration of a conventional imaging device.

The image sensor includes a pixel portion 101′, a vertical selection circuit 102′ that selects a row in the pixel portion 101′, and signals of pixels in a row selected by the vertical selection circuit 102′ among the pixels in the pixel portion 101′. It has a column circuit 103' for processing. Further, the image pickup device includes a column memory 104' that holds the signals processed by the column circuit 103' for each column, a horizontal selection circuit 105' that selects a column of signals held in the column memory 104', and a horizontal selection circuit 105'. has an output signal line 106' for reading out the signal of the column selected in ' to the output circuit 107'. In addition to the illustrated components, the imaging device includes, for example, a timing generator for providing timing signals to the vertical selection circuit 102', the horizontal selection circuit 105', the column circuit 103', and the like, a control circuit, and the like.

The vertical selection circuit 102' sequentially selects a plurality of rows of the pixel section 101' and outputs the selected signal to the column memory 104' via the column circuit 103'. The horizontal selection circuit 105' sequentially selects the signals held in the column memory 104' and outputs them to the output circuit 107' via the output signal line 106'. The pixel unit 101' is configured by arranging a plurality of pixels in a two-dimensional array to provide a two-dimensional image. These circuits are formed on a single semiconductor substrate, and along with miniaturization of the semiconductor process, reduction in pixel spacing and reduction in the area of peripheral circuits are being carried out.

FIG. 28 is a diagram showing the configuration of one pixel in a conventional imaging device and the configuration of a circuit for reading out signals from the pixel.

As shown in FIG. 28, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201' includes a photodiode (hereinafter also referred to as "PD") 202', a transfer switch 203', a floating diffusion section (hereinafter also referred to as "FD") 204', a reset switch 207', an amplification MOS amplifier 205', a selection It is configured to include a switch 206'.

The PD 202' functions as a photoelectric conversion element that photoelectrically converts light incident through the optical system to generate charges. The anode of PD 202' is connected to the ground line and the cathode is connected to the source of transfer switch 203'. The transfer switch 203' is driven by a transfer pulse .phi.TX input to its gate terminal, and transfers charges generated in the PD 202' to the FD 204'. The FD 204' functions as a charge-voltage converter that temporarily accumulates charges and converts the accumulated charges into voltage signals.

The amplifying MOS amplifier 205' functions as a source follower, and the signal subjected to charge-voltage conversion by the FD 204' is input to its gate. The amplifying MOS amplifier 205' has a drain connected to the first power supply line VDD1 that supplies the first potential, and a source connected to the selection switch 206'. The selection switch 206' is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205', and its source is connected to the vertical signal line (column signal line) 208'. . When the vertical selection pulse φSEL becomes active level (high level), the selection switch 206′ of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplifying MOS amplifier 205 is connected to the vertical signal line 208′. .

The reset switch 207' has a drain connected to a second power supply line VDD2 that supplies a second potential (reset potential) and a source connected to the FD 204'. Further, the reset switch 207' is driven by a reset pulse φRES input to its gate to remove the charges accumulated in the FD 204'.

In addition to the FD 204' and the amplifying MOS amplifier 205', a constant current source 209' that supplies a constant current to the vertical signal line 208' constitutes a floating diffusion amplifier. In each pixel constituting the row selected by the selection switch 206', the charge transferred from the PD 202' to the FD 204' is converted into a voltage signal by the FD 204', and the vertical signal line provided for each column through the floating diffusion amplifier. (column signal line) 208'.

A column circuit 103' connected to each vertical signal line (column signal line) 208' is composed of a CDS (correlated double sampling) circuit, a gain amplifier, and the like. Also, the column circuits 103' are formed of circuits having the same configuration for each column. The signals processed by column circuits 103' are held in corresponding column memories 104'. A signal held in the column memory 104' is transferred to the output circuit 107' via the output signal line 106'. The output circuit 107' performs amplification, impedance conversion, and the like on the input signal, and outputs the signal to the outside of the image sensor.

Japanese Patent Application Laid-Open No. 2008-211220

However, in Patent Literature 1, a floating diffusion (FD), which has a weak signal amount among pixels, is used for connection between chips, so variations in the manufacture of the FDs result in variations in the capacitance values of the FDs. As a result, PRNU (photo response non-uniformity) and DSNU (dark signal non-uniformity) are caused. In addition, although Patent Document 1 does not describe the arrangement of the readout circuit, since the pixel portion and the peripheral circuit portion are formed on separate chips, it is desirable to arrange the readout circuit more efficiently than in the past. In addition, recently, circuits for realizing a plurality of functions, such as an AD converter for each column, have been introduced into the peripheral circuits, resulting in an increase in the chip area of the peripheral circuits. As a result, the heat generated in the peripheral circuit not only generates a dark current in the PD 202' of the pixel, but also causes the dark current to become uneven within the screen corresponding area if the peripheral circuit arrangement is biased. A problem arises.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image pickup device and an image pickup apparatus that do not impair the performance of a pixel section and that can suppress an increase in the chip area of peripheral circuits to suppress an increase in cost.

It is another object of the present invention to suppress an increase in chip area by efficiently arranging peripheral circuits without impairing the performance of the pixel portion in an imaging device in which a pixel portion and a peripheral circuit portion are formed in separate regions. It is also an object of the present invention to provide an imaging element and an imaging apparatus in which non-uniformity of dark current within a screen-corresponding area due to heat generation of peripheral circuits is suppressed.

In order to achieve the above object, an imaging device according to claim 1 comprises a first semiconductor substrate and a second semiconductor substrate which are laminated to each other, a pixel section in which a plurality of pixels are arranged in a matrix, and a driving circuit that drives a pixel portion; a plurality of signal processing circuits that are provided for each of a plurality of pixels of a predetermined unit in the pixel portion and perform predetermined signal processing on signals output from the plurality of pixels of the predetermined unit; and a plurality of output circuits for outputting to the outside signals that have been subjected to predetermined signal processing by the plurality of signal processing circuits, wherein the pixel section and at least part of the driving circuit are the first The plurality of signal processing circuits and the plurality of output circuits are formed in a region of the first semiconductor substrate, and the plurality of signal processing circuits and the plurality of output circuits are formed in a region of the second semiconductor substrate. 1. The plurality of signal processing circuits are arranged at positions overlapping with the pixel section, and the plurality of output circuits are arranged at positions not overlapping with the pixel section.

In order to achieve the above object, the image pickup device according to claim 5 includes a first semiconductor substrate and a second semiconductor substrate which are laminated to each other, and a pixel section in which a plurality of pixels are arranged in a matrix. a driving circuit for driving the pixel portion; and a plurality of signal processing circuits provided for each of a plurality of pixels of a predetermined unit in the pixel portion and performing predetermined signal processing on signals output from the plurality of pixels of the predetermined unit. and a plurality of output circuits for outputting to the outside signals subjected to predetermined signal processing by the plurality of signal processing circuits, wherein the pixel section and at least part of the driving circuit are The plurality of signal processing circuits and the plurality of output circuits are formed in the region of the first semiconductor substrate, and the plurality of signal processing circuits and the plurality of output circuits are formed in the region of the second semiconductor substrate. an image pickup device in which the plurality of signal processing circuits are arranged at positions overlapping with the pixel portion and the plurality of output circuits are arranged at positions not overlapping with the pixel portion; and a signal output from the image pickup device. a recording unit for recording on a recording medium, a display unit for displaying an image based on the signal output from the imaging device, and a controller for controlling the entire device including the imaging device, the recording unit, and the display unit. It is characterized by having

According to the present invention, it is possible to suppress an increase in cost due to an increase in the chip area of peripheral circuits without impairing the performance of the pixel portion.

Further, according to the present invention, it is possible to efficiently and efficiently arrange the peripheral circuits without impairing the performance of the pixel portion, and to suppress the non-uniformity of the dark current within the screen corresponding area due to the heat generated by the peripheral circuits. becomes possible.

1 is a block diagram for explaining the overall configuration of an imaging device according to a first embodiment of the present invention; FIG. FIG. 2 is a diagram showing a pixel and a circuit configuration for reading out signals from the pixel in the image sensor according to the first embodiment; 3 is a diagram showing a modification of the circuit configuration of FIG. 2; FIG. 3 is a diagram showing another modification of the circuit configuration of FIG. 2; FIG. 1 is a diagram showing a cross-sectional structure of an imaging device according to a first embodiment; FIG. 2 is a block diagram showing a modification of the overall configuration of the imaging element shown in FIG. 1; FIG. 3 is a block diagram showing another modification of the overall configuration of the imaging element shown in FIG. 1; FIG. It is a figure showing the cross-sectional structure of the image pick-up element based on the 2nd Embodiment of this invention. 3 is a block diagram showing still another modification of the overall configuration of the imaging element shown in FIG. 1. FIG. 1 is a diagram showing a schematic configuration of a digital camera, which is an example of an imaging device equipped with an imaging device according to any one of the first and second embodiments and modifications thereof; FIG. FIG. 10 is a diagram showing the configuration of one pixel and the configuration of a circuit for reading a signal from the pixel in an image sensor according to a third embodiment of the present invention; FIG. 12 is a diagram showing a modification of the circuit configuration of the imaging device of FIG. 11; FIG. 12 is a diagram showing another modification of the circuit configuration of the imaging device of FIG. 11; It is the figure which looked down on the whole structure of the image pick-up element of 3rd Embodiment from the top. FIG. 11 is a cross-sectional view of an imaging device of a modified example of the third embodiment; It is the figure which looked down on the whole structure of the imaging device of the 5th Embodiment of this invention from the top. It is the figure which looked down at the whole structure modification of the image pick-up element of 5th Embodiment from the top. FIG. 20 is a top view of another modification of the overall configuration of the image sensor according to the fifth embodiment; It is the figure which looked down on the whole structure of the imaging device of the 6th Embodiment of this invention from the top. FIG. 20 is a top view of a modification of the overall configuration of the imaging device according to the sixth embodiment; FIG. 20 is a top view of another modification of the overall configuration of the imaging device according to the sixth embodiment; It is the figure which looked down on the whole structure of the image pick-up element of the 7th Embodiment of this invention from the top. It is the figure which looked down on the whole structure of the image pick-up element of the 8th Embodiment of this invention from the top. It is the figure which looked down on the whole structure of the image pick-up element of the 9th Embodiment of this invention from the top. FIG. 20 is a top view of a modification of the overall configuration of the imaging device according to the ninth embodiment; FIG. 22 is a top view of another modified example of the overall configuration of the imaging device according to the ninth embodiment; It is a figure for demonstrating schematic structure of the conventional imaging device. It is a figure which shows the structure of 1 pixel in the conventional image pick-up element, and the structure of the circuit which reads a signal from the pixel.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining a schematic configuration of an imaging device according to a first embodiment of the invention. In practice, it is assumed that area 1 and area 2 shown in the drawing overlap in the vertical direction.

In FIG. 1, the image sensor includes a pixel portion 101, a vertical selection circuit 102 that selects a row in the pixel portion 101, and a pixel signal of a row selected by the vertical selection circuit 102 among the pixels in the pixel portion 101. has a column circuit 103 for performing the processing of Further, the image sensor includes a column memory 104 that holds the signals processed by the column circuit 103 for each column, a horizontal selection circuit 105 that selects the signals held in the column memory 104, and a column selected by the horizontal selection circuit 105. It has an output signal line 106 for reading out to an output circuit 107 . In addition to the components shown in the drawing, the image pickup device includes, for example, a timing generator 1007, which provides timing to the vertical selection circuit 102, the horizontal selection circuit 105, the column circuit 103, and the like, a control circuit 1009, a DA conversion circuit, and the like. However, they do not need to be provided on the same substrate as the imaging device, and the timing generator 1007 and the control circuit 1009 are provided separately from the imaging device as shown in FIG. good too.

The vertical selection circuit 102 sequentially selects a plurality of rows of the pixel section 101 and outputs signals of the selected rows to the column memory 104 via the column circuit 103 . The horizontal selection circuit 105 sequentially selects the signals held in the column memory 104 and outputs them to the output circuit 107 via the output signal line 106 . The pixel unit 101 is configured by arranging a plurality of pixels in a two-dimensional array to provide a two-dimensional image.

A pixel portion 101, a vertical selection circuit 102, and an output circuit 107 included in region 1 are formed on a first semiconductor substrate. On the other hand, column circuits 103, column memories 104, horizontal selection circuits 105, and output signal lines 106 included in region 2 are formed on the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are separately formed, and are mounted in the same package by connecting wires that require electrical connection and laminating them. That is, when viewed from the upper surface of the package of the imaging device (the light incident surface side of the pixel section 101), the pixel section 101 formed in the region 1 of the first semiconductor substrate and the region 2 of the second semiconductor substrate are arranged below the pixel section 101. The formed column circuit 103, column memory 104, horizontal selection circuit 105, and output signal line 106 are located at overlapping positions. If the timing generator 1007, the control circuit 1009, the DA converter, etc. are arranged in the area 2 under the vertical selection circuit 102 and the output circuit 107 in the area 1, the area efficiency is good. In addition, although a configuration including a first semiconductor substrate and a second semiconductor substrate will be described as an example in a plurality of embodiments described below, the configuration is not limited to this, and a configuration including another semiconductor substrate may be used. .

FIG. 2 is a diagram showing the configuration of one pixel in the image sensor according to the first embodiment and the configuration of a circuit for reading out signals from the pixel.

As shown in FIG. 2, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201 includes a photodiode (hereinafter also referred to as "PD") 202, a transfer switch 203, a floating diffusion section (hereinafter also referred to as "FD") 204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206. Configured. A reset switch 207 functions as a reset unit.

The PD 202 functions as a photoelectric conversion element that photoelectrically converts light incident through the optical system to generate charges. The PD 202 has an anode connected to the ground line and a cathode connected to the source of the transfer switch 203 . A transfer switch (transfer unit) 203 is driven by a transfer pulse φTX input to its gate terminal, and transfers charges generated in the PD 202 to the FD 204 . The FD 204 functions as a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into voltage signals.

An amplifying MOS amplifier (amplifying section) 205 is composed of an amplifying circuit such as a MOSFET, functions as a source follower, and receives a signal charge-voltage converted by the FD 204 at its gate. The amplifying MOS amplifier 205 has a drain connected to the first power supply line VDD1 that supplies the first potential, and a source connected to the selection switch 206 . The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205 , and its source is connected to the vertical signal line 208 . When the vertical selection pulse φSEL becomes active level (high level), the selection switch 206 of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplifying MOS amplifier 205 is connected to the vertical signal line 208 .

The reset switch (reset unit) 207 has a drain connected to a second power supply line VDD2 that supplies a constant second potential (reset potential), and a source connected to the FD204. Also, the reset switch 207 is driven by a reset pulse φRES input to its gate, and removes the charge accumulated in the FD 204 . φTX, φSEL, and φRES are supplied from vertical select circuit 102 .

In addition to the FD 204 and the amplifying MOS amplifier 205, a constant current source 209 that supplies a constant current to the vertical signal line 208 constitutes a floating diffusion amplifier. In each pixel constituting the row selected by the selection switch 206, the charge transferred from the PD 202 to the FD 204 is converted into a voltage signal by the FD 204 and applied to a vertical signal line (column signal line) provided for each column through a floating diffusion amplifier. ) 208 .

A column circuit 103 connected to each vertical signal line (column signal line) 208 is composed of a CDS (correlated double sampling) circuit, a gain amplifier, and the like. The CDS circuit subjects the signal output to the vertical signal line 208 to correlated double sampling processing. Also, the gain amplifier amplifies the signal output to the vertical signal line 208 with a predetermined amplification factor. Also, the column circuit 103 is formed by a circuit having the same configuration for each column. The signals processed by the column circuit 103 are held in the corresponding column memories 104, respectively. A signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106 . The output circuit 107 performs amplification, impedance conversion, and the like on the input signal, and outputs the signal to the outside of the image sensor.

The column circuit 103, the column memory 104, and the output circuit 107 may have the circuit configuration described above, but the column circuit 103 may be of a type having an AD converter for each column. In that case, the column circuit 103 has an AD converter in addition to the CDS circuit and gain amplifier. The column memory 104 at that time is a digital (digital signal) memory, and the output circuit 107 includes components such as an LVDS (Low Voltage Differential Signaling) driver.

The illustrated region 1, that is, the first semiconductor substrate, is configured to include a PD 202, a transfer switch 203, an FD 204, a reset switch 207, an amplification MOS amplifier 205, a selection switch 206, and an output circuit 107 provided for each pixel. It is

The illustrated region 2, that is, the second semiconductor substrate, is configured to include a vertical signal line 208, a constant current source 209, a column circuit 103, a column memory 104, and an output signal line 106 provided for each column. . Note that the vertical signal line (column signal line) 208 is a wiring that connects the pixel portion 101 and the column circuit 103 and may be included in either region 1 or region 2 . Also, the selection switch 206 may be included in region 2 .

Also, the constant current source 209 may be in region 1 as in the modification of the circuit configuration shown in FIG. However, in this case, since the constant current source 209 is arranged on the same substrate as the pixels, the area efficiency is not so good. This is effective only when the area of the column circuit 103, the column memory 104, the output signal line 106, etc. is larger than the area of the pixel portion.

Further, as in another modification of the circuit configuration shown in FIG. 4, a configuration without the selection switch 206 may be used. In a configuration without the selection switch 206, a selected row and a non-selected row are set by controlling ΦRES and the potential of the second power supply line VDD2.

FIG. 5 is a diagram showing the cross-sectional structure of the imaging device according to the first embodiment of the present invention. It shows a structure in which a region 1 representing a first semiconductor substrate is stacked over a region 2 representing a second semiconductor substrate. The same symbols are attached to the same components as those shown in FIG.

A region 1 representing a first semiconductor substrate is formed on a semiconductor substrate 501 . The region 1 includes a first conductivity type region 502 , a PD region 202 , and a first conductivity type region 503 for suppressing dark current of the PD 202 . It also has a transfer switch 203 , an FD 204 and an amplification MOS amplifier 205 . In addition, a reset switch 207 is also included.

Further, an element isolation region 504 , a wiring layer 505 formed in multiple layers, and an interlayer film 506 between the multilayer wiring layers 505 are provided. The through holes 507 electrically connect the wirings. Since the region 1 includes a pixel portion, it also includes a color filter 508 for color separation and a microlens 509 for condensing light.

A region 2 representing a second semiconductor substrate as a semiconductor substrate other than the first semiconductor substrate is formed on a semiconductor substrate 510 . Each circuit of the column circuit 103 is formed by a plurality of types of switches in each switch group 511 . Region 2 also includes column memories 104, output signal lines 106, and the like. A connection point 115 of the vertical signal line 208 electrically connects the regions 1 and 2 with a microbump or the like. In addition to the connection points 115 of the vertical signal lines 208, wirings for supplying power and various driving pulses are connected to each other at connection points 512 such as microbumps. In the present embodiment, the first semiconductor substrate in which the light-receiving portion is formed is illustrated as being of the backside illumination type, but the first semiconductor substrate may be of the frontside illumination type instead of the backside illumination type.

In this embodiment, as shown in FIG. 1, the pixel portion 101, the vertical selection circuit 102, and the output circuit 107 are formed in the region 1, and the other driver circuits are arranged in the region 2. However, it is not limited to this. do not have. For example, the output circuit 107 may be arranged in the area 2 as in the modification of the overall configuration of the image sensor in FIG.

Further, as shown in another modified example of the overall configuration of the imaging device in FIG. 7, a part of the vertical selection circuit 102 may be arranged in the region 1 and the rest of the vertical selection circuit 102 may be arranged in the region 2. FIG. Also, in that case, by arranging them in substantially the same place when viewed from above, the area efficiency can be improved. That is, in the present invention, if at least the transfer switch 203, the FD 204, the reset switch 207, and the amplification MOS amplifier 205 are in the region 1 so as not to divide the FD 204 into the regions 1 and 2 in the pixel section 101, good. Other drive circuits may be arranged in either region 1 or region 2 depending on the area efficiency of the semiconductor substrate.

In the above embodiment, as shown in FIG. 5, the region 1 is the first semiconductor substrate and the region 2 is the second semiconductor substrate. may be formed on a semiconductor substrate.

FIG. 8 is a diagram showing a cross-sectional structure of an imaging device according to a second embodiment of the present invention. The same components as those shown in FIG. 2 and those shown in FIG.

In the second embodiment shown in FIG. 8, regions 1 and 2 are formed on the front surface (first surface or second surface) and back surface (first surface or second surface) of a semiconductor substrate 501, respectively. . In this embodiment, the side on which the region 1 is formed is the front surface, and the side on which the region 2 is formed is the back surface. The protective layer 801 protects the wiring layer 505 on the back surface. A plug 802 electrically connects the front surface and the back surface.

Further, in the above embodiment, the region 1 and the region 2 have been described, but the number of regions is not limited to two, and each component may be arranged by dividing into a plurality of regions. For example, as in the modification shown in FIG. 9, the pixel portion 101 and the vertical selection circuit 102 may be formed in the region 1, and the remaining driving circuits may be divided into the regions 2 and 3 and formed. . In the illustrated example, the remainder of the vertical selection circuit 102 and the column circuit 103 are formed in the region 2, and the remainder of the column circuit 103 and other driving circuits are separately formed in the region 3. FIG. In this way, by separately arranging each component over a plurality of regions, an AD converter or the like can be mounted for each column, and the increasing number of column circuits 103 can be effectively arranged. Note that the regions 1, 2, and 3 may be formed on separate semiconductor substrates.

FIG. 10 is a diagram showing a schematic configuration of a digital camera, which is an example of an imaging device equipped with an imaging device according to any one of the above-described embodiments and modifications.

In FIG. 10, a lens unit 1001 that forms an optical image of a subject on a solid-state imaging device (imaging device according to any of the embodiments and modifications) 1005 performs zoom control, focus control, and aperture control by a lens driving device 1002. etc. A mechanical shutter 1003 is controlled by a shutter control unit 1004 . A solid-state imaging device 1005 converts the subject image formed by the lens unit 1001 into an image signal and outputs the image signal. The imaging signal processing circuit 1006 performs various corrections on the image signal output from the solid-state imaging device 1005 and compresses the data.

A timing generator 1007 is a driving unit that outputs various timing signals to the solid-state imaging device 1005 and the imaging signal processing circuit 1006 . A control circuit 1009 controls various calculations and the entire imaging apparatus. A memory 1008 temporarily stores image data. A recording medium control interface 1010 performs recording or reading on a removable recording medium 1011 such as a semiconductor memory. A display unit 1012 displays various information and captured images.

Next, a description will be given of the operation of the digital camera having the above-described configuration during photographing.

When a main power supply (not shown) is turned on, the power supply of the control system is turned on, and further, the power supply of the imaging system circuits such as the imaging signal processing circuit 1006 is turned on. Subsequently, when a release button (not shown) is pressed, the control circuit 1009 extracts high frequency components based on the signal output from the distance measuring device 1014 and calculates the distance to the subject. After that, the lens unit 1001 is driven by the lens driving device 1002 to determine whether or not the object is in focus. Then, after the in-focus state is confirmed, the photographing operation is started.

When the photographing operation is completed, the image signal output from the solid-state imaging device 1005 is image-processed by the imaging signal processing circuit 1006 and written to the memory 1008 by the control circuit 1009 . The data stored in the memory 1008 passes through the recording medium control I/F unit 1010 under the control of the control circuit 1009 and is recorded in a removable recording medium 1011 such as a semiconductor memory. Note that the image may be processed by directly inputting it to a computer or the like through an external I/F section (not shown).

FIG. 11 is a diagram showing the configuration of one pixel in the image sensor according to the third embodiment of the present invention and the circuit configuration for reading out signals from the pixel. Region 1 is a chip having circuits formed on a first semiconductor substrate, and region 2 is a chip having circuits formed on a second semiconductor substrate.

Region 1 mainly contains pixels 201 and region 2 mainly contains column circuits for processing signals from pixels 201 .

A region 1 is configured by arranging a plurality of pixels 201 in a two-dimensional array as a pixel array that provides a two-dimensional image. Each pixel 201 includes a photodiode (hereinafter also referred to as PD) 202, a transfer switch 203, a floating diffusion section (hereinafter also referred to as FD) 204, an amplifying MOS amplifier 205, a selection switch 206, and a reset switch 207. sell.

The PD 202 functions as a photoelectric conversion unit that photoelectrically converts light incident through the optical system to generate charges. The PD 202 has an anode connected to the ground line and a cathode connected to the source of the transfer switch 203 . A transfer switch 203 as a transfer unit is driven by a transfer pulse φTX input to its gate terminal, and transfers charges generated in the PD 202 to the FD 204 . The FD 204 functions as a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into voltage signals.

The amplifying MOS amplifier 205 functions as a source follower, and the signal subjected to charge-voltage conversion by the FD 204 is input to its gate. The amplifying MOS amplifier 205 has a drain connected to the first power supply line VDD1 that supplies the first potential, and a source connected to the selection switch 206 . The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205 , and its source is connected to the vertical signal line 208 . When the vertical selection pulse φSEL becomes active level (high level), the selection switch 206 of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplifying MOS amplifier 205 is connected to the vertical signal line 208 . A vertical signal line 208 is shared by a plurality of pixels 201 sharing a column.

The reset switch 207 has a drain connected to a second power supply line VDD2 that supplies a second potential (reset potential), a source connected to the FD 204, and a gate driven by a reset pulse φRES. , removes the charge accumulated in the FD 204 .

The FD 204, the amplifying MOS amplifier 205, and a constant current source 209 that supplies a constant current to the vertical signal line 208 constitute a floating diffusion amplifier. In each pixel constituting the row selected by the selection switch 206, the charge transferred from the PD 202 to the FD 204 is converted into a voltage signal by the FD 204 and applied to a vertical signal line (column signal line) provided for each column through a floating diffusion amplifier. ) 208 . φTX, φSEL, and φRES are supplied from a vertical selection circuit which will be described later.

A column circuit 103 connected to each vertical signal line (column signal line) 208 is composed of a column amplifier 110 and the like. The column circuit 103 is formed of a circuit having the same configuration as each column. Column circuit 103 may have a configuration of only column amplifier 110 shown in FIG. 11, or may have a configuration including a CDS (correlated double sampling) circuit or the like.

The signals that have undergone various processing in the column circuits 103 are held in the corresponding column memories 104 . A signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106 . An output circuit 107 performs amplification, impedance conversion, and the like, and outputs a signal to the outside of the imaging element.

Region 1 and region 2 are electrically connected via connection point 115 of vertical signal line (column signal line) 208 . By placing the connection point 115 after the MOS amplifier 205 as shown in FIG. 11, PRNU and DSNU can be reduced. The constant current source 209 may be in region 2 or may be in region 1 .

FIG. 12 is a diagram showing a modification of the imaging device circuit of FIG.

In FIG. 12, column AD 111 is mounted after column amplifier 110 . A column AD 111 is an AD converter for each column and performs AD conversion. In this case, the column circuit 103 is composed of a column amplifier 110 and a column AD111. Moreover, the CDS circuit etc. which were mentioned above may be included. For configurations with column ADs 111, column memory 104 is a digital memory and output circuit 107 also includes components such as LVDS drivers.

Further, as in another modified example shown in FIG. 13, a configuration without the selection switch 206 may be used.

FIG. 14 is an overhead view of the outline of the imaging element of the third embodiment. Region 1 and region 2 are chips formed on different semiconductor substrates, respectively, and are mounted in the same package by connecting wiring that requires electrical connection. That is, when looking down from the upper surface of the package, the region 2 is arranged under the region 1 so as to overlap therewith.

In the region 1, pixels 201 are formed in an array in multiple rows and multiple columns. The aforementioned φTX, φSEL, and φRES for driving the pixels 201 are supplied from the vertical selection circuit 102 for each row. A vertical signal line 208 for extracting signals from pixels is shared by pixels in the same column. Here, the vertical signal lines 208 of the 1st to 4th columns are indicated as 208_1, 208_2, 208_3, and 208_4, respectively. Regions 1 and 2 have connection points 115 for connecting vertical signal lines 208 to column circuitry 103 . A connection point 115 that the vertical signal line 208_1 has is indicated as 115_1. Also, the column circuit 103 connected to the vertical signal line 208_1 is indicated as 103_1, and the column memory 104 connected to the column circuit 103_1 is indicated as 104_1. Region 2 has a horizontal selection circuit 105 for transferring the signal of the column memory 104 to the output circuit 107 . The horizontal selection circuit 105 transfers the signals of the column memory 104 to the output circuit 107 in time series.

Although not shown, either region 1 or region 2 has the above-described constant current source 209 in addition to the illustrated components. A constant current source 209 may be included in the column circuit 103 . In addition, for example, it has a timing generator or control circuit that provides timing to the vertical selection circuit 102, the horizontal selection circuit 105, the column circuit 103, etc., a serial communication interface, a DA converter, and the like.

Since various pulses are supplied to the horizontal selection circuit 105 from a timing generator or the like, it is desirable that the horizontal selection circuit 105 be located near the edge of the chip. As shown in FIG. 14, by bringing the connection point 115 near the center in the column direction, the horizontal selection circuit 105 can be arranged in the vertical direction. It should be noted that the connection points 115 can also be brought near the periphery in the column direction.

The cross-sectional structure of the imaging device according to this embodiment is substantially the same as that of the first embodiment shown in FIG. 5, so illustration and description are omitted.

As shown in FIG. 14, the connection point 115 is shared by the pixels in each column on each vertical signal line (column signal line). Since there are few, it becomes possible to solve the problem that the yield is reduced due to defective formation of connection points. Of course, there may be several connection points instead of one connection point in consideration of yield. In this embodiment, the vertical signal lines on the region 1 side share the pixels, thereby eliminating the need to connect the regions 1 and 2 for each pixel.

Here, although the first semiconductor substrate in which the light-receiving portion is formed is of the backside illumination type, the first semiconductor substrate may be of the frontside illumination type instead of the backside illumination type. FIG. 15 is a diagram showing a cross-sectional structure of a surface irradiation type modification of the present embodiment. It shows a structure in which a region 1 representing a first semiconductor substrate is stacked on a region 2 representing a second semiconductor substrate. The description of the components with the same reference numerals as those in FIG. 5 is omitted. In the case of the front illumination type, the microlens 509 is placed above the wiring 505 with respect to the semiconductor substrate 501 . A through via 601 is formed to connect the connection point 115 and the components of the region 1 in the case of the front illumination type.

Since the cross-sectional structure of the fourth embodiment of the present invention in which the front irradiation type regions 1 and 2 are formed on the same substrate 501 is substantially the same as that of the second embodiment shown in FIG. Although illustration and description are omitted, in this case, the connection point 115 becomes the through via 601 to connect the vertical signal line 208 and the circuit on the back side, as described above.

FIG. 16 is a top view of the overall configuration of an imaging device according to the fifth embodiment of the present invention. 17 and 18 are diagrams respectively showing the modifications thereof.

Unlike the diagram shown in FIG. 14, in the overall configuration of the image pickup device according to the fifth embodiment shown in FIG. It is possible to arrange the connection point 115 in the immediate vicinity of the . As a result, the wiring length in region 2 can be shortened, and the column circuits 103 and the like can be arranged more efficiently.

In the modification of FIG. 17, by shifting the connection points 115_1, 115_2, 115_3, and 115_4, it is possible to sparsely arrange the column circuits 103_1 to 110_4. As shown in FIG. 14, when the column circuits 103 are arranged unevenly in the screen corresponding area, the heat generation of the column circuits 103 is concentrated, and the PD 202 receiving the heat from the column circuits 103 causes the image to be captured within the screen corresponding area of the photographed image. Non-uniformity of dark current occurs. However, by adopting a configuration such as that shown in FIG. 17, for example, uniform arrangement, it is possible to reduce non-uniformity of dark current due to heat generation of the column circuits 103 within the screen corresponding area. In FIG. 17, the column circuits 103 are distributed by reversing the arrangement of the column circuit 103_1 and column memory 104_1 and the column circuit 103_3 and column memory 104_3. Therefore, the output signal line 106 is arranged also in the center in the direction along the column. However, in the case as shown in FIG. 18 where the column circuit 103 and the column memory 104 can be sufficiently small, this is not necessary, and the column circuits 103_1 and 103_3 may be arranged in the same direction.

As described above, by shifting the connection points 115 for each column, an efficient layout and a layout that reduces the influence of heat generated by the column circuits 103 can be achieved.

FIG. 19 is a top view of the overall configuration of an imaging device according to the sixth embodiment of the present invention. 20 and 21 are diagrams respectively showing the modifications thereof.

14, 16, 17 and 18, the column circuit 103 and the column memory 104 are described as circuits having a width of two columns in the direction along the row, but the present invention can take other configurations. , but not limited to that configuration. For example, as shown in FIG. 19, the circuit may have a width of one column along the row. However, the column circuit 103 and the column memory 104 become circuits whose lengths increase in the direction along the columns, making them even longer in the vertical direction. Since the column circuit 103 and the column memory 104 are separated from the adjacent column circuit 103 and column memory 104 by the element isolation region, the area efficiency is better when they are formed in a region closer to a square. The modified example of FIG. 20 has a width of four columns in the row direction. Although it looks horizontally long in the schematic diagram, such a layout is also possible by shifting the connection points 115 for each column in order to make it closer to a square. By increasing the widths of the column circuits 103 and the column memories 104 in the row direction, as shown in the modification of FIG. 21, it is possible to arrange a plurality of output signal lines 106 . Since the output signal lines 106 do not consume power, increasing the number of output signal lines 106 and arranging them between the column circuit 103 and the column memory 104 makes it possible to disperse heat generation.

FIG. 22 is a top view of the overall configuration of an imaging device according to the seventh embodiment of the present invention. The layout of FIG. 22 is based on the same concept as that of FIG. 17, but if the column circuits 103 and column memories 114 are small, there will be gaps between the circuits. Digital circuitry 1401 can be present if a column AD as shown in FIG. 12 is implemented. The digital circuit 1401 can also perform various types of correction processing such as gamma correction processing and image processing such as white balance adjustment on the signals from the column memory 104 . 17 and 21, by distributing the column circuits 103, the digital circuits 1401 are also distributed, and the non-uniformity of the dark current due to the heat generated from the digital circuits 1401 can be reduced. becomes possible. Also, when the column AD is mounted, the horizontal selection circuit 105 is not necessarily required.

FIG. 23 is an overhead view of the overall configuration of an imaging device according to the eighth embodiment of the present invention. In FIG. 23, the connection points 115 are biased vertically. In this case, the non-uniformity of dark current cannot be reduced, but it is effective for forming through vias as shown in FIGS. When the characteristics of the pixels 201 near the connection point 115 are poor due to the formation of the through via, the image can be made inconspicuous by moving the connection point 115 relatively inconspicuously vertically in the screen.

FIG. 24 is an overhead view of an outline of an imaging device according to the ninth embodiment of the present invention. 25 and 26 are diagrams respectively showing the modifications thereof.

In the above configuration, the vertical selection circuit 102 is configured in region 1 and the output circuit 107 is configured in region 2, but the present invention is not limited to this. As shown in FIG. 24, output circuit 107 may be in region 1 . In this case, the output signal line 106 and the output circuit 107 are connected in the regions 1 and 2. FIG. As schematically shown in FIG. 24, the sizes of regions 1 and 2 may not be the same. Further, as shown in the modified example of FIG. 25, the vertical selection circuit 102 may be partially located in the region 1 and partially located in the region 2 . In such a configuration, it is possible to bring the driving buffer for driving the pixel 201 to the area 1 and the digital part to the area 2 in the vertical selection circuit 102 . Also, as shown in FIG. 26, it is possible to arrange the output circuit 107 not in the horizontal direction but in the vertical direction. If the column circuit is small in the vertical direction, it is possible to make the sizes of the regions 1 and 2 substantially the same by adopting such a configuration.

The configuration and operation of a digital camera, which is an image pickup apparatus using the image pickup device of the embodiment and modification described above, are the same as those described above with reference to FIG. 10, so description thereof will be omitted.

Also, the object of the present invention is achieved by executing the following processing. That is, a storage medium recording software program code for realizing the functions of the above-described embodiments is supplied to a system or device, and the computer (or CPU, MPU, etc.) of the system or device executes the program stored in the storage medium. This is the process of reading the code.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

Moreover, the following can be used as a storage medium for supplying the program code. For example, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW, magnetic tape, non-volatile memory card, ROM or the like. Alternatively, program code may be downloaded over a network.

The present invention also includes the case where the functions of the above embodiments are realized by executing the program code read by the computer. In addition, based on the instructions of the program code, the OS (operating system) running on the computer performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments. is also included.

Furthermore, the present invention also includes a case where the functions of the above-described embodiments are realized by the following processing. That is, the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Thereafter, based on the instruction of the program code, the CPU or the like provided in the function expansion board or function expansion unit may perform part or all of the actual processing.

1 region 2 region 101 pixel section 102 vertical selection circuit 103 column circuit 104 column memory 105 horizontal selection circuit 106 output signal line 107 output circuit

Claims (8)

a first semiconductor substrate and a second semiconductor substrate stacked together;
a pixel portion in which a plurality of pixels are arranged in a matrix;
a driving circuit that drives the pixel unit;
a plurality of signal processing circuits provided for each of a plurality of pixels of a predetermined unit in the pixel portion and performing predetermined signal processing on signals output from the plurality of pixels of the predetermined unit;
and a plurality of output circuits for outputting to the outside signals subjected to predetermined signal processing by the plurality of signal processing circuits, wherein
The pixel portion and at least part of the driving circuit are formed in the region of the first semiconductor substrate, and the plurality of signal processing circuits and the plurality of output circuits are formed in the region of the second semiconductor substrate. ,
When the imaging device is viewed from the light incident surface side, the plurality of signal processing circuits are arranged at positions overlapping with the pixel section, and the plurality of output circuits are arranged at positions not overlapping with the pixel section. An imaging device characterized by: 2. The imaging device according to claim 1, wherein a digital circuit for performing predetermined image processing on the output signals of said plurality of signal processing circuits is arranged in a region of said second semiconductor substrate. Each of the plurality of pixels in the pixel section includes a photoelectric conversion element that generates electric charge by photoelectric conversion, a floating diffusion section that temporarily stores the electric charge generated by the photoelectric conversion element, and a potential corresponding to the potential of the floating diffusion section. 2. The imaging device according to claim 1, further comprising an amplifying section for outputting the signal. Each of the pixel units further includes a transfer unit that transfers charges from the photoelectric conversion element to the floating diffusion unit, and a reset unit that is connected to the floating diffusion unit and resets the floating diffusion unit. The imaging device according to claim 3. a first semiconductor substrate and a second semiconductor substrate stacked together;
a pixel portion in which a plurality of pixels are arranged in a matrix;
a driving circuit that drives the pixel unit;
a plurality of signal processing circuits provided for each of a plurality of pixels of a predetermined unit in the pixel portion and performing predetermined signal processing on signals output from the plurality of pixels of the predetermined unit;
and a plurality of output circuits for outputting to the outside signals subjected to predetermined signal processing by the plurality of signal processing circuits, wherein
The pixel portion and at least part of the driving circuit are formed in the region of the first semiconductor substrate, and the plurality of signal processing circuits and the plurality of output circuits are formed in the region of the second semiconductor substrate. ,
When the imaging element is viewed from the light incident surface side, the plurality of signal processing circuits are arranged at positions overlapping with the pixel section, and the plurality of output circuits are arranged at positions not overlapping with the pixel section. an element;
a recording unit that records a signal output from the imaging device on a recording medium;
a display unit that displays an image based on the signal output from the imaging element;
An image pickup apparatus comprising: a controller for controlling the entire apparatus including the image pickup device, the recording section, and the display section. 6. The image pickup apparatus according to claim 5, wherein in said image pickup device, a digital circuit for performing predetermined image processing on the output signals of said plurality of signal processing circuits is arranged in a region of said second semiconductor substrate. . Each of the plurality of pixels of the pixel section in the imaging element includes a photoelectric conversion element that generates electric charge by photoelectric conversion, a floating diffusion section that temporarily stores the electric charge generated by the photoelectric conversion element, and the floating diffusion section. 6. The image pickup apparatus according to claim 5, further comprising an amplifier that outputs a signal corresponding to the potential of . Each of the pixel units in the imaging element further includes a transfer unit that transfers charges from the photoelectric conversion element to the floating diffusion unit, and a reset unit that is connected to the floating diffusion unit and resets the floating diffusion unit. 8. The imaging apparatus according to claim 7, characterized by:

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