JP6091550B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an imaging element and an imaging apparatus.

  2. Description of the Related Art Conventionally, imaging apparatuses such as a digital camera and a digital video camera that record a captured image using a CMOSAPS (Complementary Metal Oxide Semiconductor Active Pixel Sensor) as an imaging element have been developed. The image sensor has a pixel portion and a peripheral circuit portion. The peripheral circuit section reads out signals from the pixels and outputs them as image signals to the outside. The pixel portion performs photoelectric conversion with a photodiode, and a signal obtained by the photoelectric conversion is read to a peripheral circuit portion by a pixel circuit formed in the pixel portion.

  In recent years, with the miniaturization of pixels, the circuit inside the pixel is reduced as much as possible, the area of the photodiode is increased, and the performance of the image sensor is ensured. In addition, as the function is improved, the area of the peripheral circuit portion is also increasing. Therefore, development of a technique for forming the pixel portion and the peripheral circuit portion on separate chips has been performed. For example, in Patent Document 1, a method is adopted in which the pixel includes only a photodiode and some switches, and the other switches are configured in separate chips.

  FIG. 27 is a diagram for explaining a schematic configuration of a conventional image sensor.

  The image sensor includes a pixel unit 101 ′, a vertical selection circuit 102 ′ that selects a row in the pixel unit 101 ′, and a pixel signal in a row selected by the vertical selection circuit 102 ′ among the pixels in the pixel unit 101 ′. It has a column circuit 103 ′ that performs processing. Further, the image sensor includes a column memory 104 ′ that holds the signal processed by the column circuit 103 ′ for each column, a horizontal selection circuit 105 ′ that selects a column of signals held in the column memory 104 ′, and a horizontal selection circuit 105. An output signal line 106 ′ for reading out the signal of the column selected by “′” to the output circuit 107 ′. In addition to the components shown in the figure, the imaging device includes, for example, a timing generator that provides a timing signal to the vertical selection circuit 102 ′, the horizontal selection circuit 105 ′, the column circuit 103 ′, a control circuit, and the like.

  The vertical selection circuit 102 'sequentially selects a plurality of rows of the pixel portion 101' and outputs the selected signal to the column memory 104 'via the column circuit 103'. The horizontal selection circuit 105 ′ sequentially selects signals held in the column memory 104 ′ and outputs them to the output circuit 107 ′ via the output signal line 106 ′. The pixel unit 101 ′ is configured by arranging a plurality of pixels in a two-dimensional array in order to provide a two-dimensional image. These circuits are formed on a single semiconductor substrate, and along with miniaturization of semiconductor processes, reduction of pixel intervals and reduction of area of peripheral circuits are performed.

  FIG. 28 is a diagram illustrating a configuration of one pixel in a conventional image sensor and a configuration of a circuit that reads a signal from the pixel.

  As shown in FIG. 28, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201 ′ includes a photodiode (hereinafter also referred to as “PD”) 202 ′, a transfer switch 203 ′, a floating diffusion portion (hereinafter also referred to as “FD”) 204 ′, a reset switch 207 ′, an amplification MOS amplifier 205 ′, and a selection. It is configured to include a switch 206 ′.

  The PD 202 ′ functions as a photoelectric conversion element that photoelectrically converts light incident through the optical system to generate charges. The anode of the PD 202 'is connected to the ground line, and the cathode is connected to the source of the transfer switch 203'. The transfer switch 203 'is driven by a transfer pulse φTX input to its gate terminal, and transfers the charge generated in the PD 202' to the FD 204 '. The FD 204 ′ functions as a charge voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into a voltage signal.

  The amplification MOS amplifier 205 ′ functions as a source follower, and a signal that has been subjected to charge-voltage conversion by the FD 204 ′ is input to its gate. The amplification MOS amplifier 205 ′ has a drain connected to the first power supply line VDD 1 that supplies the first potential, and a source connected to the selection switch 206 ′. The selection switch 206 ′ is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205 ′, and its source is connected to a vertical signal line (column signal line) 208 ′. . When the vertical selection pulse φSEL becomes an active level (high level), the selection switch 206 ′ of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208 ′. .

  The reset switch 207 ′ has a drain connected to the second power supply line VDD 2 that supplies a second potential (reset potential), and a source connected to the FD 204 ′. Further, the reset switch 207 ′ is driven by a reset pulse φRES input to its gate, and removes charges accumulated in the FD 204 ′.

  In addition to the FD 204 ′ and the amplification MOS amplifier 205 ′, a floating diffusion amplifier is configured by a constant current source 209 ′ that supplies a constant current to the vertical signal line 208 ′. In each pixel constituting the row selected by the selection switch 206 ′, the charge transferred from the PD 202 ′ to the FD 204 ′ is converted into a voltage signal by the FD 204 ′, and a vertical signal line provided for each column through the floating diffusion amplifier. (Column signal line) 208 ′ is output.

  The column circuit 103 ′ connected to each of the vertical signal lines (column signal lines) 208 ′ includes a CDS (correlated double sampling) circuit and a gain amplifier. The column circuit 103 'is formed of a circuit having the same configuration for each column. The signals processed by the column circuit 103 'are held in the corresponding column memories 104'. The signal held in the column memory 104 'is transferred to the output circuit 107' via the output signal line 106 '. The output circuit 107 ′ performs amplification, impedance conversion, and the like on the input signal, and outputs the signal outside the image sensor.

JP 2008-211220 A

  However, in Patent Document 1, since connection between chips is performed by floating diffusion (FD) in which a signal amount is weak among pixels, variation in manufacturing of FD becomes variation in capacitance value of FD. As a result, it causes PRNU (Photo Response Non-Uniformity) and DSNU (Dark Signal Non-Uniformity). Further, although the arrangement of the readout circuit is not described in Patent Document 1, since the pixel portion and the peripheral circuit portion are provided in separate chips, it is desirable to arrange the readout circuit more efficiently than in the past. Recently, a chip area of the peripheral circuit is increased because a circuit that realizes a plurality of functions is introduced into the peripheral circuit, such as an AD converter for each column is introduced into the column circuit. As a result, not only does the heat generated in the peripheral circuit generate a dark current in the PD 202 ′ of the pixel, but also if the arrangement of the peripheral circuit is biased, the dark current becomes non-uniform in the screen corresponding area. The problem occurs.

  An object of the present invention is to provide an imaging device and an imaging apparatus that can suppress an increase in cost by suppressing an increase in chip area of a peripheral circuit without impairing the performance of a pixel portion.

  In addition, the object of the present invention is to further suppress the increase in the chip area by efficiently arranging the peripheral circuit without impairing the performance of the pixel part in the imaging device in which the pixel part and the peripheral circuit part are formed in different regions. Another object of the present invention is to provide an image pickup device and an image pickup apparatus in which non-uniformity of dark current in a screen corresponding region due to heat generation of peripheral circuits is suppressed.

In order to achieve the above object, an image pickup device according to claim 1 includes a first semiconductor substrate and a second semiconductor substrate stacked on each other, a pixel portion in which a plurality of pixels are arranged in a matrix, and the pixels A plurality of column signal lines for outputting signals from the plurality of pixels of each column for each column, and each of which includes at least an AD converter, and for each column to perform predetermined processing on the signals output to the column signal lines a plurality of column circuits provided, the imaging device having a plurality of columns memory provided for each column to hold the signal subjected to predetermined processing by the plurality of column circuits, the imaging device The pixel portion is formed in the region of the first semiconductor substrate such that the plurality of column circuits and the plurality of column memories are positioned under the pixel portion when viewed from the light incident surface side. Rutotomoni the plurality of column circuits and the plurality of rows Mori is formed in a region of the second semiconductor substrate, the second of the formed in the region of the semiconductor substrate a plurality of column circuits and said plurality of columns memory, in a direction along the direction or column along the line at least On the other hand, at least two adjacent rows are arranged at different positions.

  In order to achieve the above object, an imaging device according to an eleventh aspect includes the imaging element according to any one of the first to tenth aspects.

  According to the present invention, it is possible to obtain an effect that the increase in cost due to the increase in the chip area of the peripheral circuit can be suppressed without impairing the performance of the pixel portion.

  In addition, according to the present invention, it is possible to efficiently and efficiently arrange peripheral circuits without impairing the performance of the pixel portion, and to suppress the non-uniformity of dark current in the screen corresponding area due to the heat generated by the peripheral circuits. Is possible.

It is a block diagram for demonstrating the whole structure of the image pick-up element which concerns on the 1st Embodiment of this invention. It is a figure which shows the circuit structure which reads the signal from the pixel in the image pick-up element which concerns on 1st Embodiment, and the pixel. FIG. 3 is a diagram illustrating a modification of the circuit configuration in FIG. 2. FIG. 10 is a diagram showing another modification of the circuit configuration of FIG. 2. It is a figure showing the cross-sectional structure of the image pick-up element based on 1st Embodiment. It is a block diagram which shows the modification of the whole structure of the image pick-up element shown in FIG. It is a block diagram which shows the other modification of the whole structure of the image pick-up element shown in FIG. It is a figure showing the cross-section of the image pick-up element which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the further modification of the whole structure of the image pick-up element shown in FIG. It is a figure which shows schematic structure of the digital camera which is an example of the imaging device carrying the image pick-up element which concerns on either of 1st and 2nd embodiment and its modification. It is a figure which shows the structure of 1 pixel in the image pick-up element which concerns on the 3rd Embodiment of this invention, and the circuit structure which reads a signal from the pixel. It is a figure which shows the modification of the circuit structure of the image pick-up element of FIG. It is a figure which shows the other modification of the circuit structure of the image pick-up element of FIG. It is the figure which looked down at the whole structure of the image pick-up element of 3rd Embodiment from the top. It is sectional drawing of the image pick-up element of the modification of 3rd Embodiment. It is the figure which looked down at the whole structure of the image pick-up element of the 5th Embodiment of this invention from the top. It is the figure which looked down at the whole structure modification of the image sensor of 5th Embodiment from the top. It is the figure which looked down on the whole structure other modification of the image pick-up element of 5th Embodiment from the top. It is the figure which looked down at the whole structure of the image pick-up element of the 6th Embodiment of this invention from the top. It is the figure which looked down at the modification of the whole structure of the image pick-up element of 6th Embodiment from the top. It is the figure which looked down at the other modification of the whole structure of the image pick-up element of 6th Embodiment from the top. It is the figure which looked down at the whole structure of the image pick-up element of the 7th Embodiment of this invention from the top. It is the figure which looked down at the whole structure of the image pick-up element of the 8th Embodiment of this invention from the top. It is the figure which looked down at the whole structure of the image pick-up element of the 9th Embodiment of this invention from the top. It is the figure which looked down at the modification of the whole structure of the image pick-up element of 9th Embodiment from the top. It is the figure which looked down at the other modification of the whole structure of the image pick-up element of 9th Embodiment from the top. It is a figure for demonstrating schematic structure of the conventional image pick-up element. It is a figure which shows the structure of 1 pixel in the conventional image sensor, and the structure of the circuit which reads a signal from the pixel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining a schematic configuration of an image sensor according to the first embodiment of the present invention. Actually, it is assumed that the illustrated region 1 and region 2 overlap in the vertical direction.

  In FIG. 1, the imaging device reads out a pixel signal from a pixel portion 101, a vertical selection circuit 102 that selects a row in the pixel portion 101, and a pixel signal in a row selected by the vertical selection circuit 102 among the pixels in the pixel portion 101. The column circuit 103 that performs the process is provided. Further, the image sensor includes a column memory 104 that holds the signal processed by the column circuit 103 for each column, a horizontal selection circuit 105 that selects a signal held in the column memory 104, and a column selected by the horizontal selection circuit 105. An output signal line 106 to be read out to the output circuit 107 is provided. In addition to the components shown in the figure, the image sensor includes, for example, a timing generator 1007 described later that provides timing to the vertical selection circuit 102, horizontal selection circuit 105, column circuit 103, and the like, a control circuit 1009 described later, and DA conversion. However, the timing generator 1007 and the control circuit 1009 may be provided separately from the image sensor as shown in FIG. 10. Also good.

  The vertical selection circuit 102 sequentially selects a plurality of rows in the pixel portion 101, and outputs a signal of the selected row to the column memory 104 via the column circuit 103. The horizontal selection circuit 105 sequentially selects the signals held in the column memory 104 and outputs them to the output circuit 107 via the output signal line 106. The pixel unit 101 is configured by arranging a plurality of pixels in a two-dimensional array in order to provide a two-dimensional image.

  The pixel portion 101, the vertical selection circuit 102, and the output circuit 107 included in the region 1 are formed on the first semiconductor substrate. On the other hand, the column circuit 103, the column memory 104, the horizontal selection circuit 105, and the output signal line 106 included in the region 2 are formed on the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are formed separately, and are mounted on the same package by connecting and stacking wirings that need to be electrically connected. That is, when viewed from the upper surface of the image pickup device package (on the light incident surface side of the pixel portion 101), the pixel portion 101 is formed in the region 2 of the first semiconductor substrate and the region 2 of the second semiconductor substrate. The column circuit 103, the column memory 104, the horizontal selection circuit 105, and the output signal line 106 thus formed are present at positions where they overlap. If the timing generator 1007, the control circuit 1009, the DA converter, and the like are arranged in the area 2 under the vertical selection circuit 102 and the output circuit 107 in the area 1, the area efficiency is good. In the embodiments described below, a configuration including the first semiconductor substrate and the second semiconductor substrate will be described as an example. However, the configuration is not limited thereto, and a configuration including another semiconductor substrate may be used. .

  FIG. 2 is a diagram illustrating a configuration of one pixel and a configuration of a circuit that reads a signal from the pixel in the image sensor according to the first embodiment.

  As shown in FIG. 2, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201 includes a photodiode (hereinafter also referred to as “PD”) 202, a transfer switch 203, a floating diffusion portion (hereinafter also referred to as “FD”) 204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206. Composed. The reset switch 207 functions as a reset unit.

  The PD 202 functions as a photoelectric conversion element that generates charges by photoelectrically converting light incident through the optical system. The anode of the PD 202 is connected to the ground line, and the cathode is connected to the source of the transfer switch 203. The transfer switch (transfer unit) 203 is driven by a transfer pulse φTX input to its gate terminal, and transfers the charge generated in the PD 202 to the FD 204. The FD 204 functions as a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into a voltage signal.

  The amplification MOS amplifier (amplification unit) 205 is configured by an amplification circuit such as a MOSFET and functions as a source follower, and a signal that has been subjected to charge-voltage conversion by the FD 204 is input to its gate. The amplification MOS amplifier 205 has its drain connected to the first power supply line VDD1 that supplies the first potential, and its source connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205, and its source is connected to the vertical signal line 208. When the vertical selection pulse φSEL becomes an active level (high level), the selection switches 206 of the pixels belonging to the corresponding row of the pixel array are turned on, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208.

  The reset switch (reset unit) 207 has a drain connected to a second power supply line VDD2 that supplies a second potential (reset potential) that is a constant potential, and a source connected to the FD 204. The reset switch 207 is driven by a reset pulse φRES input to its gate, and removes charges accumulated in the FD 204. φTX, φSEL, and φRES are supplied from the vertical selection circuit 102.

  In addition to the FD 204 and the amplification MOS amplifier 205, the constant current source 209 that supplies a constant current to the vertical signal line 208 forms a floating diffusion amplifier. In each pixel constituting the row selected by the selection switch 206, the charge transferred from the PD 202 to the FD 204 is converted into a voltage signal by the FD 204, and a vertical signal line (column signal line) provided for each column through the floating diffusion amplifier. ) 208 is output.

  The column circuit 103 connected to each of the vertical signal lines (column signal lines) 208 includes a CDS (correlated double sampling) circuit, a gain amplifier, and the like. The CDS circuit performs correlated double sampling processing on the signal output to the vertical signal line 208. The gain amplifier amplifies the signal output to the vertical signal line 208 with a predetermined amplification factor. The column circuit 103 is formed of a circuit having the same configuration for each column. The signals subjected to the above processing in the column circuit 103 are held in the corresponding column memories 104, respectively. The signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106. The output circuit 107 performs amplification and impedance conversion on the input signal and outputs the signal to the outside of the image sensor.

  The column circuit 103, the column memory 104, and the output circuit 107 can have the above-described circuit configuration, but may be a type in which the column circuit 103 includes an AD converter for each column. In that case, the column circuit 103 includes an AD converter in addition to the CDS circuit and the gain amplifier. In this case, the column memory 104 is a digital memory, and the output circuit 107 includes components such as an LVDS (Low Voltage Differential Signaling) driver.

  The illustrated region 1, that is, the first semiconductor substrate includes a PD 202, a transfer switch 203, an FD 204, a reset switch 207, an amplification MOS amplifier 205, a selection switch 206, and an output circuit 107 provided for each pixel. Has been.

  The illustrated region 2, that is, the second semiconductor substrate is configured to include a vertical signal line 208, a constant current source 209, a column circuit 103, a column memory 104, and an output signal line 106 provided for each column. . Note that the vertical signal line (column signal line) 208 is a wiring for connecting the pixel portion 101 and the column circuit 103 and may be included in either the region 1 or the region 2. The selection switch 206 may be included in the region 2.

  Further, the constant current source 209 may be in the region 1 as in a modification of the circuit configuration shown in FIG. However, in this case, since the constant current source 209 is arranged on the same substrate as the pixel, the area efficiency is not so good. This is effective only when the configuration area of the column circuit 103, the column memory 104, the output signal line 106, and the like is larger than the area of the pixel portion.

  Further, a configuration without the selection switch 206 may be used as in another modification of the circuit configuration shown in FIG. In the configuration without the selection switch 206, the selected row and the non-selected row are set by controlling the potential of ΦRES and the second power supply line VDD2.

  FIG. 5 is a diagram illustrating a cross-sectional structure of the image sensor according to the first embodiment of the present invention. A structure in which a region 1 representing a first semiconductor substrate is stacked on a region 2 representing a second semiconductor substrate is shown. The same components as those shown in FIG.

  Region 1 representing the first semiconductor substrate is formed on semiconductor substrate 501. The region 1 includes a first conductivity type region 502, a PD region 202, and a first conductivity type region 503 for suppressing dark current in the PD 202. In addition, a transfer switch 203, an FD 204, and an amplification MOS amplifier 205 are provided. In addition, a reset switch 207 is also included.

  Further, an element isolation region 504, a multilayer wiring layer 505, and an interlayer film 506 between the multilayer wiring layers 505 are provided. The through hole 507 electrically connects the wirings. Since the region 1 includes a pixel portion, the region 1 also includes a color filter 508 that performs color separation and a microlens 509 that collects light.

  Region 2 representing the second semiconductor substrate as a semiconductor substrate other than the first semiconductor substrate is formed on semiconductor substrate 510. Each circuit of the column circuit 103 is formed by a plurality of types of switches in each switch group 511. The region 2 also includes a column memory 104, an output signal line 106, and the like. The connection point 115 of the vertical signal line 208 electrically connects the region 1 and the region 2 with a micro bump or the like. In addition to the connection point 115 of the vertical signal line 208, wirings for supplying power, various drive pulses, and the like are connected by connection points 512 such as micro bumps. In the present embodiment, the first semiconductor substrate in which the light receiving portion is formed by the backside illumination type is illustrated, but the backside illumination type may be used instead of the backside illumination type.

  In this embodiment mode, as shown in FIG. 1, the pixel portion 101, the vertical selection circuit 102, and the output circuit 107 are formed in the region 1, and the other driving circuits are arranged in the region 2. However, the present invention is not limited to this. Absent. For example, the output circuit 107 may be arranged in the region 2 as in a modification of the overall configuration of the image sensor in FIG.

  Further, as shown in another modification of the overall configuration of the imaging device in FIG. 7, a part of the vertical selection circuit 102 may be arranged in the region 1 and the rest of the vertical selection circuit 102 may be arranged in the region 2. Moreover, in that case, area efficiency can also be improved by arrange | positioning in the substantially same location when it overlooks from the top. In other words, in the present invention, if at least the transfer switch 203, the FD 204, the reset switch 207, and the amplification MOS amplifier 205 are in the region 1 so that the FD 204 is not divided into the region 1 and the region 2 in the pixel portion 101. Good. Other driving circuits may be arranged in the region 1 or in the region 2 depending on the area efficiency of the semiconductor substrate.

  In the above embodiment, as shown in FIG. 5, the region 1 is the first semiconductor substrate and the region 2 is the second semiconductor substrate. However, the present invention is not limited to this, and as shown in FIG. It may be formed on the semiconductor substrate.

  FIG. 8 is a diagram illustrating a cross-sectional structure of an image sensor according to the second embodiment of the present invention. The same components as those shown in FIG. 2 and the components shown in FIG. 5 are given the same reference numerals, and descriptions thereof are omitted.

  In the second embodiment shown in FIG. 8, a region 1 and a region 2 are formed on the front surface (first surface or second surface) and back surface (first surface or second surface) of the semiconductor substrate 501, respectively. . In the present embodiment, the side on which the region 1 is formed is described as the front surface, and the side on which the region 2 is formed is described as the back surface. The protective layer 801 protects the wiring layer 505 on the back surface. The plug 802 electrically connects the front surface and the back surface.

  In the embodiment described above, the regions 1 and 2 have been described. However, the present invention is not limited to two regions, and each component may be arranged by being divided into a plurality of regions. For example, as in the modification shown in FIG. 9, the pixel unit 101 and the vertical selection circuit 102 may be formed in the region 1 and the remaining driving circuits may be divided into the region 2 and the region 3. . In the illustrated example, the remainder of the vertical selection circuit 102 and the column circuit 103 are formed in the area 2, and the remainder of the column circuit 103 and other drive circuits are separately formed in the area 3. In this way, by disposing each component separately over a plurality of regions, it is possible to mount an AD converter or the like for each column and effectively arrange the increasing column circuit 103. Note that the region 1, the region 2, and the region 3 may be formed on separate semiconductor substrates.

  FIG. 10 is a diagram illustrating a schematic configuration of a digital camera that is an example of an imaging apparatus equipped with an imaging device according to any of the above-described embodiments and modifications.

  In FIG. 10, a lens unit 1001 that forms an optical image of a subject on a solid-state imaging device (an imaging device according to any of the embodiments and modifications) 1005 is controlled by a lens driving device 1002 to perform zoom control, focus control, and aperture control. Etc. are performed. The mechanical shutter 1003 is controlled by the shutter control unit 1004. The solid-state image sensor 1005 converts the subject image formed by the lens unit 1001 into an image signal and outputs the image signal. The imaging signal processing circuit 1006 performs various corrections on the image signal output from the solid-state imaging device 1005 and compresses data.

  The timing generator 1007 is a drive unit that outputs various timing signals to the solid-state imaging device 1005 and the imaging signal processing circuit 1006. A control circuit 1009 controls various calculations and the entire imaging apparatus. The memory 1008 temporarily stores image data. The recording medium control interface 1010 performs recording or reading on a detachable recording medium 1011 such as a semiconductor memory. The display unit 1012 displays various information and captured images.

  Next, the operation at the time of shooting of the digital camera having the above-described configuration will be described.

  When a main power supply (not shown) is turned on, the power supply for the control system is turned on, and further, the power supply for the imaging system circuit such as the imaging signal processing circuit 1006 is turned on. Subsequently, when a release button (not shown) is pressed, a high-frequency component is extracted based on a signal output from the distance measuring device 1014, and the distance to the subject is calculated by the control circuit 1009. Thereafter, the lens driving device 1002 drives the lens unit 1001 to determine whether it is in focus. When it is determined that the lens unit 1001 is not in focus, the lens unit 1001 is driven again to perform distance measurement. Then, after the in-focus state is confirmed, the photographing operation starts.

  When the photographing operation is completed, the image signal output from the solid-state imaging device 1005 is subjected to image processing by the imaging signal processing circuit 1006 and written to the memory 1008 by the control circuit 1009. Data stored in the memory 1008 passes through the recording medium control I / F unit 1010 under the control of the control circuit 1009 and is recorded on a removable recording medium 1011 such as a semiconductor memory. Note that the image processing may be performed by directly entering a computer or the like through an external I / F unit (not shown).

  FIG. 11 is a diagram illustrating a configuration of one pixel and a circuit configuration for reading a signal from the pixel in the image sensor according to the third embodiment of the present invention. Region 1 is a chip having a circuit formed on a first semiconductor substrate, and region 2 is a chip having a circuit formed on a second semiconductor substrate.

  The region 1 mainly includes pixels 201, and the region 2 includes column circuits that mainly process signals from the pixels 201.

  The region 1 is configured by arranging a plurality of pixels 201 in a two-dimensional array as a pixel array that provides a two-dimensional image. Each pixel 201 includes a photodiode (hereinafter also referred to as PD) 202, a transfer switch 203, a floating diffusion portion (hereinafter also referred to as FD) 204, an amplification MOS amplifier 205, a selection switch 206, and a reset switch 207. sell.

  The PD 202 functions as a photoelectric conversion unit that generates charges by photoelectrically converting light incident through the optical system. The anode of the PD 202 is connected to the ground line, and the cathode is connected to the source of the transfer switch 203. The transfer switch 203 as a transfer unit is driven by a transfer pulse φTX input to its gate terminal, and transfers the charge generated in the PD 202 to the FD 204. The FD 204 functions as a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into a voltage signal.

  The amplification MOS amplifier 205 functions as a source follower, and a signal that has been subjected to charge-voltage conversion by the FD 204 is input to its gate. The amplification MOS amplifier 205 has its drain connected to the first power supply line VDD1 that supplies the first potential, and its source connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205, and its source is connected to the vertical signal line 208. When the vertical selection pulse φSEL becomes an active level (high level), the selection switches 206 of the pixels belonging to the corresponding row of the pixel array are turned on, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208. The vertical signal line 208 is shared by a plurality of pixels 201 sharing a column.

  The reset switch 207 has a drain connected to the second power supply line VDD2 for supplying a second potential (reset potential), a source connected to the FD 204, and is driven by a reset pulse φRES input to the gate. , The charge accumulated in the FD 204 is removed.

  In addition to the FD 204 and the amplification MOS amplifier 205, a floating diffusion amplifier is configured by a constant current source 209 that supplies a constant current to the vertical signal line 208. In each pixel constituting the row selected by the selection switch 206, the charge transferred from the PD 202 to the FD 204 is converted into a voltage signal by the FD 204, and a vertical signal line (column signal line) provided for each column through the floating diffusion amplifier. ) 208 is output. φTX, φSEL, and φRES are supplied from a vertical selection circuit described later.

  The column circuit 103 connected to each of the vertical signal lines (column signal lines) 208 includes a column amplifier 110 and the like. The column circuit 103 is formed by a circuit having the same configuration as each column. The column circuit 103 may have a configuration including only the column amplifier 110 illustrated in FIG. 11 or may include a CDS (correlated double sampling) circuit.

  Signals subjected to various processes in the column circuit 103 are held in the corresponding column memories 104, respectively. The signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106. The output circuit 107 performs amplification, impedance conversion, and the like, and outputs a signal to the outside of the image sensor.

  Region 1 and region 2 are electrically connected via a connection point 115 of a vertical signal line (column signal line) 208. As shown in FIG. 11, by connecting the connection point 115 after the amplification MOS amplifier 205, it is possible to reduce PRNU and DSNU. The constant current source 209 may be in the region 2 or the region 1.

  FIG. 12 is a diagram illustrating a modification of the image sensor circuit of FIG.

  In FIG. 12, the column AD 111 is mounted after the column amplifier 110. The column AD111 is an AD converter for each column, and performs AD conversion. In this case, the column circuit 103 includes a column amplifier 110 and a column AD111. Further, the CDS circuit described above may be included. In the case of a configuration having the column AD111, the column memory 104 is a digital memory, and the output circuit 107 includes components such as an LVDS driver.

  Further, a configuration without the selection switch 206 may be used as in another modification shown in FIG.

  FIG. 14 is an overhead view of the outline of the image sensor according to the third embodiment. Region 1 and region 2 are chips formed on different semiconductor substrates, and are mounted on the same package by connecting wirings that need to be electrically connected. That is, when viewed from the top surface of the package, the region 2 is disposed so as to overlap the region 1.

  In the region 1, the pixels 201 are formed on the array in a plurality of rows and a plurality of columns. The aforementioned φTX, φSEL, and φRES for driving the pixel 201 are supplied from the vertical selection circuit 102 for each row. A vertical signal line 208 for extracting a signal from a pixel is shared for each pixel in the same column. Here, the vertical signal lines 208 in the first to fourth columns are denoted as 208_1, 208_2, 208_3, and 208_4, respectively. Region 1 and region 2 have a connection point 115 for connecting the vertical signal line 208 to the column circuit 103. A connection point 115 included in the vertical signal line 208_1 is denoted as 115_1. Further, the column circuit 103 connected to the vertical signal line 208_1 is denoted as 103_1, and the column memory 104 connected to the column circuit 103_1 is denoted as 104_1. The area 2 has a horizontal selection circuit 105 for transferring the signal of the column memory 104 to the output circuit 107. The horizontal selection circuit 105 transfers the signal of the column memory 104 to the output circuit 107 in time series.

  In addition, although not illustrated, in any one of the region 1 and the region 2, the above-described constant current source 209 is provided in addition to the illustrated components. The constant current source 209 may be included in the column circuit 103. In addition, for example, a timing generator or control circuit that provides timing to the vertical selection circuit 102, the horizontal selection circuit 105, the column circuit 103, and the like, a serial communication interface, a DA converter, and the like are included.

  Since various pulses are supplied to the horizontal selection circuit 105 from a timing generator or the like, it is desirable that the horizontal selection circuit 105 be near the end of the chip. As shown in FIG. 14, the horizontal selection circuit 105 can be arranged in the vertical direction by bringing the connection point 115 near the center in the column direction. Note that the connection point 115 can be brought near the periphery in the column direction.

  Since the cross-sectional structure of the image sensor according to the present embodiment is substantially the same as that of the first embodiment shown in FIG. 5, illustration and description thereof are omitted.

  As shown in FIG. 14, the connection point 115 is shared by the pixels of each column on each vertical signal line (column signal line), so that the number of connection points is smaller than when there is a connection point for each pixel. Since there are few, the subject that the yield by the formation failure of a connection point reduces can also be solved. Of course, the number of connection points is not limited to one, but may be several in consideration of yield. In the present embodiment, the pixels are shared by the vertical signal lines on the region 1 side, so that it is not necessary to connect the region 1 and the region 2 for each pixel.

  In addition, although the 1st semiconductor substrate which formed the light-receiving part with the back irradiation type was shown here, the front surface irradiation type may be sufficient instead of a back surface irradiation type. FIG. 15 is a diagram showing a cross-sectional structure of a surface irradiation type according to a modification of the present embodiment. A structure in which a region 1 representing a first semiconductor substrate is stacked on a region 2 representing a second semiconductor substrate is shown. The description of the components having the same reference numerals as those in FIG. 5 is omitted. In the case of the surface irradiation type, the microlens 509 is installed above the wiring 505 with respect to the semiconductor substrate 501. In the case of the surface irradiation type, a through via 601 is formed in order to connect the connection point 115 and the components of the region 1.

  The cross-sectional structure of the fourth embodiment of the present invention in which the surface irradiation type region 1 and region 2 are formed on the same substrate 501 is substantially the same as that of the second embodiment shown in FIG. Although illustration and description are omitted, as described above, in this case, the connection point 115 becomes the through via 601 in order to connect the vertical signal line 208 and the circuit on the back surface side.

  FIG. 16 is an overhead view of the entire configuration of the image sensor according to the fifth embodiment of the present invention. FIG. 17 and FIG. 18 are diagrams showing modifications thereof, respectively.

  Unlike the diagram shown in FIG. 14, in the overall configuration of the image sensor of the fifth embodiment shown in FIG. It is possible to place the connection point 115 in the immediate vicinity. Accordingly, the wiring length in the region 2 is shortened, and the column circuit 103 and the like can be arranged more efficiently.

  In the modified example of FIG. 17, it is possible to sparsely arrange the column circuits 103_1 to 110_4 by shifting the connection points 115_1, 115_2, 115_3, and 115_4. As shown in FIG. 14, when the column circuit 103 is biased in the screen corresponding area, the heat generated in the column circuit 103 is concentrated, and the PD 202 that has received heat from the column circuit 103 is within the screen corresponding area of the photographed image. Dark current non-uniformity occurs. However, by adopting the configuration as shown in FIG. 17, for example, an equal arrangement, it is possible to reduce dark current non-uniformity due to heat generated by the column circuit 103 in the screen corresponding region. In FIG. 17, the column circuit 103 is distributed by reversing the arrangement of the column circuit 103_1, the column memory 104_1, the column circuit 103_3, and the column memory 104_3. Therefore, the output signal line 106 is arranged at the center in the direction along the column. However, in the case shown in FIG. 18 in which the column circuit 103 and the column memory 104 can have a sufficiently small configuration, this is not necessary, and the column circuits 103_1 and 103_3 may be arranged in the same direction.

  As described above, by shifting the connection point 115 for each column, an efficient arrangement and an arrangement for reducing the influence of heat generated in the column circuit 103 are possible.

  FIG. 19 is an overhead view of the entire configuration of the image sensor according to the sixth embodiment of the present invention. 20 and 21 are diagrams showing modifications thereof, respectively.

  14, 16, 17, and 18, the column circuit 103 and the column memory 104 are described as circuits having a width corresponding to two columns in the direction along the row. However, the present invention can have other configurations. The configuration is not limited to this. For example, as shown in FIG. 19, a circuit having a width of one column in the direction along the row may be used. However, the column circuit 103 or the column memory 104 becomes a circuit whose length increases in the direction along the column, and becomes further vertically long. Since the column circuit 103 and the column memory 104 are separated from each other by the element isolation region with respect to the adjacent column circuit 103 and the column memory 104, the area efficiency is better when formed in a region closer to a square. In the modification of FIG. 20, the width is 4 columns in the direction along the row. Although it looks horizontally long on the schematic diagram, such a layout is also possible by actually shifting the connection points 115 for each column in order to approach a square. As shown in the modification of FIG. 21, a plurality of output signal lines 106 can be arranged by increasing the width of the column circuit 103 and the column memory 104 in the direction along the row. Since the output signal line 106 does not consume power, the number of the output signal lines 106 is increased and arranged between the column circuit 103 and the column memory 104, so that heat generation can be dispersed.

  FIG. 22 is an overhead view of the entire configuration of the image sensor according to the seventh embodiment of the present invention. The arrangement in FIG. 22 has the same concept as that in FIG. 17, but when the column circuit 103 and the column memory 114 are small, there is a gap between the circuits. When the column AD as shown in FIG. 12 is mounted, a digital circuit 1401 can be placed. The digital circuit 1401 can also perform various correction processes such as a gamma correction process and image processes such as white balance adjustment on the signal from the column memory 104. In addition to the arrangement of FIG. 17 and FIG. 21, by arranging the column circuits 103 in a distributed manner, the digital circuits 1401 are also distributed and the dark current non-uniformity due to heat generated from the digital circuits 1401 can be reduced. Is possible. Further, when the column AD is mounted, the horizontal selection circuit 105 is not always necessary.

  FIG. 23 is an overhead view of the overall configuration of the image sensor according to the eighth embodiment of the present invention. In FIG. 23, the connection points 115 are biased up and down. In this case, dark current non-uniformity cannot be reduced, but it is effective for forming a through via as shown in FIGS. When the characteristics of the pixel 201 in the vicinity of the connection point 115 are poor due to the formation of the through via, it is possible to make the image less noticeable by bringing the connection point 115 up and down which is relatively inconspicuous in the screen.

  FIG. 24 is an overhead view of the outline of the image sensor according to the ninth embodiment of the present invention. FIG. 25 and FIG. 26 are diagrams showing modifications thereof, respectively.

  In the configuration described above, the vertical selection circuit 102 is configured in the region 1 and the output circuit 107 is configured in the region 2. However, the present invention is not limited to this. The output circuit 107 may be in the region 1 as shown in FIG. In this case, the output signal line 106 and the output circuit 107 are connected in the region 1 and the region 2. As schematically shown in FIG. 24, the size of the region 1 and the region 2 may not be the same. 25, a part of the vertical selection circuit 102 may be in the area 1 and a part in the area 2. In such a configuration, the driving buffer for driving the pixel 201 in the vertical selection circuit 102 can be brought into the region 1 and the digital portion can be brought into the region 2. Further, as shown in FIG. 26, it is possible to bring the output circuit 107 in the vertical direction instead of the horizontal direction. When the column circuit is small in the vertical direction, the size of the region 1 and the region 2 can be made substantially the same by adopting such a configuration.

  The configuration and operation of the digital camera, which is an imaging apparatus using the imaging device according to the embodiment and the modification described above, are the same as those described above with reference to FIG.

  The object of the present invention is achieved by executing the following processing. That is, a storage medium that records a program code of software that realizes the functions of the above-described embodiments is supplied to a system or apparatus, and a computer (or CPU, MPU, etc.) of the system or apparatus is stored in the storage medium. This is the process of reading the code.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

  Moreover, the following can be used as a storage medium for supplying the program code. For example, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW, magnetic tape, nonvolatile memory card, ROM or the like. Alternatively, the program code may be downloaded via a network.

  Further, the present invention includes a case where the function of the above-described embodiment is realized by executing the program code read by the computer. In addition, an OS (operating system) running on the computer performs part or all of the actual processing based on an instruction of the program code, and the functions of the above-described embodiments are realized by the processing. Is also included.

  Furthermore, a case where the functions of the above-described embodiment are realized by the following processing is also included in the present invention. That is, the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Thereafter, based on the instruction of the program code, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing.

1 area 2 area 101 pixel portion 102 vertical selection circuit 103 column circuit 104 column memory 105 horizontal selection circuit 106 output signal line 107 output circuit

Claims (10)

A first semiconductor substrate and a second semiconductor substrate stacked on each other ;
A pixel portion in which a plurality of pixels are arranged in a matrix; and
A plurality of column signal lines for outputting signals for each column from a plurality of pixels of the pixel unit;
Each of which includes at least an AD converter, and a plurality of column circuits provided for each column in order to perform predetermined processing on the signal output to the column signal line;
In an image sensor having a plurality of column memories provided for each column in order to hold a signal subjected to predetermined processing in the plurality of column circuits ,
When the image pickup device is viewed from the light incident surface side, the pixel portion is formed on the first semiconductor substrate such that the plurality of column circuits and the plurality of column memories are positioned under the pixel portion. A plurality of column circuits and a plurality of column memories formed in a region of the second semiconductor substrate;
The plurality of column circuits and the plurality of column memories formed in the region of the second semiconductor substrate are arranged at different positions in at least two adjacent columns in at least one of the direction along the row or the direction along the column. An imaging device characterized by comprising: The plurality of column circuits and the plurality of column memories formed in the region of the second semiconductor substrate are arranged at different positions in at least two adjacent columns in the direction along the row and the direction along the column. The imaging device according to claim 1. A connection point for each column that electrically connects the region of the first semiconductor substrate and the region of the second semiconductor substrate is provided at a different position in at least two adjacent columns in the direction along the column. The imaging device according to claim 1 or 2 . The image pickup device according to claim 3, wherein the connection points for the respective columns are respectively present in the plurality of column signal lines. Imaging device according to any one of claims 1 to 4, characterized in that the digital circuit for performing a predetermined image processing in the region of the second semiconductor substrate is disposed. Further comprising a drive circuits for driving the pixel portion,
According to any one of claims 1 to 5, characterized in that at least part of the driving circuits are separately formed in a region and a region of said second semiconductor substrate of the first semiconductor substrate Image sensor. Imaging device according to claim 6, wherein at least a part of the drive circuits are formed in a region of said first semiconductor substrate. Each of the plurality of pixels of the pixel unit includes a photoelectric conversion element that generates charge by photoelectric conversion, a floating diffusion part that temporarily stores the charge generated by the photoelectric conversion element, and a potential of the floating diffusion part imaging device according to any one of claims 1 to 7, characterized in that it has an amplifying section for outputting a signal. Each of the pixel units further includes a transfer unit that transfers charges from the photoelectric conversion element to the floating diffusion unit, and a reset unit that is connected to the floating diffusion unit and resets the floating diffusion unit. The imaging device according to claim 8 . Imaging apparatus characterized by comprising an imaging element according to any one of claims 1 to 9.

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