JP6328190B2 - Solid-state imaging device - Google Patents

Description

  In the present invention, a first substrate on which a plurality of photoelectric conversion units are arranged and a second substrate provided with a plurality of readout circuits for processing or reading signals generated in the photoelectric conversion units are attached. The present invention relates to a solid-state imaging device configured together.

  In a solid-state imaging device, a configuration in which a photoelectric conversion unit and a peripheral circuit unit or a part of a pixel circuit are formed separately on different substrates and are electrically connected to each other is known.

  In Patent Document 1, in order to improve the sensitivity of a photoelectric conversion unit, a bonding pad in which a photoelectric conversion unit arranged on a first substrate and a peripheral circuit arranged on a second substrate are arranged on each front surface is provided. There is disclosed a back-illuminated solid-state imaging device joined via a via.

  Patent Document 2 discloses a configuration in which light receiving pixels and through wirings are arranged on a first substrate, and a readout circuit is arranged on a second substrate. The readout circuit reads out an electrical signal through the through wiring and outputs it as an image signal. This solid-state imaging device has a configuration in which the opposite surface of the first substrate and the readout circuit of the second substrate are arranged to face each other, and the terminals of the through wiring and the readout circuit are electrically joined. ing.

JP 2006-191081 A JP 2008-235478 A

  In the configuration in which the photoelectric conversion unit and part of the pixel circuit and the peripheral circuit are formed separately on different substrates and electrically connected to each other, the alignment accuracy increases as the pixels and elements constituting each circuit become finer. Need to increase. For example, it is difficult to reliably perform electrical connection at each of a large number of electrical connection nodes such as for each pixel.

  Furthermore, as described in Patent Document 2, when a microbump structure is used for the connection portion, it is difficult to reduce the size.

  In view of the above, an object of the present invention is to provide a solid-state imaging device that can perform reliable electrical connection even if the element is miniaturized.

  The solid-state imaging device according to the present invention includes a first substrate on which a plurality of photoelectric conversion units are arranged, and a second substrate on which a plurality of readout circuits for processing signals from the photoelectric conversion units or reading the signals are arranged. A plurality of first conductive patterns disposed on the first substrate and electrically separated from each other, and each disposed on the second substrate, each of which is disposed on the first substrate. A plurality of electrically conductive second conductive patterns, and each of the plurality of first conductive patterns has a first electrical connection portion in contact with the second conductive pattern. Each of the plurality of second conductive patterns includes a second electrical connection portion that contacts the first conductive pattern, and the first conductive pattern includes the first electrical connection portion. A second partial pattern including a first partial pattern including and extending in a first direction. The turn has a partial pattern including the second electrical connection portion and extending in a second direction different from the first direction, and extends in the first direction of the first partial pattern. The existing length is longer than the length in the second direction of the first partial pattern.

  According to the present invention, in a configuration in which a solid-state imaging device is divided into a plurality of substrates and electrically connected to each other, it is possible to reliably perform electrical connection between the substrates.

1 is a conceptual diagram of a cross section of a solid-state imaging device according to Embodiment 1. FIG. 1 is a conceptual top view of a solid-state imaging device according to Embodiment 1. FIG. FIG. 6 is a top conceptual diagram of a solid-state imaging device according to Embodiment 2. It is a top surface conceptual diagram of the solid-state imaging device of a modification. 6 is a top conceptual diagram of a solid-state imaging device according to Embodiment 3. FIG. It is an example of a pixel equivalent circuit applicable to the present invention. It is sectional drawing of the solid-state imaging device applicable to this invention. It is a figure which shows the relationship between the conductive pattern of the solid-state imaging device of Example 1, and a pixel pitch. It is a figure which shows the relationship between the conductive pattern of the solid-state imaging device of Example 1, and a pixel pitch.

Example 1
FIG. 1 is a conceptual diagram of a cross section of an electrical connection portion between a first substrate and a second substrate of the solid-state imaging device of this embodiment. Here, an example in which silicon is used as the main component constituting the semiconductor portion of the substrate will be described. However, for example, gallium, arsenic, or the like may be used as the main component, or an SOI substrate may be used. The substrate is configured by combining a portion made of a semiconductor material as a main component and a portion including an insulating layer, a wiring layer, and an optical member arranged in contact with the portion made of the semiconductor material. In particular, a portion made of a semiconductor material may be called a semiconductor substrate. FIG. 1 shows a cross section of one pixel. Actually, a large number of pixels are arranged, and a column amplification unit, a vertical scanning unit, a horizontal scanning unit, and the like may be provided.

  Reference numeral 101a denotes an interface between the silicon of the first substrate and an interlayer insulating film disposed on the silicon. Reference numeral 101b denotes an interface between silicon of the second substrate and an interlayer insulating film disposed on the silicon. A plurality of photoelectric conversion units are arranged on the first substrate, and a plurality of readout circuits for processing a signal generated in each photoelectric conversion unit or reading out the signals are arranged on the second substrate. The readout circuit includes a part of the pixel circuit and a peripheral circuit provided for each pixel column. The pixel circuit includes a floating diffusion (hereinafter referred to as FD), a transfer unit that transfers a signal from the photoelectric conversion unit to the FD, a pixel amplification unit in which the FD and the gate are electrically connected, and a potential at an input node of the pixel amplification unit. A pixel circuit such as a pixel reset unit may be included. The peripheral circuit may include a signal processing unit provided for each pixel column, such as a column amplification unit and a column AD conversion unit. Further, a vertical scanning circuit, a horizontal scanning circuit, and the like can be included.

  In the readout circuit, all the above-described structures may be arranged on the second substrate, or a part thereof may be arranged on the second substrate. Preferably, as shown in FIG. 1, the transfer unit and the FD are arranged on the first substrate, and the pixel amplification unit, the pixel reset unit, and the like are arranged on the second substrate.

  Reference numeral 102 denotes a photoelectric conversion unit. Reference numeral 103 denotes an FD. A contact plug 104 is electrically connected to the FD. The contact plug is formed, for example, by burying a contact hole provided in an interlayer insulating film with a conductor such as tungsten.

  Reference numeral 105 denotes a first conductive pattern disposed on the first substrate. The first conductive pattern 105 is electrically connected to the contact plug 104. A plurality of first conductive patterns are arranged on the first substrate, and each of the plurality of first conductive patterns is electrically separated.

  Reference numeral 106 denotes a second conductive pattern disposed on the second substrate. A plurality of second conductive patterns are arranged on the second substrate, and each of the plurality of second conductive patterns is electrically separated.

  The second conductive pattern 106 is electrically connected to the gate of the pixel amplification unit and the source of the pixel reset unit arranged on the second substrate via, for example, a plug and a wiring.

  Reference numeral 107 denotes a first direction axis indicating a first direction, and reference numeral 108 denotes a second direction axis indicating a second direction different from the first direction. Preferably, the first direction and the second direction are perpendicular to each other.

  The first conductive pattern 105 has a first electrical connection portion that contacts the second conductive pattern 106, and the second conductive pattern 106 is a second electrical connection that contacts the first conductive pattern 105. Part.

  In order to show the 1st and 2nd electrical connection part, the upper surface conceptual diagram of the electrical connection part of a 1st board | substrate and a 2nd board | substrate is shown in FIG. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Reference numeral 201 denotes an electrical connection portion between the first conductive pattern 105 and the second conductive pattern 106. The electrical connection portion 201 is configured by bringing a first electrical connection portion included in the first conductive pattern and a second electrical connection portion included in the second conductive pattern into contact with each other.

  Reference numeral 202 denotes an electrical connection portion between the first conductive pattern and a conductor that electrically connects the first conductive pattern and the FD. Reference numeral 203 denotes an electrical connection portion between the second conductive pattern and a conductor that electrically connects the second conductive pattern to the gate of the pixel amplification unit and the source of the pixel reset unit. Preferably, the electrical connection portions 202 and 203 are arranged at positions different from the electrical connection portion 201 in a plan view.

  The first conductive pattern 105 extends in the first direction, and the second conductive pattern 106 extends in the second direction. Then, the first electrical connection portion of the first conductive pattern 105 and the second electrical connection portion of the second conductive pattern 106 are electrically connected by contact.

  The length of the first conductive pattern 105 parallel to the first direction is b1, and the length parallel to the second direction is b2. The length of the second conductive pattern 106 parallel to the first direction is a1, and the length parallel to the first direction is a2. And b1 is longer than b2, and a2 is longer than a1. The lengths of a1 and b1, which are the lengths in the extending direction of the respective conductive patterns, are preferably shorter than the pixel pitch. Furthermore, it is preferable that the upper limit of a2 or b1 in the configuration in which a plurality of photoelectric conversion units share a pixel amplification unit is shorter than a pitch corresponding to the number of pixels to be shared. Here, the pixel pitch is a pixel pitch on the first substrate. Specifically, it can be defined by the length between the central portions of the photoelectric conversion units.

  An example of the positional relationship between the pixel pitch and the conductive pattern on the first substrate is shown in FIG. Here, an example in which a photoelectric conversion unit, an FD, and a transfer unit are arranged on the first substrate is shown.

  Reference numeral 801 denotes a photoelectric conversion unit. Reference numeral 802 denotes an FD. Reference numeral 803 denotes a transfer gate constituting a part of the transfer unit. Reference numeral 804 denotes a first conductive pattern. Reference numeral 805 denotes an element isolation region for determining the active region of the semiconductor region. The pixel pitch in the vertical direction is p1, and the pixel pitch in the horizontal direction is p2. In this example, the first conductive pattern 804 extends in the horizontal direction, and the length extending in the horizontal direction is a1. A1 is shorter than the pixel pitches p1 and p2. As in this example, when the length of the pixel pitch differs depending on the adjacent direction, it may be shorter than at least the longer pixel pitch.

  Further, the first conductive pattern 804 is arranged so as to overlap with a part of the photoelectric conversion unit 801. In other words, the first conductive pattern 804 extends to a part of a region obtained by vertically projecting the photoelectric conversion unit in the direction of the second substrate. Such a configuration is preferable because the light transmitted through the photoelectric conversion unit can be reflected back to the photoelectric conversion unit again.

  FIG. 9 shows an example of a top view of the first substrate in the case where the pixel amplification unit is shared by a plurality of photoelectric conversion units. Portions similar to those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 9A shows the configuration of the first example, and FIG. 9B shows the configuration of the second example. Both examples are included in this embodiment.

  In FIG. 9A, reference numeral 901 denotes a first conductive pattern. The first conductive pattern 901 extends in the vertical direction with a length a1, and is composed of the uppermost wiring layer. The first conductive pattern 901 is in contact with the second conductive pattern of the second substrate to form an electrical connection portion. The first conductive pattern 901 is arranged across the boundary line 902 of the pixel. By arranging in this way, the length of the first conductive pattern parallel to the first direction can be increased, and the electrical connection with the second conductive pattern can be more reliably performed. . More preferably, the length a1 extending in the vertical direction of the first conductive pattern is longer than the pixel pitch p1 and shorter than twice the pixel pitch p1. Furthermore, in a configuration in which a pixel amplification unit or the like is shared by a large number of photoelectric conversion units, the pitch may be shorter than the number of the photoelectric conversion units in the arrangement direction shared. For example, when four photoelectric conversion units are shared, the pixel pitch may be longer than 3 times and shorter than 4 times. In general, it is preferable to satisfy (n−1) × p ≦ L ≦ n × P, where L is the length of the conductive pattern, n is the number of shared pixels, and p is the pixel pitch.

  In FIG. 9B, reference numeral 902 denotes a conductive pattern composed of the uppermost wiring layer. The conductive pattern 902 is in contact with the second conductive pattern to form an electrical connection portion. The conductive pattern 902 extends in the vertical direction with a length a2. The length a2 of the conductive pattern 902 is shorter than the pixel pitch p1. Reference numeral 903 denotes a conductive pattern constituted by a wiring layer below the conductive pattern 902. Conductive patterns 902 and 903 are electrically connected via a plug. In the second example of FIG. 9B, the length of the conductive pattern that actually contacts the second conductive pattern, that is, the length of the conductive pattern 902 is compared to the configuration of FIG. Become shorter. Even with such a configuration, the present invention can be realized, but in order to further improve the reliability of electrical connection, the configuration as shown in FIG. 9A is better.

  8 and 9, the first conductive pattern has been described. However, it can be similarly applied to the second conductive pattern. In this case, the relationship between the pixel pitch on the first substrate and the second conductive pattern may be defined in the same manner as the above formula. In the case of a common pixel configuration as in the case of the first conductive pattern, the second conductive pattern is preferably arranged across the pixel boundary.

  As in this example, the first conductive pattern and the second conductive pattern are brought into contact with each other and electrically connected to each other, thereby suppressing an increase in capacitance (FD capacitance) generated in the FD. It is possible to reliably perform electrical connection of the substrate.

Specifically, for example, as a comparative example, consider a case where the first and second conductive patterns have a square shape of 0.2 μm × 0.2 μm. That is, a1 = a2 = b1 = b2. In order to make the resistance within a desired range, it is assumed that a good connection is made when the area of the electrical contact portion is 0.01 μm ² or more. In this case, in the comparative example, when an alignment misalignment greater than 0.1 μm occurs, the area of the electrical connection portion becomes smaller than 0.01 μm ² , and the resistance becomes larger than a desired value. Become.

On the other hand, when the first and second conductive patterns are a1 = b1 = 0.4 μm and a2 = b2 = 0.1 μm, and the area of the contact portion is 0.01 μm ² or more, good connection is performed. It shall be. In this case, it is possible to tolerate an alignment deviation of 0.15 μm, and the allowable range of the alignment deviation is 1.5 times that of the comparative example.

  Moreover, it is advantageous also in a manufacturing process to make it a shape with a large aspect ratio like a present Example. Specifically, it has a great advantage when a conductive pattern for electrical connection using copper or the like as a wiring material is formed by a damascene manufacturing method (damascene structure). When the first conductive pattern has a square shape as in the comparative example and the area is increased for good connection, dishing or the like is likely to occur during the CMP process for forming the damascene structure. Compared to this, dishing during the CMP process can be suppressed compared to the comparative example by forming at least one of the first conductive pattern or the second conductive pattern into a shape with a large aspect ratio extending in one direction. It becomes.

(Example 2)
FIG. 3 shows a top view of the electrical connection portion of the present embodiment. The difference of the present embodiment from the first embodiment is that a plurality of electrical connection portions between one first conductive pattern and one second conductive pattern are provided.

  301a to 301e are partial patterns constituting the first conductive pattern. The first conductive pattern is composed of a plurality of partial patterns. On the other hand, it can be said that Example 1 is composed of a single partial pattern. Reference numeral 302 denotes a second conductive pattern. Reference numerals 303 a to 303 d denote electrical connection portions between the partial patterns 301 a to 301 d and the second conductive pattern 302. Reference numeral 304 denotes an electrical connection portion between a conductor that electrically connects the partial pattern 301a and the FD and the first conductive pattern 301a.

  Reference numeral 305 denotes an electrical connection portion between the second conductive pattern 302 and a conductor that electrically connects the second conductive pattern 302 to the gate of the pixel amplification unit and the source of the pixel reset unit. Reference numeral 306 denotes a direction axis indicating the first direction, and reference numeral 307 denotes a direction axis indicating the second direction.

  In the partial patterns 301a to 301d, the length in the direction parallel to the first direction is a1, and the length in the direction parallel to the second direction is a2. a1 is longer than a2. The length of the partial pattern 301e in the direction parallel to the first direction is a3, and the length in the direction parallel to the second direction is a4. The partial pattern 301e is provided to electrically connect the partial patterns 301a to 301d. The partial pattern 301e is not provided with an electrical connection portion with the second conductive pattern 302. In this embodiment, the partial patterns 301a to 301d are portions extending in the first direction. That is, one first conductive pattern has a plurality of portions extending in the first direction.

  The length of the second conductive pattern 302 in the direction parallel to the first direction is b1, and the length in the direction parallel to the second direction is b2. b2 is longer than b1.

  In this embodiment, the first conductive pattern has a plurality of partial patterns extending in the first direction, so that a plurality of electrical connection portions between the first conductive pattern and the second conductive pattern are provided. According to such a configuration, it is possible to perform better electrical connection as compared with the first embodiment. The number of electrical connections is not limited to this, and the effect of this embodiment can be obtained if a plurality of electrical connections are provided. 3 shows an example in which the partial patterns 301a to 301e are formed by the same wiring layer. For example, the partial pattern 301e is formed by a wiring layer different from 301a to 301d and is electrically connected by a via plug. It is good. In this case, the first conductive pattern is composed of a plurality of wiring layers.

(Modification of Example 2)
FIG. 4 shows a top view of an electrical connection portion of a modification of the second embodiment. The difference of the present modification from the second embodiment is that each of the first conductive pattern and the second conductive pattern has a partial pattern extending in both the first and second directions.

  401a and 401b are partial patterns included in the first conductive pattern. In the partial pattern 401a, the length in the direction parallel to the first direction is a1, the length in the direction parallel to the second direction is a2, and a1 is longer than a2. Therefore, the partial pattern 401a extends in the first direction.

  Reference numerals 402a and b denote partial patterns included in the second conductive pattern. In the partial pattern 402b, the length in the direction parallel to the first direction is b2, and the length in the direction parallel to the second direction is b1. b1 is longer than b2. Therefore, the partial pattern 402b extends in a second direction different from the first direction. The partial pattern 401b has the same shape as the partial pattern 402b, and the partial pattern 402a has the same shape as the partial pattern 401a. Therefore, the first conductive pattern has a partial pattern (conductive pattern 401a) extending in the first direction and a partial pattern (conductive pattern 401b) extending in the second direction. The second conductive pattern has a partial pattern (conductive pattern 402a) extending in the first direction and a part (conductive pattern 402b) extending in the second direction.

  Reference numerals 403a and 403b denote electrical connection portions between the first conductive pattern and the second conductive pattern. More specifically, the electrical connection portion 403a is an electrical connection portion between the partial pattern 401b extending in the second direction and the partial pattern 402a extending in the first direction. The electrical connection portion 403b is an electrical connection portion between the partial pattern 401a extending in the first direction and the partial pattern 401b extending in the second direction.

  Reference numeral 404 denotes an electrical connection portion between the partial pattern 401a and a conductor that electrically connects the partial pattern 401a and the FD. Reference numeral 405 denotes an electrical connection portion between the partial pattern 402b and a conductor that electrically connects the partial pattern 402b to the gate of the pixel amplification unit and the source of the pixel reset unit.

  Also in this embodiment, it is possible to obtain the same effect as that of the second embodiment.

(Example 3)
FIG. 5 shows a top view of the electrical connection portion of the present embodiment. The difference between the present embodiment and the first and second embodiments is the shape of the second conductive pattern. Specifically, a circular shape was used as the pattern shape of the second conductive pattern.

  Reference numeral 501 denotes a first conductive pattern, and reference numeral 502 denotes a second conductive pattern. Reference numeral 503 denotes an electrical connection portion between the first conductive pattern 501 and the second conductive pattern 502. Reference numeral 504 denotes an electrical connection portion between the first conductive pattern 501 and a conductor that electrically connects the first conductive pattern 501 and the FD. Reference numeral 505 denotes an electrical connection portion between the second conductive pattern 502 and a conductor that electrically connects the second conductive pattern 502 to the gate of the pixel amplification unit and the source of the pixel reset unit. Reference numeral 506 denotes a direction axis indicating the first direction, and reference numeral 507 denotes a direction axis indicating the second direction.

  The length of the first conductive pattern 501 in the direction parallel to the first direction is a1, and the length in the direction parallel to the second direction is a2. a1 is longer than a2. Therefore, the first conductive pattern 501 extends in the first direction.

  The second conductive pattern 502 has a circular shape with a diameter b1.

  According to the present embodiment, since the area of the second conductive pattern is increased, the FD capacity may be increased, but the electrical connection can be more reliably performed. Further, as a manufacturing process suitable for this embodiment, a case where the first conductive pattern is formed by the damascene method and the second conductive pattern is formed by patterning wiring different from that of the damascene can be considered. According to such a manufacturing process, even if the area of the second conductive pattern is increased, dishing or the like in the damascene CMP is not preferable.

  As described above, the reliability of the electrical connection between the first substrate and the second substrate can be enhanced by the configuration of the electrical connection portion of each embodiment of the present invention.

(Equivalent circuit diagram of solid-state imaging device)
The example of the equivalent circuit schematic of 1 pixel of the solid-state imaging device which can apply the structure of the electrical connection part of Examples 1-3 is shown.

  6A and 6B are equivalent circuit diagrams of the pixel of the present invention. Although only one pixel is shown here, a pixel array actually includes a plurality of pixels.

  Reference numeral 601 denotes a photoelectric conversion unit. Holes and electrons are generated by photoelectric conversion. For example, a photodiode is used.

  Reference numeral 602 denotes a transfer unit. The charge of the photoelectric conversion unit is transferred. For example, a MOS transistor (transfer MOS transistor) is used.

  Reference numeral 603 denotes an FD. The electric charge of the photoelectric conversion unit is transferred by the transfer unit while the potential is in a floating state.

  Reference numeral 604 denotes a pixel reset unit. At least the potential of FD is set to the reference potential. Alternatively, the potential of the photoelectric conversion unit is set to the reference potential by being turned on simultaneously with the transfer unit. For example, a MOS transistor (reset MOS transistor) is used as the pixel reset unit.

  Reference numeral 605 denotes a pixel amplification unit. Amplifies and outputs a signal based on one of the charge pairs generated in the photoelectric conversion unit. For example, a MOS transistor is used. In this case, the gate of the MOS transistor (amplification MOS transistor) of the pixel amplification unit and the FD are electrically connected.

  Reference numeral 606 denotes a transfer control line for controlling the operation of the transfer unit. Reference numeral 607 denotes a reset control line for controlling the operation of the pixel reset unit. In the case where the transfer unit and the reset unit are MOS transistors, they are wirings that transmit a pulse for turning the transistor on and off to the gate of the MOS transistor. These control lines are supplied with drive pulses from a vertical scanning circuit (not shown).

  Reference numeral 608 denotes a vertical output line. To the vertical output line 608, signals amplified by a plurality of pixel amplification units included in the pixel column are sequentially output.

  Reference numeral 609 denotes a current source. This is for supplying a bias current to the amplifying unit. In this circuit configuration, a bias current for operating the amplification MOS transistor as a source follower is supplied.

  V1 is a voltage supplied to the drains of the amplification MOS transistor and the reset MOS transistor in FIG. Although the common voltage is described here, a separate power source may be used. V2 is a voltage supplied to the current source 609a in FIG.

  V3 is a voltage supplied to the drain of the reset MOS transistor in FIG. V4 is a voltage supplied to the drain of the amplification MOS transistor in FIG. V5 is a voltage supplied to the current source 609b in FIG. 6B.

  Of the elements constituting the pixel, pixA indicates a portion disposed on the first semiconductor substrate, and pixB indicates a portion disposed on the second semiconductor substrate. A pixel pix is configured by pixA and pixB.

  Here, the difference between FIGS. 6A and 6B will be described. Different members are distinguished from each other by adding subscripts a and b. Specifically, the conductivity types of the amplification MOS transistor and the reset MOS transistor are different. In FIG. 6A, an NMOS transistor is used, and in FIG. 6B, a PMOS transistor is used. Correspondingly, the voltages supplied to the respective transistors and current sources are different.

  In FIG. 6A, V1 is a power supply voltage such as 5V or 3.3V. V2 is a voltage lower than V1, and is a ground potential, for example. On the other hand, V3 and V4 in FIG. 6B are relatively low potentials such as the ground potential, and V5 is a higher voltage than V3 such as 3.3V and 1.8V.

  In FIG. 6B, the amplification MOS transistor is a PMOS transistor. The photoelectric conversion unit is configured to use electrons as signal charges, and the gate potential of the PMOS transistor decreases when the amount of incident light is large. In response to this, the source potential of the PMOS transistor tends to rise as compared to when it is dark. That is, it becomes possible to drive the common output line with a high driving force when the signal amplitude is larger than that at the time of resetting. Therefore, it is advantageous in terms of reading speed as compared with the configuration of FIG. Conventionally, since such a configuration is arranged on the same semiconductor substrate, the structure is complicated, such as dividing wells in pixels. On the other hand, it is possible to suppress such an adverse effect by dividing the circuit board into separate substrates as in the present invention. Further, the operating voltage range in FIG. 1B can be narrowed, which is advantageous from the viewpoint of reducing the power supply voltage.

  The essence is not that the amplification MOS transistor is a PMOS transistor, but that a MOS transistor having a polarity opposite to that of the signal charge is used. That is, when the signal charge is an electron, a PMOS transistor is used as the amplification MOS transistor and the reset MOS transistor, and when the signal charge is a hole, an NMOS transistor is used. In terms of the conductivity type of the transfer transistor, the transfer MOS transistor is a first conductivity type MOS transistor, and the amplification MOS transistor and the reset transistor are second conductivity type transistors opposite to the first conductivity type.

  Although the pixel configurations have been described above, the present invention is not limited to these configurations. For example, a junction field effect transistor (JFET) can be used as the amplification transistor. Alternatively, a hole may be used as the signal charge as the photoelectric conversion unit. In this case, the transfer transistor is a PMOS transistor. A plurality of photoelectric conversion units may share an amplification transistor and a reset transistor. Alternatively, a selection transistor may be separately used in series with the amplification transistor. Further, an example of distributing pixel configurations to a plurality of semiconductor substrates is not limited to the above configuration. In addition to the above configuration, a reset MOS transistor and an amplification MOS transistor may be arranged on the first semiconductor substrate. Further, the pixel may not be provided with the amplification MOS transistor and the reset MOS transistor, and the charge of the photoelectric conversion unit may be directly output to the common output line by the transfer MOS transistor.

  The embodiments described in the first to third embodiments have been described with reference to an example in which the FD disposed on the first substrate is applied to a portion connecting the gate of the amplification transistor and the source of the reset transistor disposed on the second substrate. . However, the present invention is not limited to this, and the present invention is preferably applied to the case where a large number of electrical connection portions are provided between the first substrate and the second substrate such as for each pixel or each pixel column.

(Conceptual sectional view of the entire solid-state imaging device)
FIG. 7 shows a conceptual diagram of a cross section including an electrical connection portion between the first substrate and the second substrate. Here, a configuration in which a photoelectric conversion unit, an FD, and a transfer unit are arranged on the first substrate, and a pixel amplification unit and a pixel reset unit are arranged on the second substrate is shown. In the electrical connection unit, the FD is connected to the gate of the pixel amplification unit and the source of the pixel reset unit. However, the example of the electrical connection is not limited to this.

  Reference numeral 701 denotes a first substrate. Reference numeral 702 denotes a second substrate. Reference numeral 703a denotes a pixel region arranged on the first substrate. Reference numeral 703b denotes a pixel region disposed on the second substrate. Reference numeral 704a denotes a first peripheral region disposed on the first substrate. The first peripheral region 704a is a region arranged outside the pixel region 703a. Reference numeral 704b denotes a second peripheral region disposed on the second substrate. The second peripheral area 704b is an area disposed outside the pixel area 703b, and a circuit for processing a signal output from the pixel area via the common output line or a signal output from the pixel area is disposed. .

  Reference numeral 705 denotes a photoelectric conversion unit. Reference numeral 706 denotes an FD. Reference numeral 707 denotes an amplification transistor that constitutes a pixel amplification unit. The gate is electrically connected to the FD. Reference numeral 708 denotes a MOS transistor that constitutes a part of the readout circuit arranged in the second peripheral region. As an example of the readout circuit, there is a parallel processing circuit that processes in parallel the signals read out for each of the plurality of pixel columns. Examples of such parallel processing circuits include a column amplifier and a column AD. Reference numeral 709 denotes a MOS transistor constituting a circuit other than the parallel processing circuit arranged in the second peripheral circuit.

  Reference numeral 710 denotes a third conductive pattern constituting a DC voltage supply wiring for supplying a DC voltage to the MOS transistor 709 constituting the parallel processing circuit. The third conductive pattern 710 extends in the depth direction of the drawing, and supplies a DC voltage to the MOS transistors of the parallel processing circuits in common. The third conductive pattern is disposed outside the pixel region.

  Reference numeral 711 denotes a fourth conductive pattern disposed on the first substrate. The fourth conductive pattern is disposed outside the pixel region.

  Reference numeral 712 denotes an electrical connection portion that electrically connects the third conductive pattern 710 and the fourth conductive pattern 711. For example, the electrical connection portion 712 is configured by forming a conductive pattern with the uppermost wiring layer disposed on the first substrate and the uppermost wiring layer disposed on the second substrate, and electrically connecting them. Can do. The configuration described in the first to third embodiments can be applied to this electrical connection portion.

  The fourth conductive pattern 711 is disposed in the first peripheral region of the first substrate. The first peripheral region has fewer circuit elements than the second peripheral region disposed on the second substrate, or there is no circuit element itself. Accordingly, since the degree of freedom of layout is relatively high, the resistance value can be increased while maintaining the degree of freedom of the wiring layout of the second substrate by making the area of the fourth conductive pattern larger than the area of the second conductive pattern. It can be lowered, which is preferable.

  Reference numeral 713 denotes an electrical connection portion that electrically connects the FD 706 and the gate of the amplification transistor 707. The second electrical connection portion can be configured by forming a conductive pattern by the uppermost wiring layer of the first substrate and the uppermost wiring layer of the second substrate and electrically connecting them. The electrical connection part demonstrated in Examples 1-3 corresponds to this.

  Here, regarding the relationship between the area of the conductive pattern constituting the electrical connection portion 712 and the area of the conductive pattern constituting the electrical connection portion 712, it is better to reduce the area of the conductive pattern constituting the electrical connection portion 713. . This is because the electrical connection portion 713 connects the FD and the gate of the amplification transistor, and the parasitic capacitance generated in the FD increases when the area of the conductive pattern is large.

  Although not shown in the drawing, a control wiring for controlling the transfer unit is arranged on the first substrate, and vertical scanning for supplying a driving pulse for controlling the conduction of the transfer unit to the control substrate on the second substrate. Department is arranged. Therefore, the control wiring and the vertical scanning unit are also electrically connected by the same configuration as the electrical connection 713.

  Although the present invention has been described with reference to the embodiments, the embodiments can be combined or modified without departing from the gist of the invention.

  For example, in the configurations of the first and second embodiments, the shapes of the first conductive pattern and the second conductive pattern can be interchanged. Furthermore, in the first and second embodiments, at least one of the first and second conductive patterns has a partial pattern extending in a predetermined direction, and the length of the extending part parallel to the predetermined direction is: What is necessary is just to be longer than the length of the direction different from a predetermined direction. The shape of the other conductive pattern is not particularly limited. The magnitude relationship between the length in the direction in which the conductive pattern extends and the pixel pitch described in the first embodiment is applicable to other embodiments.

  Further, in the embodiment, an example is shown in which the FD is applied to an electrical connection portion between the FD, the pixel amplification unit, and the pixel reset unit. However, it may be applied only to other parts. Specifically, when the transfer unit is arranged on the first substrate and the vertical scanning unit for scanning the transfer unit is arranged on the second substrate, the electrical connection part between the vertical scanning unit and the control line of the transfer unit is used. It is also possible to apply. Furthermore, when a vertical output line is arranged on the first substrate, and a column readout circuit such as a column amplification unit or a column AD is arranged on the second substrate, the electrical connection between each vertical output line and the column readout circuit It is also possible to apply to a general connection.

  Alternatively, the first or second conductive pattern may be arranged so as to extend to a region corresponding to a part of a region where the photoelectric conversion unit is vertically projected in the direction of the second substrate. According to such a configuration, it is possible to return the light that has passed through the photoelectric conversion unit to the photoelectric conversion unit, and it is possible to improve photosensitivity.

102 photoelectric conversion unit 702 first substrate 701 second substrate 105 first conductive pattern 106 second conductive pattern 201 electrical connection unit

Claims (10)

A first substrate on which a photoelectric conversion unit and a floating diffusion are disposed;
A solid-state imaging device having a second substrate on which a pixel amplification unit in which the floating diffusion and the gate are electrically connected is disposed,
A first conductive pattern disposed on the first substrate;
A second conductive pattern disposed on the second substrate,
The first conductive pattern is disposed on an uppermost wiring layer of the first substrate, and has a first partial pattern extending in a first direction,
The second conductive pattern is disposed on an uppermost wiring layer of the second substrate, and has a second partial pattern extending in a second direction different from the first direction,
The first partial pattern and the second partial pattern have an intersection where they are in contact with each other,
A solid-state imaging device, wherein a length of the intersecting portion in the first direction is different from a length of the intersecting portion in the second direction.   The solid-state imaging device according to claim 1, wherein the first direction and the second direction are orthogonal to each other. A peripheral circuit is disposed on the second substrate,
Wherein the first conductive pattern via the second conductive pattern, the solid-state imaging device according to claim 1 or 2 signal is characterized in that it is output to the peripheral circuit. At least a part of the plurality of first conductive patterns or the plurality of second conductive patterns extends to a part of a region obtained by vertically projecting the photoelectric conversion unit in the direction of the second substrate. It is arrange | positioned, The solid-state imaging device of any one of Claims 1-3 characterized by the above-mentioned. A plurality of the floating diffusions, a plurality of transfer units for transferring the signals of the respective photoelectric conversion units to the respective floating diffusions, and a plurality of transfer control lines for controlling conduction of the transfer units are arranged on the first substrate. ,
A vertical scanning unit for supplying drive pulses to the plurality of transfer control lines is disposed on the second substrate, and each of the plurality of first conductive patterns is electrically connected to each of the plurality of transfer control lines. Has been
Wherein each of the plurality of second conductive patterns, the solid-state imaging device according to any one of claims 1 to 4, characterized in that connected the electrically vertical scanning unit. Wherein at least one of the first conductive pattern and the second conductive pattern is a solid-state imaging device according to any one of claims 1 to 5, characterized in that it is formed by a plurality of wiring layers. The first conductive pattern further includes a third partial pattern extending in the second direction,
The second conductive pattern further includes a fourth partial pattern extending in the first direction,
The third partial pattern has an electrical connection portion that contacts the fourth partial pattern,
It said fourth portion pattern, the solid-state imaging device according to any one of claims 1 to 6, characterized in that it has an electrical connection portion for connecting the third partial patterns and electrically. The solid-state imaging device according to any one of claims 1 to 7, at least one of said first conductive pattern and the second conductive pattern is characterized by a damascene structure. The photoelectric conversion unit;
The floating diffusion;
A plurality of pixels including a transfer unit that transfers a signal of the photoelectric conversion unit to the floating diffusion, and a set of the photoelectric conversion unit, the floating diffusion, and the transfer unit is provided on the first substrate with a predetermined pixel pitch; Are regularly arranged,
2. The solid-state imaging device according to claim 1, wherein a length of the first partial pattern in a direction parallel to the first direction is shorter than the pixel pitch. The photoelectric conversion unit, the floating diffusion,
A transfer unit for transferring a signal of the photoelectric conversion unit to the floating diffusion, the pixel amplification unit,
A pixel reset unit that resets a potential of an input node of the pixel amplification unit;
A plurality of pixels including
The plurality of photoelectric conversion units, the plurality of floating diffusions and the plurality of transfer units are arranged on the first substrate,
The plurality of pixel amplification units and the plurality of pixel reset units are disposed on the second substrate,
The pixel amplification unit and the pixel reset unit are shared by the plurality of photoelectric conversion units by electrically connecting the first conductive pattern to the plurality of floating diffusions,
The plurality of photoelectric conversion units are regularly arranged at a predetermined pixel pitch,
When the length in the first direction of the first partial pattern is L, the number of the shared photoelectric conversion units is n, and the pixel pitch is p,
(N-1) × p ≦ L ≦ n × p
The solid-state imaging device according to claim 1, wherein:

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