JP2004186407A - Photoelectric converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric converter the height of which is lowered from a photoelectric conversion region. <P>SOLUTION: The photoelectric converter includes a photoelectric conversion region 1, a plurality of unit pixels having a plurality of MOS transistors two-dimensionally arranged to read a signal from the photoelectric conversion region 1, control lines TX, RES, SEL providing potential to gates 2, 3, 6 of a plurality of the MOS transistors, an output line 5 for outputting the signal from the unit pixels, and a power supply line VDD connected to at least one of a plurality of the MOS transistors. The gates 2, 3, 6 of a plurality of the transistors and the control lines TX, RES, SEL are configured with a first wiring layer (polysilicon layer), and the output line 5 and the power supply line VDD are configured with a second wiring layer (metal layer). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device in which a plurality of unit pixels each having a photoelectric conversion region and a plurality of transistors for reading signals from the photoelectric conversion region are two-dimensionally arranged.
[0002]
[Prior art]
In recent years, CMOS-type photoelectric conversion elements have been reviewed due to the merit that they can be operated with a single power supply with lower power consumption than the CCD type, and the light receiving section and peripheral circuits can be manufactured in the same CMOS process and can be easily integrated. There is a move towards commercialization. Since the CMOS type photoelectric conversion device has a large number of elements per pixel, it is required to increase the aperture ratio by wiring metal layers in multiple layers.
[0003]
FIG. 14 is an equivalent circuit diagram of a CMOS photoelectric conversion device described in Patent Document 1, and FIG. 15 is a layout diagram of the CMOS photoelectric conversion device. FIG. 16 is a sectional view taken along line XX of FIG. 15 (adjacent pixels are not shown). FIG. 15 shows only four pixels. In the following description, only the pixel related to the photodiode unit PD2 will be described.
[0004]
Around the photodiode section PD2, the gate 2 of the transfer transistor M2, the floating diffusion (FD) 7, the gate 3 of the reset transistor M3, the gate 6 of the selection transistor M5, the gate 4 of the amplification transistor M4, the output Line 5 is provided. Further, TX is a control line for giving the gate potential of the transfer transistor M2, RES is a control line for giving the gate potential of the reset transistor M3, and SEL is a control line for giving the gate potential of the selection transistor M5. φTX is a control signal for giving the gate potential of the transfer transistor M2, φRES is a control line signal for giving the gate potential of the reset transistor M3, and φSEL is a control signal for giving the gate potential of the selection transistor M5.
[0005]
[Patent Document 1]
JP-A-11-195776
[Problems to be solved by the invention]
As shown in FIGS. 15 and 16, the drive line of the CMOS photoelectric conversion device had a three-layer structure of a polysilicon layer, an aluminum first layer, and an aluminum second layer.
[0007]
When shrinking the chip size, the simplest method is to simply reduce the layout of the conventional example to a desired size. However, when the chip size is shrunk by this method, it is difficult to reduce the size in the height direction even if the size can be reduced in the vertical and horizontal directions.
[0008]
According to the conventional example described with reference to FIGS. 14 to 16, since wiring is performed using two metal (aluminum) layers, even if the distance h (described in FIG. 16) from the light receiving surface is reduced, there is no limitation. is there. In other amplifying CMOS photoelectric conversion devices, there are cases where three metal layers are used to increase the area of the light receiving portion. In this case, the distance from the light receiving surface is higher than h in FIG. turn into. In a sensor whose height from the light receiving surface of the chip is high, the sensitivity decreases with an optical system having a small F-number. In particular, in a sensor such as a digital camera that requires high image quality, the problem is that the sensitivity is reduced by an optical system having a small F number.
[0009]
Therefore, an object of the present invention is to provide a configuration in which a height from a light receiving surface is reduced when a pixel size is shrunk in a photoelectric conversion device such as a CMOS photoelectric conversion device as described above.
[0010]
[Means for Solving the Problems]
In the photoelectric conversion device of the present invention, a plurality of unit pixels each including a plurality of transistors for reading signals from the photoelectric conversion region and the photoelectric conversion region are arranged in a two-dimensional manner,
A photoelectric conversion device, comprising: a control line that applies a potential to control electrodes of the plurality of transistors; an output line that outputs a signal from the unit pixel; and a power supply line connected to at least one of the plurality of transistors. ,
The photoelectric conversion device, wherein each control electrode of the plurality of transistors and the control line are configured by a first wiring layer, and the output line and the power supply line are configured by a second wiring layer. It is.
[0011]
In the embodiment described below, a photodiode is used as an element constituting the photoelectric conversion region, and a MOS transistor is used as a transistor, but another configuration may be used.
[0012]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
(Example 1)
FIG. 1 is a layout diagram showing the configuration of a first embodiment of the photoelectric conversion device of the present invention, and FIG. 2 is a cross-sectional view taken along the line aa 'of FIG. FIG. 3 is an equivalent circuit diagram of the photoelectric conversion device of FIG.
[0014]
1 to 3, reference numeral 1 denotes a photoelectric conversion region (photodiode portion); 2 denotes a gate electrode of a transfer MOS transistor M2 for transferring charges accumulated in the photoelectric conversion region 1 to a floating diffusion (FD) region 7; Reference numeral 3 denotes a gate electrode of the reset MOS transistor M3 (which serves as a control electrode). Reference numeral 4 denotes a gate electrode of the amplification MOS transistor M4. Reference numeral 5 denotes an output line. Reference numeral 6 denotes a selection MOS transistor M5. It is a gate electrode. In FIG. 2, reference numeral 8 denotes a color filter, and 9 denotes an on-chip lens for condensing light on the photoelectric conversion region 1. As an element constituting the photoelectric conversion region, for example, a bipolar transistor-structured BASIS, a static induction transistor (SIT), or the like that stores and reads out electric charges in a base can be used (the same applies to other embodiments).
[0015]
In the horizontal direction of FIG. 1, the gate control line TX of the transfer MOS transistor M2, the gate control line RES of the reset MOS transistor M3, and the gate control line SEL of the selection MOS transistor M5 are wired in a polysilicon layer. The output line 5 and the power supply line VDD are laid out in an aluminum layer or an aluminum alloy layer. In FIG. 3, φRES represents a control line signal for giving the gate potential of the resetting transistor M3, and φSEL represents a control signal for giving the gate potential of the selecting transistor M5.
[0016]
As is clear from the layout diagram of FIG. 1 and the sectional view of FIG. 2, the gate electrode 2 and the gate control line TX of the transfer MOS transistor M2, the gate electrode 3 and the gate control line RES of the reset MOS transistor M3, and the selection MOS The gate electrode 6 and the gate control line SEL of the transistor M5, and the gate electrode 4 of the amplifying MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as a gate electrode.
[0017]
When the layout is performed as in the present embodiment, only the two wiring layers of the polysilicon layer and the metal layer are used. Therefore, the distance h from the light receiving surface shown in FIG. 2 is smaller than that of the conventional example shown in FIG. It is getting smaller.
[0018]
According to the configuration of the present embodiment, it is possible to realize good image quality without lowering the sensitivity and without lowering the sensitivity even in an optical system having a small F-number.
[0019]
Note that the present invention can be suitably used for a photoelectric conversion device including a selection transistor as described in the first embodiment, but can also be applied to a configuration without a selection transistor. The following embodiment describes this configuration.
[0020]
(Example 2)
FIG. 4 is a layout diagram showing the configuration of a second embodiment of the photoelectric conversion device of the present invention, and FIG. 5 is an equivalent circuit diagram of the photoelectric conversion device of FIG. 4 and 5, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is partially omitted.
[0021]
The configuration of the light beam conversion device of the present embodiment is the same as that of the photoelectric conversion device of Embodiment 1 shown in FIGS. 1 to 3 except that there is no selection MOS transistor M5 and no gate control line SEL. The photoelectric conversion device excluding the selection MOS transistor is disclosed in, for example, Japanese Patent Application Laid-Open No. H11-112018.
[0022]
In the horizontal direction of FIG. 4, the gate control line TX of the transfer MOS transistor M2 and the gate control line RES of the reset MOS transistor M3 are wired with a polysilicon layer, and the output line 5 and the power supply line VDD are vertically wired with an aluminum layer. Alternatively, the wiring is laid out with an aluminum alloy layer.
[0023]
As is clear from the layout diagram of FIG. 4, the gate electrode 2 and the gate control line TX of the transfer MOS transistor M2, the gate electrode 3 and the gate control line RES of the reset MOS transistor M3, and the gate electrode of the amplification MOS transistor M4. 4 is formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as a gate electrode.
[0024]
In this embodiment, the same effect as in the first embodiment can be obtained. In addition, since there is no gate electrode of the selection MOS transistor M5, the gate control line SEL, and the like, the aperture ratio of the pixel is increased (the area of the photoelectric conversion region is increased). )be able to.
[0025]
(Example 3)
FIG. 6 is an equivalent circuit diagram of a third embodiment of the photoelectric conversion device of the present invention. FIG. 7 is a layout diagram showing the configuration of a third embodiment of the photoelectric conversion device of the present invention, and FIG. 8 is a cross-sectional view taken along the line bb 'of FIG. 6 to 8, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and a description thereof is partially omitted.
[0026]
This embodiment shows a two-pixel common amplification CMOS photoelectric conversion device using one reset MOS transistor and one amplification MOS transistor in common for two photoelectric conversion regions.
[0027]
1a and 1b are photoelectric conversion regions of the photodiodes PD1a and PD1b, 2a and 2b are gate electrodes of transfer MOS transistors M2a and M2b, 3 is a gate electrode of a reset MOS transistor M3, and 4 is a gate electrode of an amplification MOS transistor M4. Reference numerals 5 and 5 are output lines.
[0028]
In the horizontal direction of FIG. 7, two gate control lines TXa and TXb of the transfer MOS transistors M2a and M2b and one gate control line RES of the reset MOS transistor M3 are wired in a polysilicon layer, and are vertically aligned. The layout is such that the output line 5 and the power supply line VDD are wired in an aluminum or aluminum alloy layer.
[0029]
As is apparent from the layout diagram of FIG. 7 and the cross-sectional view of FIG. 8, the gate electrodes 2a and 2b of the transfer MOS transistors M2a and M2b, the gate control lines TXa and TXb, the gate electrode 3 and the gate control of the reset MOS transistor M3. The line RES and the gate electrode 4 of the amplification MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as a gate electrode.
[0030]
In the present embodiment, the layout is based on an equivalent circuit common to two pixels, and since only two transistors are used per pixel, the aperture ratio is further increased as compared with the second embodiment. Sensor with high performance. Further, since only two wiring layers of the polysilicon layer and the metal layer are used, the distance h from the light receiving surface (photoelectric conversion region surface) shown in FIG. 8 is smaller than that of the conventional example.
[0031]
According to the present embodiment, a sensor having higher sensitivity than the conventional example was realized, and good image quality could be realized without lowering the sensitivity even in an optical system having a small F-number.
[0032]
(Example 4)
FIG. 9 is an equivalent circuit diagram of a fourth embodiment of the photoelectric conversion device of the present invention. FIG. 10 is a layout diagram showing a configuration of a fourth embodiment of the photoelectric conversion device of the present invention, and FIG. 11 is a cross-sectional view taken along the line cc 'of FIG. 9 to 11, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and a description thereof is partially omitted.
[0033]
This embodiment shows a four-pixel common amplification CMOS type photoelectric conversion device in which one reset MOS transistor and one amplification MOS transistor are commonly used for four photoelectric conversion regions.
[0034]
1a, 1b, 1c, 1d are photoelectric conversion regions of photodiodes PD1a, PD1b, PD1c, PD1d, 2a, 2b, 2c, 2d are gate electrodes of transfer MOS transistors M2a, M2b, M2c, M2d, and 3 is a reset MOS. A gate electrode 4 of the transistor M3 is a gate electrode of the amplifying MOS transistor M4, and 5 is an output line.
[0035]
In the horizontal direction of FIG. 10, four gate control lines TXa to TXd of the transfer MOS transistors M2a to M2d and one gate control line RES of the reset MOS transistor M3 are wired in a polysilicon layer. The layout is such that the output line 5 and the power supply line VDD are wired in an aluminum or aluminum alloy layer.
[0036]
As is clear from the layout diagram of FIG. 10 and the sectional view of FIG. 11, the gate electrodes 2a to 2d of the transfer MOS transistors M2a to M2d and the gate control lines TXa to TXd, the gate electrode 3 of the reset MOS transistor M3 and the gate control The line RES and the gate electrode 4 of the amplification MOS transistor M4 are formed of a polysilicon layer. Note that since the gate electrode and the gate control line are formed of the same polysilicon layer, a part of the gate control line can be regarded as functioning as a gate electrode.
[0037]
In the present embodiment, the layout is based on the equivalent circuit common to the four pixels, so that only 1.5 transistors are used per pixel. Therefore, the aperture ratio is further increased as compared with the third embodiment. A sensor with even higher sensitivity can be made. Further, since only two wiring layers, ie, a polysilicon layer and a metal layer, are used, the distance h from the light receiving surface shown in FIG. 11 is smaller than that of the conventional example.
[0038]
According to the present embodiment, a sensor having higher sensitivity than the conventional example was realized, and good image quality could be realized without lowering the sensitivity even in an optical system having a small F-number.
[0039]
(Example 5)
FIG. 12 is a sectional view of a fifth embodiment of the photoelectric conversion device of the present invention. The same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is partially omitted.
[0040]
12, the right side A of the dashed line indicates the pixel region as shown in FIG. 2, and the left side B of the dashed line indicates the peripheral circuit region. In the peripheral circuit region B of FIG. 12, 10 is a gate electrode of a MOS transistor, 11 is a wiring, 12 and 14 are a source wiring and a drain wiring of the MOS transistor, and 13 is a wiring. The gate electrode 10 and the wiring 11 are formed of a single layer of polysilicon, the source wiring 12 and the wiring 13 are formed of a first metal layer, and the drain wiring 14 is formed of a second metal layer.
[0041]
In the present embodiment, the peripheral circuit region B is formed by a total of three layers of two metal layers as in the related art, whereas the pixel region A is formed by a total of two layers of one layer of polysilicon and one metal layer. . Therefore, the distance h from the light receiving surface (photoelectric conversion region surface) only in the pixel region can be reduced without changing the configuration of the peripheral circuit (h << h ′ in FIG. 12).
[0042]
According to the present embodiment, good image quality can be realized without deteriorating the sensitivity even in an optical system having a small F-number by simply changing the configuration of the pixel region while keeping the configuration of the peripheral circuit unchanged.
[0043]
(Example 6)
FIG. 13 is a sectional view of a sixth embodiment of the photoelectric conversion device of the present invention. The same components as those in FIGS. 1 to 3 and 12 are denoted by the same reference numerals, and the description thereof is partially omitted.
[0044]
In FIG. 13, the right side A of the dashed line indicates a pixel region as shown in FIG. 2, and the left side B of the dashed line indicates a peripheral circuit region. In the peripheral circuit region B of FIG. 13, 10 is a gate electrode of a MOS transistor, 11 is a wiring, 12 and 17 are source and drain wirings of the MOS transistor, and 13, 15, and 16 are wirings.
[0045]
The gate electrode 10 and the wiring 11 are formed of a single layer of polysilicon, the source wiring 12 and the wiring 13 are formed of a first metal layer, the wirings 15 and 16 are formed of a second metal layer, and the drain wiring 17 is formed of a third metal layer. Formed in layers.
[0046]
In the present embodiment, the peripheral circuit area B is formed by a total of four layers of one layer of polysilicon and three layers of metal as in the past, whereas the pixel area A is formed of two layers of one layer of polysilicon and one metal. It is configured. Therefore, the distance h from the light receiving surface (photoelectric conversion region surface) only in the pixel region can be reduced without changing the configuration of the peripheral circuit (h << h ′ in FIG. 13).
[0047]
According to the present embodiment, good image quality can be realized without deteriorating the sensitivity even in an optical system having a small F-number by simply changing the configuration of the pixel region while keeping the configuration of the peripheral circuit unchanged.
[0048]
Next, an imaging system using the photoelectric conversion device of each of the above embodiments will be described. An embodiment in which the photoelectric conversion device of the present invention is applied to a still camera will be described in detail with reference to FIG.
[0049]
FIG. 17 is a block diagram showing a case where the solid-state imaging device of the present invention is applied to a “still video camera”.
[0050]
In FIG. 17, reference numeral 101 denotes a barrier that serves both as protection of the lens and as a main switch; 102, a lens for forming an optical image of a subject on a solid-state imaging device (photoelectric conversion device) 104; 103, for varying the amount of light passing through the lens 102; Reference numeral 104 denotes a solid-state imaging device for capturing a subject formed by the lens 102 as an image signal; 106, an A / D converter for performing analog-digital conversion of an image signal output from the solid-state imaging device 104; Denotes a signal processing unit that performs various corrections on the image data output from the A / D converter 106 and compresses the data. 108 denotes a solid-state imaging device 104, an imaging signal processing circuit 105, an A / D converter 106, and signal processing. A timing generation unit that outputs various timing signals to a unit 107, and a control unit 109 controls various calculations and the entire still video camera. An overall control / arithmetic unit; 110, a memory unit for temporarily storing image data; 111, an interface unit for recording or reading on a recording medium; 112, a semiconductor for recording or reading image data A detachable recording medium such as a memory, and 113 is an interface unit for communicating with an external computer or the like.
[0051]
Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
[0052]
When the barrier 101 is opened, the main power is turned on, the power of the control system is turned on, and the power of the imaging system circuit such as the A / D converter 106 is turned on.
[0053]
Then, in order to control the amount of exposure, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state imaging device 104 is converted by the A / D converter 106, Is entered. Exposure calculation is performed by the overall control / calculation unit 109 based on the data.
[0054]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.
[0055]
Next, based on the signal output from the solid-state imaging device 104, a high-frequency component is extracted, and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not the lens is in focus. If it is determined that the lens is not in focus, the lens is driven again to measure the distance.
[0056]
Then, after the focus is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / operation 109. Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through a recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Further, the image may be processed by directly inputting it to a computer or the like through the external I / F unit 113.
[0057]
Although the embodiments of the present invention have been described above, the preferred embodiments of the present invention are the embodiments described below.
[0058]
(Embodiment 1) A plurality of unit pixels each having a photoelectric conversion region and a plurality of transistors for reading signals from the photoelectric conversion region are two-dimensionally arranged.
A photoelectric conversion device, comprising: a control line that applies a potential to control electrodes of the plurality of transistors; an output line that outputs a signal from the unit pixel; and a power supply line connected to at least one of the plurality of transistors. ,
The photoelectric conversion device, wherein each control electrode of the plurality of transistors and the control line are configured by a first wiring layer, and the output line and the power supply line are configured by a second wiring layer. .
[0059]
(Embodiment 2) A photoelectric conversion device, wherein at least one of the plurality of transistors is constituted by an insulated gate transistor.
[0060]
(Embodiment 3) The photoelectric conversion device according to embodiment 1 or 2, wherein the first wiring layer is a polysilicon layer.
[0061]
(Embodiment 4) The photoelectric conversion device according to embodiment 1 or 2, wherein the second wiring layer is an aluminum layer or an aluminum alloy layer.
[0062]
(Embodiment 5) The photoelectric conversion device according to embodiment 1 or 2, wherein the first wiring layer and the second wiring layer intersect at right angles.
[0063]
(Embodiment 6) The photoelectric conversion device according to Embodiment 1 or 2, wherein a color filter is provided via a flattening film.
[0064]
(Embodiment 7) The photoelectric conversion device according to embodiment 1, wherein the plurality of transistors are a transfer transistor that transfers a signal charge from the photoelectric conversion region to a storage region and a reset transistor that resets the storage region. Conversion device.
[0065]
(Eighth Embodiment) The photoelectric conversion device according to the seventh embodiment, wherein an amplification transistor for amplifying the signal charge is provided in the unit pixel.
[0066]
(Embodiment 9) The photoelectric conversion device according to embodiment 7 or 8, wherein a selection transistor for selecting a specific photoelectric conversion region is provided in the unit pixel.
[0067]
(Embodiment 10) The photoelectric conversion device according to Embodiment 7 includes an amplification transistor that amplifies the signal charge, and a plurality of the photoelectric conversion regions are connected to an input portion of the amplification transistor via the transfer transistor. A photoelectric conversion device characterized in that:
[0068]
(Embodiment 11) In a pixel region in which a plurality of unit pixels are two-dimensionally arranged, wiring is configured by the first wiring layer and the second wiring layer, and a circuit for operating the pixel region is arranged. 2. The photoelectric conversion device according to claim 1, wherein the peripheral region includes three or more wiring layers.
[0069]
(Embodiment 12) The photoelectric conversion device according to any one of Embodiments 1 to 11, an optical system that forms light on the photoelectric conversion device, and signal processing that processes an output signal from the photoelectric conversion device. An imaging system comprising a circuit.
[0070]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the height from the photoelectric conversion region surface, and it is possible to provide good image quality without lowering the sensitivity even in an optical system having a small F-number. .
[Brief description of the drawings]
FIG. 1 is a layout diagram showing a configuration of a first embodiment of a photoelectric conversion device according to the present invention.
FIG. 2 is a cross-sectional view taken along the line aa ′ of FIG.
FIG. 3 is an equivalent circuit diagram of the photoelectric conversion device of FIG.
FIG. 4 is a layout diagram showing a configuration of a second embodiment of the photoelectric conversion device of the present invention.
FIG. 5 is an equivalent circuit diagram of the photoelectric conversion device of FIG.
FIG. 6 is an equivalent circuit diagram of a third embodiment of the photoelectric conversion device of the present invention.
FIG. 7 is a layout diagram showing a configuration of a third embodiment of the photoelectric conversion device of the present invention.
FIG. 8 is a cross-sectional view taken along the line bb ′ of FIG. 7;
FIG. 9 is an equivalent circuit diagram of a fourth embodiment of the photoelectric conversion device of the present invention.
FIG. 10 is a layout diagram showing a configuration of a fourth embodiment of the photoelectric conversion device of the present invention.
FIG. 11 is a cross-sectional view taken along the line cc ′ of FIG. 10;
FIG. 12 is a sectional view of a fifth embodiment of the photoelectric conversion device of the present invention.
FIG. 13 is a sectional view of a sixth embodiment of the photoelectric conversion device of the present invention.
FIG. 14 is an equivalent circuit diagram of a conventional CMOS photoelectric conversion device.
FIG. 15 is a layout diagram of the CMOS photoelectric conversion device.
16 is a sectional view taken along line XX of FIG.
FIG. 17 is a block diagram showing a case where the photoelectric conversion device of the present invention is applied to a still video camera.
[Explanation of symbols]
1. Photoelectric conversion area (photodiode section)
2 Gate electrode of transfer MOS transistor M2 3 Gate electrode of reset MOS transistor M3 4 Gate electrode 5 of amplification MOS transistor M4 Output line 6 Gate electrode of selection MOS transistor M5 7 Floating diffusion (FD) region 8 Color filter 9 On-chip lenses TX, TXa to TXd Gate control line RES of transfer MOS transistor Gate control line SEL of reset MOS transistor Gate control line VDD of selection MOS transistor M5 Power supply line

Claims (1)

A plurality of unit pixels each including a plurality of transistors for performing signal reading from the photoelectric conversion region and the photoelectric conversion region are arranged in a two-dimensional manner,
A photoelectric conversion device, comprising: a control line that applies a potential to control electrodes of the plurality of transistors; an output line that outputs a signal from the unit pixel; and a power supply line connected to at least one of the plurality of transistors. ,
The photoelectric conversion device, wherein each control electrode of the plurality of transistors and the control line are configured by a first wiring layer, and the output line and the power supply line are configured by a second wiring layer. .

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