JP4291729B2 - 基板及び半導体装置 - Google Patents
基板及び半導体装置 Download PDFInfo
- Publication number
- JP4291729B2 JP4291729B2 JP2004128462A JP2004128462A JP4291729B2 JP 4291729 B2 JP4291729 B2 JP 4291729B2 JP 2004128462 A JP2004128462 A JP 2004128462A JP 2004128462 A JP2004128462 A JP 2004128462A JP 4291729 B2 JP4291729 B2 JP 4291729B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- thermal expansion
- expansion coefficient
- connection region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
また、第1及び第2の貫通穴に樹脂を埋め込むことで、金属基材を構成する金属と樹脂との熱膨張係数の違いにより、第1の接続領域の熱膨張係数と第2の接続領域の熱膨張係数とを異ならせることができる。
始めに、図2を参照して、本発明の実施例による半導体装置30について説明する。図2は、実装基板に実装された本発明の実施例による半導体装置の断面図である。なお、図2において、Aは半導体素子31がはんだバンプ32を介して基板35に接続される領域(以下、接続領域A)、Bは実装基板41がはんだボール39を介して基板35に接続される領域(以下、接続領域B)をそれぞれ示している。接続領域Aは、第1の接続領域であり、接続領域Bは、第2の接続領域である。
11,42 金属基材
12,13 樹脂部材
14,31 半導体素子
15,32 はんだバンプ
16,33 アンダーフィル樹脂
17,39 はんだボール
18,41 実装基板
30 半導体装置
36,37,47 貫通穴
38 樹脂
45 パネル
A,B 接続領域
E 基板形成領域
F 非形成領域
Claims (2)
- 板状の金属基材と、
半導体素子が接続される第1の接続領域と、
実装基板が接続される第2の接続領域とを備え、
前記半導体素子及び実装基板が接続される基板であって、
前記第1の接続領域に対応する前記金属基材に設けられた第1の貫通穴と、
前記第2の接続領域に対応する前記金属基材に、前記第1の貫通穴と穴径及び/又は穴の配設ピッチの異なる第2の貫通穴を設け、
前記第1及び第2の貫通穴に樹脂を埋め込むことを特徴とする基板。 - 請求項1に記載の基板と、
前記基板に接続される半導体素子とを備えたことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004128462A JP4291729B2 (ja) | 2004-04-23 | 2004-04-23 | 基板及び半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004128462A JP4291729B2 (ja) | 2004-04-23 | 2004-04-23 | 基板及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005311182A JP2005311182A (ja) | 2005-11-04 |
JP4291729B2 true JP4291729B2 (ja) | 2009-07-08 |
Family
ID=35439572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004128462A Expired - Fee Related JP4291729B2 (ja) | 2004-04-23 | 2004-04-23 | 基板及び半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4291729B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108076586A (zh) * | 2016-11-10 | 2018-05-25 | 南亚电路板股份有限公司 | 电路板及其制造方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4824397B2 (ja) * | 2005-12-27 | 2011-11-30 | イビデン株式会社 | 多層プリント配線板 |
JP5068060B2 (ja) * | 2006-10-30 | 2012-11-07 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
JP4521415B2 (ja) * | 2007-02-26 | 2010-08-11 | 株式会社東芝 | 半導体装置 |
KR101740878B1 (ko) * | 2011-03-22 | 2017-05-26 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 |
JP2015146401A (ja) * | 2014-02-04 | 2015-08-13 | 大日本印刷株式会社 | ガラスインターポーザー |
KR102411997B1 (ko) * | 2015-04-08 | 2022-06-22 | 삼성전기주식회사 | 회로기판 및 회로기판 제조방법 |
KR102411999B1 (ko) * | 2015-04-08 | 2022-06-22 | 삼성전기주식회사 | 회로기판 |
KR102472945B1 (ko) * | 2015-04-23 | 2022-12-01 | 삼성전기주식회사 | 인쇄회로기판, 반도체 패키지 및 그 제조방법 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5810374Y2 (ja) * | 1979-06-04 | 1983-02-25 | 三洋電機株式会社 | 混成集積回路基板 |
JP3635205B2 (ja) * | 1998-10-29 | 2005-04-06 | 新光電気工業株式会社 | 配線基板 |
JP2002222897A (ja) * | 2001-01-29 | 2002-08-09 | Hitachi Metals Ltd | 半導体用パッケージ |
-
2004
- 2004-04-23 JP JP2004128462A patent/JP4291729B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108076586A (zh) * | 2016-11-10 | 2018-05-25 | 南亚电路板股份有限公司 | 电路板及其制造方法 |
CN108076586B (zh) * | 2016-11-10 | 2020-06-05 | 南亚电路板股份有限公司 | 电路板及其制造方法 |
Also Published As
Publication number | Publication date |
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JP2005311182A (ja) | 2005-11-04 |
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