JP4276537B2 - 基板過渡抑制を備えた高性能集積回路調整器 - Google Patents

基板過渡抑制を備えた高性能集積回路調整器 Download PDF

Info

Publication number
JP4276537B2
JP4276537B2 JP2003525885A JP2003525885A JP4276537B2 JP 4276537 B2 JP4276537 B2 JP 4276537B2 JP 2003525885 A JP2003525885 A JP 2003525885A JP 2003525885 A JP2003525885 A JP 2003525885A JP 4276537 B2 JP4276537 B2 JP 4276537B2
Authority
JP
Japan
Prior art keywords
frequency
voltage
generating
input
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003525885A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005502249A5 (https=
JP2005502249A (ja
Inventor
イー． コネル、ローレンス
ダブリュ． ホーレンベック、ニール
リー ブッシュマン、マイケル
パトリック マッカーシー、ダニエル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25483827&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP4276537(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2005502249A publication Critical patent/JP2005502249A/ja
Publication of JP2005502249A5 publication Critical patent/JP2005502249A5/ja
Application granted granted Critical
Publication of JP4276537B2 publication Critical patent/JP4276537B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/12—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC
    • G05F1/40—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Noise Elimination (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)
  • Superheterodyne Receivers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Control Of Electrical Variables (AREA)
JP2003525885A 2001-09-04 2002-08-23 基板過渡抑制を備えた高性能集積回路調整器 Expired - Lifetime JP4276537B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/946,010 US6920316B2 (en) 2001-09-04 2001-09-04 High performance integrated circuit regulator with substrate transient suppression
PCT/US2002/027073 WO2003021637A2 (en) 2001-09-04 2002-08-23 A high performance integrated circuit regulator with substrate transient suppression

Publications (3)

Publication Number Publication Date
JP2005502249A JP2005502249A (ja) 2005-01-20
JP2005502249A5 JP2005502249A5 (https=) 2005-12-08
JP4276537B2 true JP4276537B2 (ja) 2009-06-10

Family

ID=25483827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003525885A Expired - Lifetime JP4276537B2 (ja) 2001-09-04 2002-08-23 基板過渡抑制を備えた高性能集積回路調整器

Country Status (7)

Country Link
US (1) US6920316B2 (https=)
EP (1) EP1436826A4 (https=)
JP (1) JP4276537B2 (https=)
KR (1) KR100958043B1 (https=)
CN (1) CN1559025A (https=)
AU (1) AU2002331722A1 (https=)
WO (1) WO2003021637A2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7756500B1 (en) * 2002-01-25 2010-07-13 Sige Semiconductor Inc. Active inductor circuits for filtering in a cable tuner circuit
US6984301B2 (en) 2002-07-18 2006-01-10 Micron Technology, Inc. Methods of forming capacitor constructions
US20080111646A1 (en) * 2006-10-24 2008-05-15 Rajendran Nair Regulated supply phase locked loop
JP5051112B2 (ja) * 2008-12-05 2012-10-17 富士通株式会社 電圧変動量算出方法及びシステム並びにコンデンサ実装形態決定方法及びシステム
BRPI0900948A2 (pt) * 2009-04-16 2010-12-28 Whirlpool Sa sistema de controle de chave eletrÈnica e método de acionamento de chave eletrÈnica
US20120008241A1 (en) * 2010-07-06 2012-01-12 Panasonic Semiconductor Asia Pte., Ltd. Esd protection circuit and method
US8810975B2 (en) * 2010-07-17 2014-08-19 Lsi Corporation Input capacitor protection circuit
KR101878883B1 (ko) * 2011-10-14 2018-07-17 삼성전자주식회사 무선 통신 시스템에서 송수신 동작을 제어하기 위한 장치 및 방법
US9672986B2 (en) * 2014-01-13 2017-06-06 Apple Inc. Acoustic noise cancellation in multi-layer capacitors
JP6523006B2 (ja) * 2015-03-26 2019-05-29 ラピスセミコンダクタ株式会社 半導体装置
KR20220102510A (ko) * 2021-01-13 2022-07-20 삼성전자주식회사 멀티 레벨의 전원 전압을 출력하는 전원 변조기 및 이의 동작 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4168442A (en) * 1975-07-18 1979-09-18 Tokyo Shibaura Electric Co., Ltd. CMOS FET device with abnormal current flow prevention
US4112377A (en) * 1976-01-14 1978-09-05 Tanner Electronic Systems Technology C. B. converter
JPS5780828A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device
US4477919A (en) * 1981-04-06 1984-10-16 Motorola, Inc. Range control circuit for counter to be used in a frequency synthesizer
US5266821A (en) * 1988-05-31 1993-11-30 Micron Technology, Inc. Chip decoupling capacitor
JP2869791B2 (ja) * 1988-08-31 1999-03-10 株式会社日立製作所 半導体集積回路装置およびそれを応用した電子装置
US5481178A (en) * 1993-03-23 1996-01-02 Linear Technology Corporation Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit
US5563501A (en) * 1995-01-20 1996-10-08 Linfinity Microelectronics Low voltage dropout circuit with compensating capacitance circuitry
DE19614979C2 (de) * 1995-04-20 2001-05-17 Fujitsu Ltd Hochfrequenz-Sende-Empfangs-Vorrichtung zur Datenkommunikation
US5613229A (en) * 1995-05-17 1997-03-18 Motorola, Inc. Voltage and current mode power regulator
US5712555A (en) * 1996-02-13 1998-01-27 Hughes Electronics Voltage regulation for access cards
US5822200A (en) * 1997-04-21 1998-10-13 Nt International, Inc. Low level, high efficiency DC/DC converter
KR20000008974A (ko) * 1998-07-20 2000-02-15 구자홍 모노튜너를 이용한 음성다중방송용 수신장치
US6486795B1 (en) * 1998-07-31 2002-11-26 The Chamberlain Group, Inc. Universal transmitter
US6271651B1 (en) * 2000-04-20 2001-08-07 Volterra Semiconductor Corporation Inductor shorting switch for a switching voltage regulator
US6888580B2 (en) * 2001-02-27 2005-05-03 Ati Technologies Inc. Integrated single and dual television tuner having improved fine tuning
US6583675B2 (en) * 2001-03-20 2003-06-24 Broadcom Corporation Apparatus and method for phase lock loop gain control using unit current sources

Also Published As

Publication number Publication date
EP1436826A4 (en) 2004-10-13
EP1436826A2 (en) 2004-07-14
AU2002331722A1 (en) 2003-03-18
KR100958043B1 (ko) 2010-05-17
US20030050026A1 (en) 2003-03-13
WO2003021637A3 (en) 2003-07-31
KR20040044538A (ko) 2004-05-28
JP2005502249A (ja) 2005-01-20
US6920316B2 (en) 2005-07-19
CN1559025A (zh) 2004-12-29
WO2003021637A2 (en) 2003-03-13

Similar Documents

Publication Publication Date Title
US7816990B2 (en) Variable gain amplification circuit
TWI477059B (zh) 低相雜訊電壓控制振盪器
US6906596B2 (en) Oscillation circuit and a communication semiconductor integrated circuit
US7115952B2 (en) System and method for ESD protection
US6600897B1 (en) Satellite-broadcasting receiving converter with a plurality of output terminals
JP4276537B2 (ja) 基板過渡抑制を備えた高性能集積回路調整器
US8035162B2 (en) System and method for ESD protection
US7687858B2 (en) System and method for ESD protection
US20070188203A1 (en) Semiconductor integrated circuit having built-in PLL circuit
Connell et al. A cmos broadband tuner IC
JP2011142668A (ja) ループフィルタ部品を低減するために二重経路およびデュアルバラクタを用いるタイプｉｉ位相ロックループ
US7308241B2 (en) Receiver system
CN100542009C (zh) 带有噪音减少电路的振荡电路
US20100093303A1 (en) Circuit current generation apparatus and method thereof, and signal processing apparatus
CN100379271C (zh) 高频信号接收机
JP2007536840A (ja) 干渉に堅固な水晶発振器用バッファ
US20090003496A1 (en) Reception apparatus
US20060072276A1 (en) Tunable tracking filter
US6590459B2 (en) Phase lock circuit
US20040198278A1 (en) On-chip loop filter for use in a phase locked loop and other applications
US7088962B2 (en) On-chip loop filter for a PLL
US20070075786A1 (en) Suppressing noise in a frequency synthesizer
US7119627B2 (en) Phase-locked loop circuit as well as a voltage-controlled oscillator as used in a phase-locked loop circuit
US6590431B1 (en) Maintaining substantially constant trans-conductance without substantially changing power consumption
JP3786558B2 (ja) 半導体集積回路及び無線通信機器

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20040927

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050822

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071113

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080213

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080220

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080313

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080321

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080414

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080421

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080512

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080715

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081010

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20081121

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090224

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090306

R150 Certificate of patent or registration of utility model

Ref document number: 4276537

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120313

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120313

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130313

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130313

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140313

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term