Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
  • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/12—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC
  • G05F1/40—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
  • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

• the present invention relates generally to regulation circuits. More specifically, the present invention relates to a high performance regulation circuit that is fully integrated onto a single CMOS integrated circuit with a circuit load.
• Remote regulation circuits suppress the noise caused by the switching of digital components, resulting in a cleaner and more accurate output single.
• remote regulation circuits are located on a separate substrate, more space is required.
• An example of an integrated mixed-mode circuit that requires regulation is a broadband tuner.
• Broadband tuners are integrated into a wide range of consumer electronics, ranging from familiar household standards, such as televisions and VCRs to newer more complex devices including cable settop boxes, cable modems, cable telephony systems, web TVs, PC/TV and the various implementations of digital television.
• Functioning as the RF broadband gateway the basic function of a tuner in these devices is to receive all available channels in the input bandwidth, select a desired channel and reject all others and translate the desired channel to a standard intermediate frequency (IF).
• IF intermediate frequency
• tuners operate over a frequency range of 50-860 MHz, taking into consideration those frequencies used by broadcast television and cable operators.
• Tuners that enable products to support PC, TV and internet functionality have very different performance requirements than the traditional television tuner.
• applications become more sophisticated tuners with higher performance are required.
• Tuners are increasingly being required to be fully integrated into a single integrated circuit.
• the performance of existing integrated tuners is limited by the phase noise of a fully integrated oscillator within the broadband tuner. To improve the performance of the tuner, a lower phase noise fully integrated oscillator is used.
• a low noise amplifier combined with a voltage controlled oscillator (VCO) and frequency synthesizer onto the common integrated circuit substrate.
• VCO voltage controlled oscillator
• systems have employed current streering logic for the synthesizer frequency dividers. This is done to minimize the frequency disturbance (spurs) generated by the dividers and prevent them from interfering with the low noise amplifier when the low noise amplifier, frequency dividers, and other sensitive analog circuitry are integrated onto a common substrate.
• current steering frequency dividers have high phase noise and severly limit the phase noise performance achievable for an integrated NCO.
• FIG. 1 is a circuit diagram of a regulation circuit in accordance with the preferred embodiment of the present invention
• FIG. 2 is a circuit diagram of an alternative regulation circuit of the present invention.
• FIG. 3 is a circuit diagram of a second alternative regulation circuit of the present invention.
• FIG. 4 is an example of a voltage regulator employed in the present invention
• FIG. 5 is a block diagram of a broadband tuner including a regulation circuit in accordance with the preferred embodiment of the present invention
• FIG. 6 is a circuit diagram of a digital D-Flop circuit used in a frequency divider of the present invention.
• FIG. 1 Illustrated in FIG. 1 is a circuit diagram of the regulation circuit 30 in accordance with the preferred embodiment of the present invention.
• the regulation circuit 30 is used to generate the supply voltage to a coupled load (not shown), and attenuates any substrate disturbances.
• the regulation circuit 30 comprises a regulator output capacitor 107, a regulator input capacitor 109, voltage regulator 112, an electrostatic discharge protector 123 and a power supply 310.
• a voltage regulator circuit 112 provides the necessary voltage required to power the coupled load (not shown).
• FIG.4 An example of a voltage regulator, such as a Motorola MC78000 series, in FIG.4.
• the voltage regulator 112 regulates its output to generate a predetermined output voltage which supplies any components coupled thereto . Since voltage regulators are well known in the art, a detailed discussion is not necessary and not included in this disclosure.
• the regulator output capacitor 107 is coupled to the output of the voltage regulator 112. This output capacitor 107 acts as a regulator output bypass capacitor to instantly provide the current required by the load.
• a regulator input capacitor 109 Coupled to the input of the voltage regulator 112 is a regulator input capacitor 109.
• the input capacitor 109 is placed at the input of the voltage regulator 112 input to significantly reduce the magnitude of any substrate disturbance. Without this regulator input capacitor 109, whenever a digital switching event occurs within any digital switching devices included within the coupled load (not shown), a correspondingly fast voltage change across the regulator output capacitor 107 is produced. This voltage change would be instantly transferred to the regulator input inductance 117, 118, the bond wire to the power supply 310, and through the parasitic capacitance 111 seen across a regulator pass device MP pass of the voltage regulator 112, to cause a disturbance to the integrated circuit substrate voltage level commensurate with the regulator 112 output voltage change.
• the input capacitor 109 works in conjunction with the parasitic capacitance 111 of the regulator pass device MP pass shown in FIG. 4 to capacitively divide any regulator 112 output voltage change before it is transferred to the input supply inductance 117, 118. Due to the input capacitor 109, the associated substrate disturbance is similarly attenuated.
• a voltage regulator 112 which contains a pass device MPpass that has a parasitic capacitance 111 across its input and output terminals of about 1 pf.
• the regulator 112 is used to supply power to a circuit load. If a 1000 pf capacitor 107 is placed only at the regulator's 112 output and no capacitance is placed at its input, a digital switching event occurring within the load can produce near instantaneous 40 mV drop in voltage across regulator output capacitor 107. Without a regulator input capacitor 109, this 40 mV voltage change would be instantaneously transferred to the regulator input inductance 117 and through the parasitic capacitance 111 seen across the regulator pass device MP pa ss 5 causing about a 40 mN disturbance to the integrated circuit substrate.
• the input inductance 117 has a value of 2.5nH.
• a single voltage regulator has been illustrated as serving a single coupled load, the output may be coupled to several loads.
• two separate voltage regulators as shown in Fig. 2 may be used to provide the necessary voltage to multiple component loads, as well as attenuate any substrate disturbances caused by the switching events of the components.
• the coupling of the loads to the voltage regulators maybe configured in any number of ways, and that more than two voltage regulators can be used in the regulation circuit 30, as shown in FIG. 3.
• a thin oxide transistor is used to implement input capacitor 109.
• FIG. 5 is a block diagram of a tuner system 10, made in accordance with the preferred embodiment of the present invention.
• the tuner system 10 comprises an amplifier 105, a mixer 103, a frequency synthesizer 20, and the regulation circuit 30.
• An input radio frequency (RF) signal RFj n is received by the amplifier 105.
• the amplifier 105 coupled to a mixer 103, regulates the varying signal levels across the spectrum of received channels.
• amplifier 105 is preferably a low noise amplifier which has an input frequency range of 50-860 MHz. This type of amplifier provides the least amount of noise to the tuner system 10. Although a low noise amplifier is preferable, it should be noted that other types of amplifiers may also be used (e.g. low noise amplifiers, buffers, impedance matching amplifiers, attenuators, or a mixer).
• the output of the amplifier 105 is forwarded to the mixer 103.
• Mixer 103 is coupled to the frequency synthesizer 20, the amplifier 105, and filter 12.
• the mixer 103 converts RF power at one frequency into power at another frequency to make signal processing easier and also less expensive.
• Mixer 103 receives the amplified input signal from the amplifier 105 and a local oscillator frequency signal from frequency synthesizer 20.
• An intermediate frequency IF signal is generated in mixer 103 by the multiplication of the amplified input signal and the local oscillator frequency signal and provided to a filter 12.
• the filter 12 may then select a narrow band of channels or even a single channel from the received signal RFj n in the IF signal.
• the frequency synthesizer 20 is coupled to the mixer 103 and a regulation circuit 30.
• the frequency synthesizer 20 comprises a frequency divider 115, a phase detector 120, a reference generator 100, a charge pump 121, a loop filter 102, and a voltage controlled oscillator (NCO) 101.
• NCO voltage controlled oscillator
• the frequency synthesizer 20 is implemented in a phase locked loop (PLL) arrangement.
• the NCO 101 is used to drive the mixer 103 and frequency translate the amplifier 105 input signal RFj n to the predetermined IF signal.
• the output frequency of the tuner 10 is about 1100 MHz, although another frequency may be used depending upon the requirements of the particular application.
• the NCO 101 In order for the tuner 10 to generate such an output frequency, the NCO 101 must cover a frequency range from 1150 - 1960 Hz, therefore a wideband fully integrated NCO is used.
• the NCO 101 is typically implemented as either an integrated multiple resonator based design or a single digital ring oscillator design (not shown). These two configurations though, are limited due to the limited quality factor for inductors that is achievable on-chip.
• the NCO 101 is placed in the wideband low noise frequency synthesizer 20 where the NCO 101 noise is significantly attenuated within the bandwidth of the synthesizer 20.
• the reference oscillator frequency signal of the frequency synthesizer 20 is generated by a reference generator 100.
• the frequency synthesizer 20 locks to this reference frequency as a result of the PLL arrangement.
• the reference generator 100 coupled to the phase detector 120 and the regulation circuit 30, comprises a crystal controlled oscillator 127 followed by a reference divider 122, for generating the reference frequency F ref .
• any oscillator may be used to generate the reference frequency.
• a crystal oscillator is preferably used because of its frequency accuracy and noise performance.
• the reference divider 122 may be eliminated as long as the reference oscillator 127 can produce the required reference frequency F re f.
• the reference frequency signal F ⁇ ef from the reference generator 100 is forwarded to the phase detector 120.
• the phase detector 120 coupled to the reference generator 100, the frequency divider 115, the charge pump 121, and the regulation circuit 30, generates a signal proportional to the difference in phase between a frequency division signal Fo/ ⁇ , transmitted by the frequency divider 115, and the reference frequency F ref forwarded by the reference generator 100. If the phase detector 120 detects a difference between the two frequency signals F ⁇ ef , Fo/N, a phase error signal is produced and forwarded to the charge pump 121.
• the charge pump 121 coupled to the regulation circuit 30, the loop filter 102 and the phase detector 120, outputs a current that charges and discharges the loop filter 102 to a voltage level V LPF - It is well known to those skilled in the art that the charging and discharging of the loop filter 102 creates a voltage change V LPF across the loop filter 102.
• This voltage change V LPF is a reference for the VCO 101.
• the loop filter 102 is coupled to the NCO 101, as well as the charge pump 121.
• the loop filter 102 receives the current output generated by the charge pump 121.
• the voltage V LPF is created and output to the NCO 101.
• the NCO 101 generates an output frequency which drives the mixer 103 to generate the predetermined IF frequency output from the tuner 10.
• the NCO 101 output frequency is also forwarded to the frequency divider 115.
• the frequency divider 115 coupled to the NCO 101 , the phase detector 120 and the regulation circuit 30, divides by ⁇ the frequency generated by the NCO 101 and used by the tuner 10 to allow the PLL configuration to lock to a frequency ⁇ times larger than the input frequency from the reference generator 100.
• a high performance frequency divider is used to produce a very low noise synthesizer. Referring to FIG. 6, a digital D-flop circuit configuration, used in a portion of the frequency divider 115, is shown.
• the inverter sizes of the P-channel and ⁇ -channel devices of II, 12, 15 and 16 are 40/0.35 and 20/0.35, respectively.
• the inverter sizes of the P-channel and ⁇ -channel devices of 13, 14, 17 and 18 are 20/0.35 and 10/0.35, respectively.
• the illustrated circuit is duplicated a plurality of times, in connection with one another, to make up the entire frequency divider.
• the D-flop circuit is duplicated three times to produce the frequency divider 115 in accordance with the preferred embodiment of the present invention, although more or less D-flop circuits may be used as desired.
• a digital frequency divider configuration is preferable because it provides low phase noise for detecting the phase difference between the frequencies F re f, Fo/ ⁇ , measured by the phase detector 120.
• the digital frequency divider output signal has approximately a 20 dB signal-to-noise advantage over a divider using current steering logic in an analog configuration.
• the frequency divider 115, the reference generator 100, the phase detector 120, and the charge pump 121 are coupled to the regulation circuit 30. Since each of the aforementioned components of the frequency synthesizer 115, 100, 120, 121 are digital circuits, the switching of the transistors in the circuits causes frequency disturbances on the substrate, which interfere with the amplifier 105 and other sensitive circuitry on the same substrate and adversely affects the overall performance of the tuner 10. As those skilled in the art would understand, the disturbance generated by this switching is seen on the output of the frequency synthesizer 20 and ultimately affects the output of the tuner 10. In order to prevent these frequency disturbances from interfering with the amplifier 105 located on the same integrated circuit substrate, the regulation circuit 30 is utilized. Utilizing the regulator circuit 30 illustrated in FIG.
• the frequency divider 115, the phase detector 120 and the reference generator 100 are coupled to the voltage regulator 112 as a combined "coupled load #1", whereas, the charge pump 121 is coupled to the voltage regulator 119 as “coupled load #2".
• this regulator circuit 30 having the integrated regulator input capacitor 109 is used to supply power to the high performance digital frequency divider 115, which produces 100mA switching currents at a 25 MHz rate, all switching spurs are attenuated to less than 1.0 uNrms.
• the charge pump 121 is preferably powered by the second voltage regulator 119 instead of voltage regulator 112 in order to additionally prevent the frequency divider 115 and the charge pump 121 from interfering with one another.
• the second voltage regulator 119 instead of voltage regulator 112 in order to additionally prevent the frequency divider 115 and the charge pump 121 from interfering with one another.
• only a single regulator input capacitor 109 is required. By sharing the regulator input capacitor 109 between the two voltage regulators 112, 119, the total substrate disturbance level created by both the digital frequency divider 115 and charge pump 121 is minimized for a given total amount of regulator input capacitance 109.
• Table 1 shows the frequency of the input signal RFTN and the corresponding input referred spur level for digital switching events at 12.5 MHz.
• Table 1 shows the frequency of the input signal RFTN and the corresponding input referred spur level for digital switching events at 12.5 MHz.
• —50 dbc is generally referred to as a desirable target level.
• the value of the spur products using the teachings of the present invention, are well below the desired level.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Power Engineering (AREA)
• Noise Elimination (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Logic Circuits (AREA)
• Superheterodyne Receivers (AREA)
• Semiconductor Integrated Circuits (AREA)
• Continuous-Control Power Sources That Use Transistors (AREA)
• Control Of Electrical Variables (AREA)

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Publications (2)

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• 2001
  • 2001-09-04 US US09/946,010 patent/US6920316B2/en not_active Expired - Lifetime
• 2002
  • 2002-08-23 KR KR1020047003242A patent/KR100958043B1/ko not_active Expired - Lifetime
  • 2002-08-23 CN CNA028188314A patent/CN1559025A/zh active Pending
  • 2002-08-23 AU AU2002331722A patent/AU2002331722A1/en not_active Abandoned
  • 2002-08-23 WO PCT/US2002/027073 patent/WO2003021637A2/en not_active Ceased
  • 2002-08-23 EP EP02768704A patent/EP1436826A4/en not_active Ceased
  • 2002-08-23 JP JP2003525885A patent/JP4276537B2/ja not_active Expired - Lifetime

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