JP4269855B2 - データ受信装置 - Google Patents
データ受信装置 Download PDFInfo
- Publication number
- JP4269855B2 JP4269855B2 JP2003314821A JP2003314821A JP4269855B2 JP 4269855 B2 JP4269855 B2 JP 4269855B2 JP 2003314821 A JP2003314821 A JP 2003314821A JP 2003314821 A JP2003314821 A JP 2003314821A JP 4269855 B2 JP4269855 B2 JP 4269855B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- selection
- comparison
- differential
- attenuation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
- H04B3/48—Testing attenuation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/30—Reducing interference caused by unbalance current in a normally balanced line
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
n(t)=1−Sn;nT≦t<(n+1)T・・・(2)
Rn=Sn−(1−Sn−m)=Sn+Sn−m−1・・・(4)
Rn=Sn+Sn−m−1=+1(Sn=1,Sn−m=1)
又は0(Sn=0,Sn−m=1又はSn=1,Sn−m=0)
又は−1(Sn=0,Sn−m=0)
・・・(6)
Sn−m=Sn=0・・・(8)
11 高周波減衰推定回路, 12 高周波減衰補償回路,
13 クロック再生回路, 14 DLL, 15a 閾値発生回路,
15b 閾値発生回路, 16 比較器, 17 比較器,
18 スキュー推定器, 19 選択回路,
20 サンプリング及びシフトレジスタ,
110A 差動導電体対, 110B 差動導電体対
Claims (4)
- 差動導電体対を介して伝送される基準クロック信号と、該基準クロック信号が伝送される差動導電体対と同等の差動導電体対を介して伝送されるNRZ信号とを受信するデータ受信装置において、
上記基準クロック信号の伝送路である上記差動導電体対における減衰特性を推定する推定手段と、
上記推定手段にて推定された減衰特性に応じて上記NRZ信号の伝送路減衰を補償する補償手段と、
上記補償手段によって伝送路減衰が補償された差動電圧と第1の閾値電圧とを比較する第1の比較手段と、
上記補償手段によって伝送路減衰が補償された差動電圧と第2の閾値電圧とを比較する第2の比較手段と、
上記第1の比較手段と上記第2の比較手段の何れかの比較結果を上記NRZ信号の再生信号として選択する選択手段と、
上記選択手段にて選択された再生信号を所定のサンプリングクロック信号に基づいて複数段シフトさせるシフトレジスタ手段と、
上記シフトレジスタ手段における各タップ出力と上記第1、第2の比較手段からの比較結果とに応じて上記選択手段における信号選択を制御する制御手段と
を備えるデータ受信装置。 - 上記制御手段は、上記シフトレジスタ手段の一のタップ出力により上記選択手段における信号選択を制御し、上記第1の比較手段からの比較結果と第2の比較手段からの比較結果との不一致を検出する不一致検出結果、又は上記シフトレジスタ手段の上記一のタップ出力に対して上記第1、第2の比較手段からの比較結果が期待する出力でないことを検出する期待値外検出結果のいずれかが得られたとき、上記シフトレジスタ手段のタップ出力を変更し、変更されたタップ出力により上記選択手段における信号選択を制御する
請求項1記載のデータ受信装置。 - 上記選択手段にて選択された上記NRZ信号の再生信号と上記基準クロック信号に周波数同期したクロック信号とを位相同期させる位相同期手段を備える請求項2記載のデータ受信装置。
- 差動導電体対を介して伝送されるNRZ信号を受信するデータ受信装置において、
上記NRZ信号のクロックの分周信号を受信して逓倍し基準クロック信号とする逓倍手段と、
上記分周信号の伝送路である上記差動導電体対における減衰特性を推定する推定手段と、
上記推定手段にて推定された減衰特性に応じて上記NRZ信号の伝送路減衰を補償する補償手段と、
上記補償手段によって伝送路減衰が補償された差動電圧と第1の閾値電圧とを比較する第1の比較手段と、
上記補償手段によって伝送路減衰が補償された差動電圧と第2の閾値電圧とを比較する第2の比較手段と、
上記第1の比較手段と上記第2の比較手段の何れかの比較結果を上記NRZ信号の再生信号として選択する選択手段と、
上記選択手段にて選択された再生信号を上記逓倍手段から得られた基準クロック信号に基づいて複数段シフトさせるシフトレジスタ手段と、
上記シフトレジスタ手段における各タップ出力と上記第1、第2の比較手段からの比較結果とに応じて上記選択手段における信号選択を制御する制御手段と
を備えるデータ受信装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003314821A JP4269855B2 (ja) | 2003-09-05 | 2003-09-05 | データ受信装置 |
US10/933,872 US7418038B2 (en) | 2003-09-05 | 2004-09-03 | Data receiving device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003314821A JP4269855B2 (ja) | 2003-09-05 | 2003-09-05 | データ受信装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005086379A JP2005086379A (ja) | 2005-03-31 |
JP4269855B2 true JP4269855B2 (ja) | 2009-05-27 |
Family
ID=34415264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003314821A Expired - Lifetime JP4269855B2 (ja) | 2003-09-05 | 2003-09-05 | データ受信装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7418038B2 (ja) |
JP (1) | JP4269855B2 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100682822B1 (ko) * | 2005-08-30 | 2007-02-15 | 엘지전자 주식회사 | 고속 라인 등화기 및 그 방법 |
US7639598B2 (en) * | 2006-01-31 | 2009-12-29 | Szabolcs Sovenyi | Simultaneous full-duplex communication over a single electrical conductor |
US8355428B2 (en) | 2006-11-09 | 2013-01-15 | Sony Corporation | Data receiving device |
JP5018027B2 (ja) * | 2006-11-09 | 2012-09-05 | ソニー株式会社 | データ受信装置 |
US8155215B2 (en) * | 2007-06-29 | 2012-04-10 | Advantest Corporation | Transmission system, transmitter, receiver, and transmission method |
US7698491B1 (en) * | 2007-09-26 | 2010-04-13 | Emc Corporation | Modular patch panel with pluggable personalities |
EP2238708B1 (en) * | 2007-12-06 | 2014-01-22 | Rambus Inc. | Apparatus and methods for differential signal receiving |
KR101448919B1 (ko) | 2007-12-28 | 2014-10-13 | 삼성전자주식회사 | 데이터 신호들과 클락 사이의 스큐를 제거하기 위한 디스큐시스템 및 이를 위한 회로들 |
CN102769509B (zh) * | 2012-06-07 | 2015-10-21 | 华为技术有限公司 | 一种物理层信号的发送方法、装置及系统 |
US9166844B2 (en) * | 2012-11-16 | 2015-10-20 | Rambus Inc. | Receiver with duobinary mode of operation |
KR20140109131A (ko) * | 2013-03-05 | 2014-09-15 | 삼성전자주식회사 | 이미지 데이터를 압축/압축해제할 수 있는 디스플레이 인터페이스, 이의 동작 방법, 및 이를 포함하는 디스플레이 장치 |
JP6504354B2 (ja) * | 2014-05-22 | 2019-04-24 | パナソニックIpマネジメント株式会社 | 受信装置 |
CN107995135B (zh) * | 2017-10-31 | 2021-07-23 | 北京集创北方科技股份有限公司 | 信道衰减补偿系统、方法、电路、存储介质及处理器 |
KR102490577B1 (ko) * | 2018-04-17 | 2023-01-25 | 에스케이하이닉스 주식회사 | 수신 회로, 이를 이용하는 반도체 장치 및 반도체 시스템 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH057230A (ja) | 1991-06-26 | 1993-01-14 | Nec Corp | 同期データ・インターフエース回路 |
US6577689B1 (en) * | 1998-04-24 | 2003-06-10 | Cirrus Logic, Inc. | Timing recovery system for a 10 BASE-T/100 BASE-T ethernet physical layer line interface |
JP3671702B2 (ja) | 1998-10-16 | 2005-07-13 | 富士ゼロックス株式会社 | 差動信号による信号伝送システムの電磁波抑制装置 |
JP3398955B2 (ja) | 1999-07-01 | 2003-04-21 | 日本電気株式会社 | 並列光信号伝送用のアレイ送信回路およびアレイ受信回路 |
US20040096004A1 (en) * | 2002-11-15 | 2004-05-20 | Stmicroelectronics, Inc. | Asymmetrical ethernet transceiver for long reach communications |
-
2003
- 2003-09-05 JP JP2003314821A patent/JP4269855B2/ja not_active Expired - Lifetime
-
2004
- 2004-09-03 US US10/933,872 patent/US7418038B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005086379A (ja) | 2005-03-31 |
US7418038B2 (en) | 2008-08-26 |
US20050084020A1 (en) | 2005-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4269855B2 (ja) | データ受信装置 | |
US8396105B2 (en) | Data communication circuit with equalization control | |
US8774262B2 (en) | Adaptive equalization with group delay | |
CN112868181B (zh) | 低延迟组合式时钟数据恢复逻辑网络及电荷泵电路 | |
US10560146B2 (en) | Method and system for calibrating multi-wire skew | |
US11784782B2 (en) | Method for measuring and correcting multi-wire skew | |
US8804889B2 (en) | Receiver with dual clock recovery circuits | |
US8379711B2 (en) | Methods and apparatus for decision-feedback equalization with oversampled phase detector | |
KR100593784B1 (ko) | 위상 제어를 샘플링하기 위한 방법 | |
TW200937925A (en) | Clock data recovery device | |
WO2008044407A1 (fr) | Dispositif de récupération de données d'horloge | |
US7545861B2 (en) | Timing recovery circuit and timing recovery method | |
KR20210141718A (ko) | 클록 복구 없는 가변 이득 증폭기 및 샘플러 오프셋 캘리브레이션 | |
US20070030890A1 (en) | Partial response transmission system and equalizing circuit thereof | |
US6570916B1 (en) | Adaptive equalization circuit and method | |
US11675732B2 (en) | Multiphase data receiver with distributed DFE | |
US9258109B2 (en) | Clock recovery method and apparatus | |
US11231740B2 (en) | Clock recovery using between-interval timing error estimation | |
WO2009040371A1 (en) | Clock recovery using a tapped delay line | |
US20030014683A1 (en) | Receiver with automatic skew compensation | |
JP5540472B2 (ja) | シリアルデータ受信機、利得制御回路および利得制御方法 | |
JP6273697B2 (ja) | 受信回路および受信方法 | |
US20070177702A1 (en) | Receiving data over channels with intersymbol interference | |
WO2017037836A1 (ja) | 信号伝送装置および信号伝送システム | |
US20230308064A1 (en) | Variable gain amplifier with cross-coupled common mode reduction |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080318 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080519 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090203 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090216 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120306 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120306 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120306 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130306 Year of fee payment: 4 |