JP4245053B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4245053B2 JP4245053B2 JP2007015183A JP2007015183A JP4245053B2 JP 4245053 B2 JP4245053 B2 JP 4245053B2 JP 2007015183 A JP2007015183 A JP 2007015183A JP 2007015183 A JP2007015183 A JP 2007015183A JP 4245053 B2 JP4245053 B2 JP 4245053B2
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- Prior art keywords
- diode
- voltage dividing
- dividing resistor
- transistors
- voltage
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- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims description 50
- 238000012360 testing method Methods 0.000 claims description 36
- 238000009499 grossing Methods 0.000 claims description 32
- 238000007689 inspection Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 25
- 239000000758 substrate Substances 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Power Conversion In General (AREA)
Description
以下、本発明の第1実施形態について図を参照して説明する。本実施形態で示される半導体装置は、例えば15Vの低電圧領域と例えば600Vの高電圧領域との間で信号伝達を行うためのレベルシフト素子として適用されるものである。
本実施形態では、第1実施形態と異なる部分についてのみ説明する。上記第1実施形態では、LDMOSトランジスタ10としてNch型のものを採用しているが、本実施形態では、Pch型のものを用いることが特徴となっている。
本実施形態では、第1、第2実施形態と異なる部分についてのみ説明する。上記各実施形態では、LDMOSトランジスタ10の各ゲート間に平滑コンデンサ70を1つ接続していたが、本実施形態では平滑コンデンサ70に加えてさらに他のコンデンサを並列接続することが特徴となっている。
上記各実施形態では、LDMOSトランジスタ10は三段に構成されているが、レベルシフト素子として必要とする耐圧に応じて段数を設定することができる。また、タンデム構造を構成するトランジスタとして、LDMOSトランジスタ10の他にIGBTを採用することもできる。
Claims (2)
- 互いに絶縁分離され、グランド電位と一定電圧との間で直列接続された複数のトランジスタ(10、90)と、
前記複数のトランジスタ(10、90)において隣り合うトランジスタのゲート間に直列接続された分圧抵抗(50)およびダイオード(60)と、
前記複数のトランジスタ(10、90)において隣り合うトランジスタのゲート間に接続されると共に、前記分圧抵抗(50)と前記ダイオード(60)との直列接続に対して並列に接続されたコンデンサ(70、71)と、
前記複数のトランジスタ(10、90)の各ゲートにそれぞれ接続された検査パッド(20)とを備え、
前記ダイオード(60)は、前記複数のトランジスタ(10、90)がオンになった場合に前記分圧抵抗(50)に電流が流れるように前記分圧抵抗(50)に直列接続されており、
前記ダイオード(60)に順方向バイアスを与えるように前記検査パッド(20)間に電圧が印加されると、前記検査パッド(20)間に前記分圧抵抗(50)および前記ダイオード(60)を経由する経路が形成されるようになっており、
前記ダイオード(60)に逆方向バイアスを与えるように前記検査パッド(20)間に電圧が印加されると、前記検査パッド(20)間に前記コンデンサ(70、71)を経由する経路が形成されるようになっていることを特徴とする半導体装置。 - 互いに絶縁分離され、グランド電位と一定電位との間で直列接続された複数のトランジスタ(10、90)と、
前記複数のトランジスタ(10、90)において隣り合うトランジスタのゲート間に直列接続された分圧抵抗(50)およびダイオード(60)と、
前記複数のトランジスタ(10、90)において隣り合うトランジスタのゲート間に接続されると共に、前記分圧抵抗(50)と前記ダイオード(60)との直列接続に対して並列に接続されたコンデンサ(70、71)と、
前記複数のトランジスタ(10、90)の各ゲートにそれぞれ接続された検査パッド(20)とを備え、
前記複数のトランジスタ(10、90)がオンになった場合に前記分圧抵抗(50)に電流が流れるように前記分圧抵抗(50)に前記ダイオード(60)が直列接続された半導体装置の製造方法であって、
前記ダイオード(60)に順方向バイアスを与えるように前記検査パッド(20)間に電圧を印加し、前記検査パッド(20)間に前記分圧抵抗(50)および前記ダイオード(60)を経由する経路を形成することで、前記分圧抵抗(50)の抵抗値を検査する分圧抵抗検査工程と、
前記ダイオード(60)に逆方向バイアスを与えるように前記検査パッド(20)間に電圧を印加し、前記検査パッド(20)間に前記コンデンサ(70、71)を経由する経路を形成することで、前記コンデンサ(70、71)のリーク電流を検査する平滑コンデンサ検査工程とを含んでいることを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007015183A JP4245053B2 (ja) | 2007-01-25 | 2007-01-25 | 半導体装置およびその製造方法 |
US12/010,111 US7821069B2 (en) | 2007-01-25 | 2008-01-22 | Semiconductor device and method for manufacturing the same |
DE102008006124A DE102008006124B4 (de) | 2007-01-25 | 2008-01-25 | Halbleitervorrichtung und Verfahren zu deren Fertigung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007015183A JP4245053B2 (ja) | 2007-01-25 | 2007-01-25 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008182108A JP2008182108A (ja) | 2008-08-07 |
JP4245053B2 true JP4245053B2 (ja) | 2009-03-25 |
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JP2007015183A Expired - Fee Related JP4245053B2 (ja) | 2007-01-25 | 2007-01-25 | 半導体装置およびその製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107808633A (zh) * | 2017-11-14 | 2018-03-16 | 京东方科技集团股份有限公司 | 像素电路、显示面板和显示装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5093197B2 (ja) * | 2009-07-27 | 2012-12-05 | タイヨーエレック株式会社 | 遊技機 |
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- 2007-01-25 JP JP2007015183A patent/JP4245053B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107808633A (zh) * | 2017-11-14 | 2018-03-16 | 京东方科技集团股份有限公司 | 像素电路、显示面板和显示装置 |
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