JP4237851B2 - Circuit member for resin-encapsulated semiconductor device and manufacturing method thereof - Google Patents

Circuit member for resin-encapsulated semiconductor device and manufacturing method thereof Download PDF

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JP4237851B2
JP4237851B2 JP32131498A JP32131498A JP4237851B2 JP 4237851 B2 JP4237851 B2 JP 4237851B2 JP 32131498 A JP32131498 A JP 32131498A JP 32131498 A JP32131498 A JP 32131498A JP 4237851 B2 JP4237851 B2 JP 4237851B2
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outer frame
frame member
die pad
plating
circuit member
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JP2000133764A (en
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寛明 宮澤
日出男 堀田
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子を搭載した樹脂封止型の半導体装置の製造に用いる回路部材と、その製造方法に関する。
【０００２】
【従来の技術】
近年、半導体装置は、高集積化や小型化技術の進歩、電気機器の高性能化と小型化の傾向から、ＬＳＩのＡＳＩＣに代表されるように、ますます高集積化、高機能化が進んできている。このように高集積化、高機能化された半導体装置においては、信号の高速処理を行うために、パッケージ内のインダクタンスが無視できない状況になってきている。このため、電源やグランドの接続端子数を多くして実質的なインダクタンスを下げ、パッケージ内のインダクタンスを低減することで対応がなされている。このように、半導体装置の高集積化、高機能化は、外部端子（ピン）の総和の増加を来すとともに、更なる多端子（ピン）化が要請されている。
【０００３】
上記のような多端子（ピン）化の要請に応えるものとして、高精細なリードフレーム等、および、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）に代表される様々な樹脂封止型の半導体装置等が普及してきた。これによりチップサイズでの実装が可能となり、より小型化、軽量化といた要請を満たしてきた。
【０００４】
【発明が解決しようとする課題】
しかし、従来の樹脂封止型半導体装置では、端子部やダイパッドと封止樹脂との密着性が問題となっていた。すなわち、端子部やダイパッドと封止樹脂との密着性が悪い場合、半導体装置の製造途中あるいは使用中に剥離（デラミネーション）を生じ、この剥離が原因で封止樹脂のクラックが発生し、これにより半導体装置の信頼性が損なわれ、耐久性が保てないという重大な欠陥を生じることある。
【０００５】
このため、樹脂封止型半導体装置に使用する回路部材に微小凹部をハーフエッチングで形成（ディンプル加工）したり、剥離の発生率が比較的高いダイパッドを半導体素子に比較して小さくする等の対応がなされている。しかしながら、上記のディンプル加工では、ダイパッドと封止樹脂との密着性向上の効果が不十分であり、また、ダイパッドの小面積化は、半導体素子の搭載に高い技術が必要になるという問題がある。
【０００６】
また、端子部に金、銀、パラジウム等の貴金属めっき部材を設けている場合、このような貴金属は基本的に封止樹脂との密着性が悪いので、半導体装置外部の水分が貴金属めっき部材と封止樹脂との界面から浸入する危険性がある。このような水分の浸入が発生すると、半導体装置内部で回路と樹脂が剥れるといった、いわゆるパッケージクラック等が生じ、半導体装置の信頼性に大きな支障を来すことになる。
【０００７】
本発明は、上記のような事情に鑑みてなされたものであり、封止樹脂との密着性に優れ、耐久性、信頼性が高い樹脂封止型半導体装置の製造を可能とする回路部材と、この回路部材の製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
このような目的を達成するために、本発明の樹脂封止型半導体装置用の回路部材は、外枠部材と、該外枠部材から各々接続リードを介して相互に独立して配設された複数の端子部と、前記外枠部材から接続リードを介して配設されたダイパッドとを備える回路部材であって、前記端子部は少なくとも側面部にめっき薄膜を有し、前記ダイパッドは少なくとも一方の面に凹部を有するとともに該凹部と側面部とにめっき薄膜を有し、前記めっき薄膜は回路部材の表面に突出する突起部を有するような構成とした。
【０００９】
本発明は、外枠部材と、該外枠部材から各々接続リードを介して相互に独立して配設された複数の端子部と、前記外枠部材から接続リードを介して配設されたダイパッドとを備えた回路部材の製造方法において、導電性基板の両面に所定の形状でレジストパターンを形成し、該レジストパターンを耐腐蝕膜として前記導電性基板をエッチングして、外枠部材と、接続リードを介して相互に独立するように前記外枠部材に連結された複数の端子部と、接続リードを介して前記外枠部材に連結され少なくとも一方の面に凹部を有するダイパッドを形成するエッチング工程と、エッチングされた部位に突出している前記レジストパターンのオーバーハング部を除去するレジスト部分除去工程と、前記レジストパターンをマスクとして導電性基板の露出部にめっきを行って、導電性基板の表面から突出する突起部を有するめっき薄膜を外枠部材と端子部と接続リードの側面部、ダイパッドと接続リードの側面部、および、ダイパッドの凹部内に設けるめっき工程と、レジストパターンを除去するレジスト除去工程と、を有するような構成とした。
【００１０】
また、本発明の回路部材の製造方法は、前記レジスト除去工程の後に、前記端子部の少なくとも一部に半導体素子との接続用のめっき部材を形成するめっき工程を有するような構成とした。
【００１１】
さらに、本発明の回路部材の製造方法は、前記レジスト部分除去工程は、粘着部材を使用する方法、ウエットブラストまたはドライブラストを使用した方法、超音波を使用した方法のいずれかにより行われるような構成とした。
【００１２】
このような本発明では、端子部やダイパッドの側面部に位置するめっき薄膜の突起部、および、ダイパッドの凹部に位置するめっき薄膜の突起部が、回路部材の表面に突出して、封止樹脂に端子部、ダイパッドを確実に固定する作用をなすとともに、外部からめっき薄膜と封止樹脂との界面に侵入した水分に対して侵入を遮断する作用をなす。
【００１３】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。
本発明の回路部材
図１は本発明の回路部材の一実施形態を示す平面図、図２は図１に示される回路部材のＡ−Ａ線における縦断面図である。図１および図２において、本発明の回路部材１は、外枠部材２と、この外枠部材２から接続リード４を介して相互に独立して配設された複数の端子部３と、外枠部材２から接続リード９を介して配設されたダイパッド７とを備えている。上記ダイパッド７は、その裏面７Ｂに複数の凹部８を備えている。そして、回路部材１は、端子部３の側面部とダイパッド７の側面部、および、ダイパッド７の凹部８にめっき薄膜５を備えている。
【００１４】
外枠部材２は、内側開口形状が矩形であり、各接続リード４は外枠部材２の内側開口の各辺から同一平面内に突設されている。
【００１５】
端子部３は、接続リード４の先端に設けられ、先端側に半導体素子との接続部位である内部端子３ａを、接続リード４寄りに外部端子３ｂを有している。図３は、このような端子部３の部分斜視図であり、図４は図３のＢ−Ｂ線における縦断面図である。図３および図４に示されるように、端子部３の側面部にはめっき薄膜５が設けられている。このめっき薄膜５は、回路部材１の表面に突出（図４の矢印ａ方向、矢印ｂ方向に突出）するように突起部５ａを有している。また、端子部３の内部端子３ａの表面には半導体素子の端子との接続用のめっき部材６が設けられている。このめっき部材６は、金、パラジウム、銀等のいずれかからなる単層めっきであり、厚みは２〜５μｍ程度である。
【００１６】
ダイパッド７は、外枠部材２の内側開口の各隅部から延設された４本の接続リード９に支持され、裏面７Ｂ側には複数の凹部８が形成されている。図５は、このようなダイパッド７の裏面７Ｂ側の部分斜視図であり、図６は図５のＣ−Ｃ線における縦断面図である。図５および図６において、ダイパッド７の裏面７Ｂ側に設けられた凹部８は、略半球形状の凹部（ディンプル）であり、ダイパッド７と接続リード９の側面部、および、ダイパッド７の凹部８にめっき薄膜５を備えている。このめっき薄膜５は、回路部材１の表面に突出（図５の矢印ａ方向、矢印ｂ方向に突出）するように突起部５ａを有している。凹部８の形状は略半球形状に限定されるものではなく、例えば、溝形状のもの等いずれであってもよい。凹部８の形状、寸法、個数等は適宜設定することができるが、凹部８の開口部８ａに存在する突起部５ａの開口幅は、封止樹脂の凹部８内への侵入の容易さを考慮して１００〜５００μｍの範囲内であることが好ましい。
【００１７】
上記のめっき薄膜５は、例えば、ニッケル、ニッケル合金等のいずれかからなる単層めっきとすることができ、厚みは４〜９μｍ程度である。このめっき薄膜５の突起部５ａの回路部材１の表面からの突出量（図４のＷ１、図６のＷ３）、および、突起部５ａのめっき薄膜５から側面方向への突出量（図４のＷ２、図６のＷ４）は、３〜８μｍ程度の範囲にある。
【００１８】
尚、めっき薄膜５の表面は粗面化処理が施されたものであってもよい。例えば、めっき薄膜５の表面を粗面とするために、ニッケルめっき浴として日本高純度化学（株）製ＷＨＭ浴を用いることができる。この場合、めっき薄膜５の表面粗さＲａは３４〜６２ｎｍ程度に設定することができる。
【００１９】
このような回路部材１の材質は、４２合金（Ｎｉ４１％のＦｅ合金）、銅、銅合金等とすることができる。
【００２０】
また、本発明の回路部材１は、ダイパッド７の表面７Ａ（半導体素子搭載面）側に電気絶縁性の両面接着テープを設けたものであってもよい。両面接着テープは、電気絶縁性のベースフィルムの両面に接着剤層を備えたもの、例えば、ユーピレックス（宇部興産（株）製の電気絶縁性のベースフィルム）の両面にＲＸＦ（（株）巴川製紙所製の接着剤）層を備えたＵＸ１Ｗ（（株）巴川製紙所製）のような両面接着テープを使用することができる。
【００２１】
尚、上述の回路部材１における端子数、端子配列等は例示であり、本発明の回路部材がこれに限定されるものではない。また、上述の回路部材１では、ダイパッドの裏面側に複数の凹部が形成されているが、表面側に半導体素子搭載領域外に余地がある場合、この部分に凹部を設けてもよい。
【００２２】
さらに、上述の回路部材１では、めっき薄膜５は、回路部材１の両面に突起部５ａを突出させているが、回路部材１の一方の面に突起部５ａを突出させたもの、部位によって適宜回路部材１のいずれかの面に突起部５ａを突出させたもの等であってもよい。
本発明の回路部材の製造方法
次に、本発明の回路部材の製造方法について説明する。
【００２３】
図７は、図１乃至図６に示される本発明の回路部材１を例とした本発明の回路部材の製造方法の一実施形態を示す工程図である。各工程は、上記の図２に対応する回路部材の縦断面図で示してある。
【００２４】
図７において、まず、導電性基板２１の両面に感光性レジストを塗布、乾燥し、これを所望のフォトマスクを介して露光した後、現像して、導電性基板２１の表面側にレジストパターン２２Ａを、裏面側にレジストパターン２２Ｂを形成する（図７（Ａ））。導電性基板２１としては、上述のように４２合金（Ｎｉ４１％のＦｅ合金）、銅、銅合金等の金属基板（厚み１００〜２５０μｍ）を使用することができ、この導電性基板２１は、両面を脱脂等を行い洗浄処理を施したものを使用することが好ましい。感光性レジストとしては、従来公知のものを使用することができ、また、感光性のドライフィルムをラミネートして露光、現像してもよい。次いで、レジストパターン２２Ａ，２２Ｂを耐腐蝕膜として導電性基板２１に対して腐蝕液でエッチングを行う（図７（Ｂ）エッチング工程）。腐蝕液は、通常、塩化第二鉄水溶液を使用し、導電性基板２１の両面からスプレーエッチングにて行う。このエッチング工程により、外枠部材２と、接続リード４を介して相互に独立するように外枠部材２に連結された複数の端子部３と、接続リード９（図示せず）を介して外枠部材２に連結されたダイパッド７が形成される。このダイパッド７に裏面７Ｂ側には、複数の凹部８がハーフエッチングにより形成されている。尚、エッチングで除去された導電性基板２１の側面部は、レジストパターン２２Ａ，２２Ｂよりも内側まで腐蝕除去されてアンダーカット形状となっている。
【００２５】
次いで、レジストパターン２２Ａ，２２Ｂのうち、エッチングされたアンダーカット部位に突出しているレジストパターンのオーバーハング部２２ａ，２２ｂを除去する（図７（Ｃ）レジスト部分除去工程）。図示例では、外枠部材２、端子部３、接続リード４およびダイパッド７の各周縁部に突出しているレジストパターンのオーバーハング部２２ａ，２２ｂと、ダイパッド７の凹部８に突出しているレジストパターンのオーバーハング部２２ｂとが除去される。
【００２６】
このレジストパターンのオーバーハング部２２ａ，２２ｂの除去は、例えば、粘着部材を使用して行うことができる。この方法は、粘着部材を周面に設けたローラをレジストパターン２２Ａ，２２Ｂ上に回転移動させたり、テープ状あるいはフィルム状の粘着部材をレジストパターン２２Ａ，２２Ｂ上に貼合した後剥離すること等により実施できる。この場合、粘着部材の粘着力は、レジストパターンとの密着性が良好で、かつ、導電性基板２１とレジストパターン２２Ａ，２２Ｂとの密着力よりも劣ることが必要がある。具体的には、テープ状粘着部材を用いる場合、レジストパターンに対する剥離力が１５０〜４００ｇ／ｃｍ（剥離速度１００ｍｍ／秒、剥離角度９０〜１１５°）程度が好ましく、また、粘着ローラを用いる場合、レジストパターンに対する剥離力が３００〜８００ｇ／ｃｍ（剥離速度６０〜９０ｍｍ／秒、剥離角度１５〜３０°）程度が好ましい。粘着部材としては、例えば、ニチバン（株）製セロハンテープ、ニッタ（株）製のアクリル系クールオフ感熱性粘着剤等を用いることができる。特に後者は、３０℃以上で粘着力が増し、常温でほとんど粘着力がないという性質を利用し、１０回以上の再利用が可能である。
【００２７】
また、レジストパターンのオーバーハング部２２ａ，２２ｂの除去は、ブラスト法により行うこともできる。この場合、使用する粒子の粒径は５０〜７０μｍ程度であり、２ｋｇ程度の吹き付け圧力で行うことができ、粒径、圧力とも使用するレジスト材料によって適宜設定する必要がある。また、レジストパターンはブラスト処理により必要なパターン部位まで破壊されないように５μｍ以上の厚みにすることが好ましいが、この厚みも使用するレジスト材料によって適宜設定する必要がある。さらに、レジストパターンのオーバーハング部２２ａ，２２ｂを超音波を使用して除去することも可能である。
【００２８】
次いで、残っているレジストパターン２２Ａ，２２Ｂをマスクとして、導電性基板２１の露出部にめっきを行う（図７（Ｄ）めっき工程）。このめっき工程では、上述のようにレジストパターンのオーバーハング部２２ａ，２２ｂが除去された導電性基板２１のアンダーカット部位において、めっきの着き回り性が向上するとともに、導電性基板２１に対して垂直方向（図７（Ｄ）の矢印ａ方向、矢印ｂ方向）へもめっきが成長する。これにより、外枠部材２と端子部３と接続リード４の側面部、および、ダイパッド７と接続リード９（図示せず）の側面部にめっき薄膜５が形成されるとともに、ダイパッド７の凹部８内にめっき薄膜５が形成され、このめっき薄膜５は導電性基板２１の表面から突出するように突起部５ａを備えたものとなる。
【００２９】
次いで、レジストパターン２２Ａ，２２Ｂを剥離して除去することにより、端子部３とダイパッド７がそれぞれ接続リード４と接続リード９（図示せず）により外枠部材２に一体的に連結された回路部材が得られる（図７（Ｅ））。この回路部材の端子部３の所定位置に、端子接続用のめっき部材６を形成して、図１乃至図６に示される本発明の回路部材１が得られる（図７（Ｆ））。
【００３０】
尚、めっき工程で形成しためっき薄膜５に樹脂封止部材との密着性を向上させるために、化学的結合強化処理や粗面化処理（物理的結合強化処理）を施してもよい。粗面化処理は、Ｚｎ−Ｃｒ合金等のめっき層形成（米国オーリン社のＡ２プロセス）、もしくはニッケルめっきに対する種々のクロメート処理等が挙げられ、めっき薄膜５の表面粗さＲａを３０ｎｍ以上程度に設定することが好ましい。このような粗面化処理を施すことにより、めっき薄膜５の封止樹脂に対する密着性が更に向上する。
【００３１】
次に、本発明の回路部材１を用いた樹脂封止型半導体装置の製造方法について、図８を参照して説明する。
【００３２】
図８において、まず、上述の本発明の製造方法により製造した回路部材１を用い、この回路部材１のダイパッド７の表面７Ａ側に半導体素子５２の回路形成面反対側を電気絶縁性の両面接着テープ５５を介して固着することにより、半導体素子５２を搭載する（図８（Ａ））。
【００３３】
次に、搭載した半導体素子５２の端子５２ａと、回路部材の内部端子３ａのめっき部材６とを、ボンディングワイヤ５４で電気的に接続する（図８（Ｂ））。
【００３４】
次いで、端子部３、ダイパッド７、半導体素子５２およびボンディングワイヤ５４を封止樹脂５６で封止する（図８（Ｃ））。次いで、回路部材１の各接続リード４および接続リード９を切断し外枠部材２を除去し、封止樹脂５６から突出している外部端子３ｂを所定の形状に加工して、樹脂封止型の半導体装置５１を得ることができる（図８（Ｄ））。
【００３５】
【発明の効果】
以上詳述したように、本発明によれば端子部やダイパッドの側面部、および、ダイパッドの凹部に位置するめっき薄膜の突起部が三次元的に封止樹脂に食い込むことにより、端子部やダイパッドが確実に固定されるので、端子部やダイパッドと封止樹脂との剥離が防止され、また、上記の突起部によって、外部から端子部と封止樹脂との界面に浸入した水分の浸入経路が遮断され、いわゆるパッケージクラックが防止され信頼性に優れた樹脂封止型の半導体装置が可能となり、このような回路部材は、上記突起部の形成部位においてレジストパターンのオーバーハング部を除去することにより、めっきの着き回り性を高めた本発明の製造方法により簡便に製造することができる。さらに、回路部材の素材である銅のマイグレーションが生じやすい端子部等の部位においても、側面部にめっき薄膜が配設されているので、マイグレーションが防止されるという効果も奏される。
【図面の簡単な説明】
【図１】本発明の回路部材の一実施形態を示す平面図である。
【図２】図１に示される回路部材のＡ−Ａ線における縦断面図である。
【図３】図１に示される回路部材の端子部の部分拡大斜視図である。
【図４】図３に示される端子部のＢ−Ｂ線における縦断面図である。
【図５】図１に示される回路部材のダイパッドの裏面側の部分拡大斜視図である。
【図６】図５に示されるダイパッドのＣ−Ｃ線における縦断面図である。
【図７】本発明の回路部材の製造方法の一実施形態を示す工程図である。
【図８】本発明の回路部材を用いた樹脂封止型半導体装置の製造方法の一例を示す工程図である。
【符号の説明】
１…回路部材
２…外枠部材
３…端子部
３ａ…内部端子
３ｂ…外部端子
４，９…接続リード
５…めっき薄膜
５ａ…突起部
６…めっき部材
７…ダイパッド
８…凹部
２１…導電性基板
２２Ａ，２２Ｂ…レジストパターン
２２ａ，２２ｂ…レジストパターンのオーバーハング部
５１…樹脂封止型半導体装置
５２…半導体素子
５２ａ…端子
５４…ワイヤ
５６…封止樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit member used for manufacturing a resin-encapsulated semiconductor device on which a semiconductor element is mounted, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, semiconductor devices are becoming increasingly highly integrated and highly functional, as represented by LSI ASICs, due to advances in high integration and miniaturization technologies, and high performance and miniaturization of electrical equipment. is made of. In such highly integrated and highly functional semiconductor devices, in order to perform high-speed signal processing, the inductance in the package cannot be ignored. For this reason, the countermeasure is taken by increasing the number of connection terminals of the power supply and the ground to lower the substantial inductance and reducing the inductance in the package. As described above, higher integration and higher functionality of a semiconductor device increase the total number of external terminals (pins), and further demand for more terminals (pins).
[0003]
In order to meet the demand for multi-terminals (pins) as described above, various resin-encapsulated types represented by high-definition lead frames, BGA (Ball Grid Array), and CSP (Chip Size Package) Semiconductor devices and the like have become widespread. As a result, mounting in a chip size is possible, and the demands for further miniaturization and weight reduction have been satisfied.
[0004]
[Problems to be solved by the invention]
However, in the conventional resin-encapsulated semiconductor device, the adhesion between the terminal portion or die pad and the encapsulating resin has been a problem. That is, when the adhesion between the terminal part or die pad and the sealing resin is poor, peeling (delamination) occurs during the manufacture or use of the semiconductor device, and the cracking of the sealing resin occurs due to this peeling. As a result, the reliability of the semiconductor device is impaired, and a serious defect that durability cannot be maintained may occur.
[0005]
For this reason, it is possible to form micro-recesses by half-etching (dimple processing) on circuit members used in resin-encapsulated semiconductor devices, and to reduce die pads with relatively high delamination rates compared to semiconductor elements. Has been made. However, in the above dimple processing, the effect of improving the adhesion between the die pad and the sealing resin is insufficient, and the reduction in area of the die pad has a problem that a high technology is required for mounting a semiconductor element. .
[0006]
In addition, when a noble metal plating member such as gold, silver, or palladium is provided in the terminal portion, such a noble metal basically has poor adhesion to the sealing resin, so that moisture outside the semiconductor device is separated from the noble metal plating member. There is a risk of entering from the interface with the sealing resin. When such moisture intrusion occurs, so-called package cracks such as peeling of the circuit and resin inside the semiconductor device occur, which greatly impedes the reliability of the semiconductor device.
[0007]
The present invention has been made in view of the above circumstances, and a circuit member that enables the manufacture of a resin-encapsulated semiconductor device that has excellent adhesion to a sealing resin and is highly durable and reliable. An object of the present invention is to provide a method for manufacturing the circuit member.
[0008]
[Means for Solving the Problems]
In order to achieve such an object, the circuit member for the resin-encapsulated semiconductor device of the present invention is arranged independently of each other from the outer frame member and the outer frame member via connection leads. a plurality of terminals, a circuit member for Ru and a disposed the die pad via the connection leads from the outer frame member, the terminal portion has a plated film on at least the side surface portion, the die pad is at least one In addition, a concave portion is formed on the surface, and a plating thin film is formed on the concave portion and the side surface portion, and the plating thin film has a protruding portion protruding on the surface of the circuit member.
[0009]
The present invention relates to an outer frame member, a plurality of terminal portions arranged independently of each other from the outer frame member via connection leads, and a die pad arranged from the outer frame member via connection leads. And forming a resist pattern in a predetermined shape on both surfaces of the conductive substrate, etching the conductive substrate using the resist pattern as a corrosion-resistant film, and connecting to the outer frame member Etching process for forming a plurality of terminal portions connected to the outer frame member so as to be independent from each other via leads, and a die pad connected to the outer frame member via a connection lead and having a recess on at least one surface A resist part removing step for removing an overhang portion of the resist pattern protruding from the etched portion, and exposing the conductive substrate using the resist pattern as a mask. Parts to perform plating, a plating film having a protruding portion protruding from the surface of the conductive substrate side surface portion of the outer frame member and the terminal portion and the connecting leads, the side surface portions of the die pad and the connection leads, and, in the recess of the die pad It has a configuration including a plating step to be provided and a resist removal step for removing the resist pattern.
[0010]
In addition, the circuit member manufacturing method of the present invention is configured to include a plating step of forming a plating member for connection to a semiconductor element on at least a part of the terminal portion after the resist removing step.
[0011]
Furthermore, in the method for producing a circuit member of the present invention, the resist portion removing step is performed by any one of a method using an adhesive member, a method using wet blast or drive last, and a method using ultrasonic waves. The configuration.
[0012]
In the present invention, the plating thin film protrusions located on the terminal portions and the side surfaces of the die pad and the plating thin film protrusions located in the recesses of the die pad protrude from the surface of the circuit member to form the sealing resin. It functions to securely fix the terminal portion and the die pad, and to block the penetration of moisture that has entered the interface between the plating thin film and the sealing resin from the outside.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Circuit member of the present invention FIG. 1 is a plan view showing an embodiment of a circuit member of the present invention, and FIG. 2 is a longitudinal sectional view taken along line AA of the circuit member shown in FIG. 1 and 2, a circuit member 1 according to the present invention includes an outer frame member 2, a plurality of terminal portions 3 arranged independently from each other through the connection lead 4 from the outer frame member 2, and an outer frame member 2. And a die pad 7 disposed from the frame member 2 via the connection lead 9. The die pad 7 includes a plurality of recesses 8 on the back surface 7B. The circuit member 1 includes the plating thin film 5 in the side surface portion of the terminal portion 3, the side surface portion of the die pad 7, and the concave portion 8 of the die pad 7.
[0014]
The outer frame member 2 has a rectangular inner opening shape, and each connection lead 4 protrudes in the same plane from each side of the inner opening of the outer frame member 2.
[0015]
The terminal portion 3 is provided at the tip of the connection lead 4, and has an internal terminal 3 a that is a connection portion with a semiconductor element on the tip side, and an external terminal 3 b that is close to the connection lead 4. FIG. 3 is a partial perspective view of such a terminal portion 3, and FIG. 4 is a longitudinal sectional view taken along line BB of FIG. As shown in FIGS. 3 and 4, a plating thin film 5 is provided on the side surface of the terminal portion 3. The plated thin film 5 has a protruding portion 5a so as to protrude from the surface of the circuit member 1 (projected in the directions of arrows a and b in FIG. 4). In addition, a plating member 6 for connection with a terminal of a semiconductor element is provided on the surface of the internal terminal 3 a of the terminal portion 3. The plating member 6 is a single layer plating made of any one of gold, palladium, silver and the like, and has a thickness of about 2 to 5 μm.
[0016]
The die pad 7 is supported by four connection leads 9 extending from each corner of the inner opening of the outer frame member 2, and a plurality of recesses 8 are formed on the back surface 7B side. FIG. 5 is a partial perspective view of such a die pad 7 on the back surface 7B side, and FIG. 6 is a longitudinal sectional view taken along the line CC in FIG. 5 and 6, the recess 8 provided on the back surface 7B side of the die pad 7 is a substantially hemispherical recess (dimple), and is formed on the side surface of the die pad 7 and the connecting lead 9 and the recess 8 of the die pad 7. A plating thin film 5 is provided. The plated thin film 5 has a protruding portion 5a so as to protrude from the surface of the circuit member 1 (projected in the directions of arrows a and b in FIG. 5). The shape of the concave portion 8 is not limited to a substantially hemispherical shape, and may be any groove shape, for example. The shape, size, number, and the like of the recesses 8 can be set as appropriate. However, the opening width of the protrusion 5a existing in the opening 8a of the recess 8 takes into consideration the ease of penetration of the sealing resin into the recess 8 And it is preferable that it exists in the range of 100-500 micrometers.
[0017]
Said plating thin film 5 can be made into single layer plating which consists of either nickel, nickel alloy etc., for example, and thickness is about 4-9 micrometers. The protruding amount of the protruding portion 5a of the plating thin film 5 from the surface of the circuit member 1 (W1 in FIG. 4, W3 in FIG. 6), and the protruding amount of the protruding portion 5a from the plating thin film 5 in the lateral direction (in FIG. 4) W2 and W4) in FIG. 6 are in the range of about 3 to 8 μm.
[0018]
In addition, the surface of the plating thin film 5 may be subjected to a roughening treatment. For example, in order to make the surface of the plating thin film 5 rough, a WHM bath manufactured by Japan High Purity Chemical Co., Ltd. can be used as the nickel plating bath. In this case, the surface roughness Ra of the plating thin film 5 can be set to about 34 to 62 nm.
[0019]
The material of the circuit member 1 can be 42 alloy (Ni 41% Fe alloy), copper, copper alloy, or the like.
[0020]
The circuit member 1 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface 7A (semiconductor element mounting surface) side of the die pad 7. A double-sided adhesive tape is one having an adhesive layer on both sides of an electrically insulating base film, for example, RXF (Yodogawa Paper Co., Ltd.) on both sides of Upilex (an electrically insulating base film manufactured by Ube Industries). A double-sided adhesive tape such as UX1W (manufactured by Yodogawa Paper) can be used.
[0021]
In addition, the number of terminals, the terminal arrangement, and the like in the circuit member 1 described above are examples, and the circuit member of the present invention is not limited thereto. Further, in the circuit member 1 described above, a plurality of recesses are formed on the back side of the die pad, but if there is room outside the semiconductor element mounting region on the front side, the recesses may be provided in this part.
[0022]
Further, in the circuit member 1 described above, the plating thin film 5 has the protrusions 5a protruding on both surfaces of the circuit member 1, but the protrusions 5a are protruded on one surface of the circuit member 1 as appropriate depending on the part. What protruded the protrusion part 5a on the any surface of the circuit member 1 may be sufficient.
Production method <br/> Next circuit member of the present invention, a method for manufacturing a circuit member of the present invention.
[0023]
FIG. 7 is a process diagram showing an embodiment of a method for producing a circuit member of the present invention, taking the circuit member 1 of the present invention shown in FIGS. 1 to 6 as an example. Each step is shown in a longitudinal sectional view of the circuit member corresponding to FIG.
[0024]
In FIG. 7, first, a photosensitive resist is applied to both surfaces of the conductive substrate 21, dried, exposed through a desired photomask, and then developed to form a resist pattern 22 </ b> A on the surface side of the conductive substrate 21. A resist pattern 22B is formed on the back side (FIG. 7A). As the conductive substrate 21, as described above, a metal substrate (thickness: 100 to 250 μm) such as 42 alloy (Ni 41% Fe alloy), copper, or copper alloy can be used. It is preferable to use a product that has been degreased and washed. As the photosensitive resist, a conventionally known one can be used, and a photosensitive dry film may be laminated and exposed and developed. Subsequently, the resist pattern 22A, 22B is used as an anticorrosion film, and the conductive substrate 21 is etched with an etching solution (FIG. 7B). As the corrosive liquid, a ferric chloride aqueous solution is usually used and spray etching is performed from both surfaces of the conductive substrate 21. By this etching process, the outer frame member 2, the plurality of terminal portions 3 connected to the outer frame member 2 so as to be independent from each other via the connection leads 4, and the connection leads 9 (not shown) are externally connected. A die pad 7 connected to the frame member 2 is formed. A plurality of recesses 8 are formed in the die pad 7 on the back surface 7B side by half etching. Note that the side surface portion of the conductive substrate 21 removed by etching is etched away to the inner side of the resist patterns 22A and 22B and has an undercut shape.
[0025]
Next, of the resist patterns 22A and 22B, the overhang portions 22a and 22b of the resist pattern protruding to the etched undercut portions are removed (FIG. 7C, resist portion removing step). In the illustrated example, the resist pattern overhang portions 22a and 22b projecting from the outer peripheral edge portion of the outer frame member 2, the terminal portion 3, the connection lead 4 and the die pad 7 and the resist pattern projecting into the concave portion 8 of the die pad 7 are illustrated. The overhang portion 22b is removed.
[0026]
The removal of the overhang portions 22a and 22b of the resist pattern can be performed using an adhesive member, for example. In this method, a roller provided with an adhesive member on its peripheral surface is rotated and moved onto the resist patterns 22A and 22B, or a tape-like or film-like adhesive member is bonded onto the resist patterns 22A and 22B and then peeled off. Can be implemented. In this case, the adhesive force of the adhesive member needs to have good adhesion to the resist pattern and to be inferior to the adhesion between the conductive substrate 21 and the resist patterns 22A and 22B. Specifically, when a tape-like adhesive member is used, the peeling force with respect to the resist pattern is preferably about 150 to 400 g / cm (peeling speed 100 mm / second, peeling angle 90 to 115 °), and when an adhesive roller is used, The peeling force for the resist pattern is preferably about 300 to 800 g / cm (peeling speed 60 to 90 mm / second, peeling angle 15 to 30 °). As the adhesive member, for example, cellophane tape manufactured by Nichiban Co., Ltd., acrylic cool-off heat-sensitive adhesive manufactured by Nita Co., Ltd., or the like can be used. In particular, the latter can be reused 10 times or more by utilizing the property that the adhesive strength increases at 30 ° C. or higher and there is almost no adhesive strength at room temperature.
[0027]
Further, the removal of the overhang portions 22a and 22b of the resist pattern can also be performed by a blast method. In this case, the particle size of the particles to be used is about 50 to 70 μm, and can be performed with a spraying pressure of about 2 kg. Both the particle size and the pressure need to be set appropriately depending on the resist material to be used. The resist pattern preferably has a thickness of 5 μm or more so that the required pattern portion is not destroyed by the blasting process. Furthermore, it is possible to remove the overhang portions 22a and 22b of the resist pattern using ultrasonic waves.
[0028]
Next, the exposed portions of the conductive substrate 21 are plated using the remaining resist patterns 22A and 22B as a mask (FIG. 7D plating step). In this plating process, the plating contactability is improved at the undercut portion of the conductive substrate 21 from which the overhang portions 22a and 22b of the resist pattern are removed as described above, and the plating substrate is improved with respect to the conductive substrate 21. Plating also grows in the direction (arrow a direction and arrow b direction in FIG. 7D). Thereby, the plating thin film 5 is formed on the side surface portions of the outer frame member 2, the terminal portion 3 and the connection lead 4, and the side surface portions of the die pad 7 and the connection lead 9 (not shown), and the recess 8 of the die pad 7. A plated thin film 5 is formed therein, and the plated thin film 5 is provided with a protruding portion 5 a so as to protrude from the surface of the conductive substrate 21.
[0029]
Next, the resist patterns 22A and 22B are peeled and removed, whereby the terminal portion 3 and the die pad 7 are integrally connected to the outer frame member 2 by the connection lead 4 and the connection lead 9 (not shown), respectively. Is obtained (FIG. 7E). A plating member 6 for terminal connection is formed at a predetermined position of the terminal portion 3 of the circuit member, and the circuit member 1 of the present invention shown in FIGS. 1 to 6 is obtained (FIG. 7F).
[0030]
In addition, in order to improve the adhesiveness with the resin sealing member, the plating thin film 5 formed in the plating process may be subjected to a chemical bond strengthening process or a roughening process (physical bond strengthening process). Examples of the surface roughening treatment include formation of a plating layer such as a Zn—Cr alloy (A2 process of Aurin, USA), various chromate treatments for nickel plating, etc., and the surface roughness Ra of the plated thin film 5 is set to about 30 nm or more. It is preferable to set. By performing such a surface roughening treatment, the adhesion of the plating thin film 5 to the sealing resin is further improved.
[0031]
Next, a method for manufacturing a resin-encapsulated semiconductor device using the circuit member 1 of the present invention will be described with reference to FIG.
[0032]
In FIG. 8, first, the circuit member 1 manufactured by the above-described manufacturing method of the present invention is used, and the opposite side of the circuit formation surface of the semiconductor element 52 is bonded to the surface 7A side of the die pad 7 of this circuit member 1 with electrically insulating double-sided bonding. The semiconductor element 52 is mounted by being fixed via the tape 55 (FIG. 8A).
[0033]
Next, the terminal 52a of the mounted semiconductor element 52 and the plating member 6 of the internal terminal 3a of the circuit member are electrically connected by the bonding wire 54 (FIG. 8B).
[0034]
Next, the terminal portion 3, the die pad 7, the semiconductor element 52, and the bonding wire 54 are sealed with a sealing resin 56 (FIG. 8C). Next, each connection lead 4 and connection lead 9 of the circuit member 1 is cut, the outer frame member 2 is removed, the external terminal 3b protruding from the sealing resin 56 is processed into a predetermined shape, and the resin-encapsulated type A semiconductor device 51 can be obtained (FIG. 8D).
[0035]
【The invention's effect】
As described in detail above, according to the present invention, the terminal portion and the die pad are formed by three-dimensionally biting into the sealing resin the protrusions of the plating thin film located in the terminal portion and the side surface portion of the die pad and the concave portion of the die pad. Is securely fixed, so that the terminal portion or die pad and the sealing resin are prevented from being peeled off, and the protrusions described above provide an intrusion path for moisture that has entered the interface between the terminal portion and the sealing resin from the outside. This makes it possible to provide a resin-encapsulated semiconductor device that is cut off and prevents so-called package cracks and has excellent reliability. Such a circuit member can be obtained by removing the overhang portion of the resist pattern at the projecting portion. Further, it can be easily produced by the production method of the present invention in which the plating contact property is enhanced. Furthermore, since the plating thin film is disposed on the side surface portion of the circuit member material such as the terminal portion where copper migration is likely to occur, the effect of preventing migration is also achieved.
[Brief description of the drawings]
FIG. 1 is a plan view showing an embodiment of a circuit member of the present invention.
2 is a longitudinal sectional view taken along line AA of the circuit member shown in FIG. 1. FIG.
3 is a partially enlarged perspective view of a terminal portion of the circuit member shown in FIG. 1. FIG.
4 is a longitudinal sectional view taken along line BB of the terminal portion shown in FIG.
FIG. 5 is a partially enlarged perspective view of the back side of the die pad of the circuit member shown in FIG. 1;
6 is a longitudinal sectional view taken along line CC of the die pad shown in FIG.
FIG. 7 is a process diagram showing an embodiment of a method for producing a circuit member of the present invention.
FIG. 8 is a process diagram showing an example of a method for manufacturing a resin-encapsulated semiconductor device using the circuit member of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Circuit member 2 ... Outer frame member 3 ... Terminal part 3a ... Internal terminal 3b ... External terminal 4, 9 ... Connection lead 5 ... Plating thin film 5a ... Projection part 6 ... Plating member 7 ... Die pad 8 ... Recess 21 ... Conductive substrate 22A, 22B ... resist patterns 22a, 22b ... resist pattern overhang 51 ... resin-sealed semiconductor device 52 ... semiconductor element 52a ... terminal 54 ... wire 56 ... sealing resin

Claims (4)

外枠部材と、該外枠部材から各々接続リードを介して相互に独立して配設された複数の端子部と、前記外枠部材から接続リードを介して配設されたダイパッドとを備える回路部材であって、前記端子部は少なくとも側面部にめっき薄膜を有し、前記ダイパッドは少なくとも一方の面に凹部を有するとともに該凹部と側面部とにめっき薄膜を有し、前記めっき薄膜は回路部材の表面に突出する突起部を有することを特徴とする樹脂封止型半導体装置用の回路部材。 Ru comprising an outer frame member, and a plurality of terminal portions arranged independently of one another via the respective connecting leads from the external frame member, and a die pad disposed over the connecting leads from the outer frame member A circuit member , wherein the terminal portion has a plating thin film on at least a side surface portion, the die pad has a concave portion on at least one surface and has a plating thin film on the concave portion and the side surface portion, and the plating thin film is a circuit A circuit member for a resin-encapsulated semiconductor device, comprising a protruding portion protruding on a surface of the member. 外枠部材と、該外枠部材から各々接続リードを介して相互に独立して配設された複数の端子部と、前記外枠部材から接続リードを介して配設されたダイパッドとを備えた回路部材の製造方法において、
導電性基板の両面に所定の形状でレジストパターンを形成し、該レジストパターンを耐腐蝕膜として前記導電性基板をエッチングして、外枠部材と、接続リードを介して相互に独立するように前記外枠部材に連結された複数の端子部と、接続リードを介して前記外枠部材に連結され少なくとも一方の面に凹部を有するダイパッドを形成するエッチング工程と、
エッチングされた部位に突出している前記レジストパターンのオーバーハング部を除去するレジスト部分除去工程と、
前記レジストパターンをマスクとして導電性基板の露出部にめっきを行って、導電性基板の表面から突出する突起部を有するめっき薄膜を外枠部材と端子部と接続リードの側面部、ダイパッドと接続リードの側面部、および、ダイパッドの凹部内に設けるめっき工程と、
レジストパターンを除去するレジスト除去工程と、を有することを特徴とする回路部材の製造方法。 An outer frame member, a plurality of terminal portions disposed independently from each other via connection leads from the outer frame member, and a die pad disposed from the outer frame member via connection leads. In the method for manufacturing a circuit member,
A resist pattern having a predetermined shape is formed on both surfaces of the conductive substrate, and the conductive substrate is etched using the resist pattern as a corrosion-resistant film so that the outer frame member and the connection lead are independent of each other. An etching step of forming a plurality of terminal portions connected to the outer frame member and a die pad connected to the outer frame member via a connection lead and having a recess on at least one surface;
A resist portion removing step for removing an overhang portion of the resist pattern protruding to the etched portion;
The exposed portion of the conductive substrate is plated using the resist pattern as a mask, and the plating thin film having the protruding portion protruding from the surface of the conductive substrate is formed on the outer frame member, the terminal portion, the side surface portion of the connection lead, the die pad, and the connection lead. And a plating step provided in the concave portion of the die pad ,
And a resist removing step for removing the resist pattern. 前記レジスト除去工程の後に、前記端子部の少なくとも一部に半導体素子との接続用のめっき部材を形成するめっき工程を有することを特徴とする請求項２に記載の回路部材の製造方法。  The method for manufacturing a circuit member according to claim 2, further comprising a plating step of forming a plating member for connection to a semiconductor element on at least a part of the terminal portion after the resist removing step. 前記レジスト部分除去工程は、粘着部材を使用する方法、ウエットブラストまたはドライブラストを使用した方法、超音波を使用した方法のいずれかにより行われることを特徴とする請求項２または請求項３に記載の回路部材の製造方法。  The resist part removing step is performed by any one of a method using an adhesive member, a method using wet blast or drive last, and a method using ultrasonic waves. The manufacturing method of the circuit member of.
JP32131498A 1998-10-26 1998-10-26 Circuit member for resin-encapsulated semiconductor device and manufacturing method thereof Expired - Fee Related JP4237851B2 (en)

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