JP2000133763A - Circuit member for resin-sealing semiconductor device and manufacture thereof - Google Patents

Circuit member for resin-sealing semiconductor device and manufacture thereof

Info

Publication number
JP2000133763A
JP2000133763A JP10321313A JP32131398A JP2000133763A JP 2000133763 A JP2000133763 A JP 2000133763A JP 10321313 A JP10321313 A JP 10321313A JP 32131398 A JP32131398 A JP 32131398A JP 2000133763 A JP2000133763 A JP 2000133763A
Authority
JP
Japan
Prior art keywords
metal layer
die pad
circuit member
outer frame
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10321313A
Other languages
Japanese (ja)
Inventor
Hideo Hotta
日出男 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP10321313A priority Critical patent/JP2000133763A/en
Publication of JP2000133763A publication Critical patent/JP2000133763A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a resin-sealing semiconductor device superior in tight- fitting characteristic to a sealing-resin, durability, and reliability. SOLUTION: For a circuit member 1, a metal layer 5 is formed on at least one surface of a conductive substrate using a material with lower etching workability than the conducting substrate in a metal layer formation process, a resist pattern is formed into a specified form on both surfaces of the conductive substrate where the metal layer 5 is formed in an etching process, so that the metal layer 5 and the conductive substrate are etched with the resist pattern as an anti-corrosion film, and then the resist pattern is removed in a resist- removing process to provide an outer frame member 2, a plurality of terminal parts 3 provided independently from the outer frame member 2 through each connection lead 4, and a die pad 7 provided from the outer lead member 2 through the connection lead 4. Here, the terminal part 3 comprises the metal layer 5 protruding to a side surface part on at least one surface, the die pad 7 comprises a recessed part 8 on at least one surface, while it comprises the metal layer 5 protruding at least to an opening part 80 of the recessed part 4 and the die pad side surface pad.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体素子を搭載し
た樹脂封止型の半導体装置に用いる回路部材と、その製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit member used for a resin-sealed semiconductor device having a semiconductor element mounted thereon, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】近年、半導体装置は、高集積化や小型化
技術の進歩、電気機器の高性能化と小型化の傾向から、
ＬＳＩのＡＳＩＣに代表されるように、ますます高集積
化、高機能化が進んできている。このような半導体装置
の高集積化、高機能化において、外部端子（ピン）の総
和の増加を来すとともに、更なる多端子（ピン）化が要
請されている。2. Description of the Related Art In recent years, due to advances in high integration and miniaturization technologies and the trend toward higher performance and miniaturization of electrical equipment, semiconductor devices have
As represented by ASICs of LSIs, higher integration and higher functions are being developed. In such a high integration and high function of a semiconductor device, the total number of external terminals (pins) is increased, and further multi-terminals (pins) are required.

【０００３】上記のような多端子（ピン）化の要請に応
えるものとして、高精細なリードフレーム等、および、
ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）、ＣＳＰ
（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）に代表される
様々な樹脂封止型の半導体装置が普及してきた。[0003] In order to meet the demand for multi-terminals (pins) as described above, high-definition lead frames and the like, and
BGA (Ball Grid Array), CSP
Various resin-encapsulated semiconductor devices represented by (Chip Size Package) have become widespread.

【０００４】[0004]

【発明が解決しようとする課題】しかし、従来の樹脂封
止型半導体装置では、端子部やダイパッドと封止樹脂と
の密着性が問題となっていた。すなわち、端子部やダイ
パッドと封止樹脂との密着性が悪い場合、半導体装置の
製造途中あるいは使用中に剥離を生じ、この剥離が原因
で封止樹脂のクラックが発生し、これにより半導体装置
の信頼性が損なわれ、耐久性が保てないという重大な欠
陥を生じることある。However, in the conventional resin-encapsulated semiconductor device, the adhesion between the terminal portion or the die pad and the encapsulating resin has been a problem. That is, when the adhesion between the terminal portion or the die pad and the sealing resin is poor, peeling occurs during the manufacture or use of the semiconductor device, and the peeling causes cracks in the sealing resin, thereby causing the semiconductor device to fail. The reliability may be impaired and serious defects may occur such that durability cannot be maintained.

【０００５】このため、剥離を生じやすいダイパッドに
微小凹部を形成するディンプル加工やスルーホール加工
を施すこと、あるいは、ダイパッドを半導体素子に比較
して小さくする、等の対応がなされている。しかしなが
ら、上記のディンプル加工は、ダイパッドと封止樹脂と
の密着性向上の効果が不十分であり、また、スルーホー
ル加工やダイパッドの小面積化は、半導体素子の搭載に
高い技術が必要になるという問題がある。[0005] For this reason, measures such as dimple processing or through-hole processing for forming minute concave portions on a die pad which is liable to peel off, or reduction in the size of the die pad as compared with a semiconductor element have been taken. However, the above-mentioned dimple processing has an insufficient effect of improving the adhesion between the die pad and the sealing resin, and the through-hole processing and the reduction of the area of the die pad require a high technology for mounting a semiconductor element. There is a problem.

【０００６】また、封止樹脂の面からの対応もなされ、
端子部やダイパッドを構成する金属材料への接着性を向
上させることが行われているが、金属材料への高い接着
性をもつ封止樹脂は、製造時に使用する金型にも接着す
るため、半導体装置の量産性に支障を来すという問題が
あり、また、このような封止樹脂の価格が高いという問
題もある。[0006] In addition, measures are taken from the aspect of the sealing resin.
While improving the adhesiveness to metal materials that make up the terminal section and die pad has been performed, the sealing resin with high adhesiveness to metal materials also adheres to the mold used during manufacturing, There is a problem that the mass productivity of the semiconductor device is hindered, and there is also a problem that the price of such a sealing resin is high.

【０００７】本発明は、上記のような事情に鑑みてなさ
れたものであり、封止樹脂との密着性に優れ、耐久性、
信頼性が高い樹脂封止型半導体装置の製造を可能とする
回路部材と、この回路部材の製造方法を提供することを
目的とする。The present invention has been made in view of the above circumstances, and has excellent adhesion to a sealing resin, durability,
It is an object of the present invention to provide a circuit member capable of manufacturing a highly reliable resin-encapsulated semiconductor device and a method for manufacturing the circuit member.

【０００８】[0008]

【課題を解決するための手段】このような目的を達成す
るために、本発明の樹脂封止型半導体装置用の回路部材
は、外枠部材と、該外枠部材から各々接続リードを介し
て相互に独立して配設された複数の端子部と、前記外枠
部材から接続リードを介して配設されたダイパッドとを
備え、前記端子部は少なくとも一方の面に側面部へ突出
するような金属層を有し、前記ダイパッドは少なくとも
一方の面に凹部を有するとともに、少なくとも該凹部の
開口部へ突出するような金属層を有するような構成とし
た。In order to achieve the above object, a circuit member for a resin-encapsulated semiconductor device according to the present invention comprises an outer frame member and a connection lead from the outer frame member via respective connection leads. A plurality of terminal portions provided independently of each other, and a die pad provided via connection leads from the outer frame member, wherein the terminal portions protrude at least on one surface to a side surface portion. The die pad has a configuration in which the die pad has a concave portion on at least one surface and has a metal layer protruding at least into the opening of the concave portion.

【０００９】また、本発明の樹脂封止型半導体装置用の
回路部材は、前記金属層がＮｉ、Ｓｎ、Ａｇ、Ｐｄ、Ａ
ｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のいずれかからな
る単層、あるいは、２種以上の組み合わせの多層である
ような構成とした。Further, in the circuit member for a resin-encapsulated semiconductor device according to the present invention, the metal layer may be made of Ni, Sn, Ag, Pd, A
u, Pt, Rh, Ru, and a single layer of any of the alloys thereof, or a multilayer of a combination of two or more.

【００１０】また、本発明の樹脂封止型半導体装置用の
回路部材は、前記端子部の側面部と、前記ダイパッドの
凹部内表面と、前記金属層の少なくとも側端面とに、め
っき層を有するような構成とした。The circuit member for a resin-encapsulated semiconductor device of the present invention has a plating layer on a side surface of the terminal portion, an inner surface of a concave portion of the die pad, and at least a side end surface of the metal layer. Such a configuration was adopted.

【００１１】さらに、本発明の樹脂封止型半導体装置用
の回路部材は、前記めっき層がＣｕ、Ｎｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層であるような構成とした。Further, in the circuit member for a resin-encapsulated semiconductor device according to the present invention, the plating layer may be formed of Cu, Ni, Sn, A
g, Pd, Au, Pt, Rh, Ru, and a single layer composed of any of the alloys thereof, or a multilayer composed of a combination of two or more types.

【００１２】本発明の回路部材の製造方法は、導電性基
板の少なくとも一方の面に、該導電性基板よりもエッチ
ング加工性の低い材料で金属層を形成する金属層形成工
程と、金属層が形成された導電性基板の両面に所定の形
状でレジストパターンを形成し、該レジストパターンを
耐腐蝕膜として前記金属層および導電性基板をエッチン
グして、外枠部材と、接続リードを介して相互に独立す
るように前記外枠部材に連結された複数の端子部と、接
続リードを介して前記外枠部材に連結され少なくとも一
方の面に凹部を有するダイパッドを形成するエッチング
工程と、レジストパターンを除去するレジスト除去工程
と、を有するような構成とした。The method for manufacturing a circuit member according to the present invention includes a metal layer forming step of forming a metal layer on at least one surface of the conductive substrate with a material having lower etching workability than the conductive substrate; A resist pattern is formed in a predetermined shape on both surfaces of the formed conductive substrate, and the metal layer and the conductive substrate are etched by using the resist pattern as a corrosion-resistant film. A plurality of terminal portions connected to the outer frame member so as to be independent of each other, an etching step of forming a die pad having a concave portion on at least one surface connected to the outer frame member via connection leads, and a resist pattern. And a resist removing step of removing.

【００１３】また、本発明の回路部材の製造方法は、前
記エッチング工程と前記レジスト除去工程との間に、露
出している前記端子部の側面部と、前記ダイパッドの側
面部および凹部内表面と、前記金属層の側端面とにめっ
き層を形成するめっき工程を有するような構成とした。Further, in the method of manufacturing a circuit member according to the present invention, the side face of the terminal part, the side face of the die pad, and the inner surface of the concave portion may be formed between the etching step and the resist removing step. And a plating step of forming a plating layer on a side end face of the metal layer.

【００１４】また、本発明の回路部材の製造方法は、前
記レジスト除去工程の後に、露出している前記端子部の
側面部と、前記ダイパッドの側面部および凹部内表面
と、前記金属層とに、めっき層を形成するめっき工程を
有するような構成とした。Further, in the method of manufacturing a circuit member according to the present invention, preferably, after the resist removing step, the exposed side surface of the terminal portion, the side surface of the die pad and the inner surface of the recess, and the metal layer are formed. And a plating step of forming a plating layer.

【００１５】さらに、本発明の回路部材の製造方法は、
前記金属層形成工程において、金属層をＮｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層として形成するような構成とした。Further, the method for manufacturing a circuit member according to the present invention comprises:
In the metal layer forming step, the metal layer is formed of Ni, Sn, A
g, Pd, Au, Pt, Rh, Ru, and alloys thereof, or a single layer thereof, or a combination of two or more layers.

【００１６】また、本発明の回路部材の製造方法は、前
記めっき工程において、めっき層をＣｕ、Ｎｉ、Ｓｎ、
Ａｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金の
いずれかからなる単層、あるいは、２種以上の組み合わ
せの多層として形成するような構成とした。In the method of manufacturing a circuit member according to the present invention, in the plating step, the plating layer may be formed of Cu, Ni, Sn,
The structure was such that it was formed as a single layer made of any of Ag, Pd, Au, Pt, Rh, Ru and alloys thereof, or as a multilayer of a combination of two or more kinds.

【００１７】このような本発明では、端子部やダイパッ
ドの側面部、および、ダイパッドの凹部の開口部へ突出
する金属層の突出部が、封止樹脂に端子部、ダイパッド
を確実に固定する作用をなす。According to the present invention, the terminal portion and the side surface of the die pad, and the protrusion of the metal layer protruding into the opening of the concave portion of the die pad function to securely fix the terminal portion and the die pad to the sealing resin. Make

【００１８】[0018]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。回路部材の第１の実施形態 図１は本発明の回路部材の一実施形態を示す平面図、図
２は図１に示される回路部材のＡ−Ａ線における縦断面
図である。図１および図２において、本発明の回路部材
１は、外枠部材２と、この外枠部材２から接続リード４
を介して相互に独立して配設された複数の端子部３と、
外枠部材２から接続リード９を介して配設されたダイパ
ッド７とを備えている。そして、回路部材１は、端子部
３の裏面３Ｂとダイパッド７の裏面７Ｂを含む裏面側に
金属層５を備えている。Embodiments of the present invention will be described below with reference to the drawings. Plan view showing an embodiment of a circuit member of the first embodiment Figure 1 a circuit member according to the present invention, FIG. 2 is a longitudinal sectional view along the line A-A of the circuit member shown in FIG. 1 and 2, a circuit member 1 according to the present invention includes an outer frame member 2 and a connection lead 4 from the outer frame member 2.
A plurality of terminal parts 3 arranged independently of each other via
A die pad 7 provided from the outer frame member 2 via a connection lead 9. The circuit member 1 includes the metal layer 5 on the back surface side including the back surface 3B of the terminal portion 3 and the back surface 7B of the die pad 7.

【００１９】外枠部材２は、外形形状および内側開口形
状が矩形であり、各接続リード４は外枠部材２の内側開
口の各辺から同一平面内に突設されている。The outer frame member 2 has a rectangular outer shape and an inner opening shape, and each connection lead 4 projects from each side of the inner opening of the outer frame member 2 in the same plane.

【００２０】端子部３は、接続リード４の先端に設けら
れ、先端側に半導体素子との接続部位である内部端子３
ａを、接続リード４寄りに外部端子３ｂを有している。
外枠部材２と端子部３と接続リード４の裏面には金属層
５が設けられている。図３は、このような端子部３の部
分斜視図である。図３に示されるように、端子部３の裏
面３Ｂには金属層５が配設されており、この金属層５
は、端子部３の側面部へ突出する突出部５ａを有してお
り、この突出部５ａが、樹脂封止型半導体装置の製造に
おいて、封止樹脂に端子部３を確実に固定する作用をな
す。尚、図示例では端子部３の内部端子３ａの表面には
半導体素子の端子との接続用のめっき部材６が設けられ
ている。The terminal portion 3 is provided at the tip of the connection lead 4 and has an internal terminal 3 which is a connection portion with the semiconductor element on the tip side.
1 has an external terminal 3b near the connection lead 4.
A metal layer 5 is provided on the back surfaces of the outer frame member 2, the terminal portions 3, and the connection leads 4. FIG. 3 is a partial perspective view of such a terminal portion 3. As shown in FIG. 3, a metal layer 5 is provided on the back surface 3B of the terminal portion 3.
Has a protruding portion 5a protruding to the side surface portion of the terminal portion 3, and this protruding portion 5a has an effect of securely fixing the terminal portion 3 to the sealing resin in the production of the resin-sealed semiconductor device. Eggplant In the illustrated example, a plating member 6 for connection with the terminal of the semiconductor element is provided on the surface of the internal terminal 3a of the terminal portion 3.

【００２１】ダイパッド７は、外枠部材２の内側開口の
各隅部から延設された４本の接続リード９に支持され、
裏面７Ｂ側には複数の凹部８が形成され、さらに、ダイ
パッド７の裏面７Ｂと接続リード９の裏面には金属層５
が設けられている。図４は、このようなダイパッド７の
裏面７Ｂ側の斜視図である。図２および図４において、
ダイパッド７の裏面７Ｂ側に設けられた凹部８は略半球
形状の凹部（ディンプル）であり、上記の金属層５は、
ダイパッド７の側面部へ突出する突出部５ａと、凹部８
の開口部８ａへ突出する突出部５ａを有している。この
ような突出部５ａが、樹脂封止型半導体装置の製造にお
いて、封止樹脂にダイパッド７を確実に固定する作用を
なす。凹部８の形状は略半球形状に限定されるものでは
なく、例えば、溝形状のもの等いずれであってもよい。
凹部８の形状、寸法、個数等は適宜設定することができ
るが、開口部８ａに突出している突出部５ａの開口幅
は、封止樹脂の凹部８内への侵入の容易さを考慮して５
０〜４００μｍの範囲内であることが好ましい。The die pad 7 is supported by four connection leads 9 extending from each corner of the inner opening of the outer frame member 2.
A plurality of recesses 8 are formed on the back surface 7B side, and a metal layer 5 is formed on the back surface 7B of the die pad 7 and the back surface of the connection lead 9.
Is provided. FIG. 4 is a perspective view of such a die pad 7 on the back surface 7B side. 2 and 4,
The concave portion 8 provided on the back surface 7B side of the die pad 7 is a substantially hemispherical concave portion (dimple).
A protruding portion 5a protruding to the side surface of the die pad 7;
Has a protruding portion 5a protruding into the opening 8a. Such a protruding portion 5a functions to securely fix the die pad 7 to the sealing resin in the production of the resin-sealed semiconductor device. The shape of the concave portion 8 is not limited to a substantially hemispherical shape, and may be, for example, a groove shape or the like.
The shape, size, number, and the like of the concave portions 8 can be set as appropriate. However, the opening width of the protruding portion 5a protruding from the opening portion 8a is determined in consideration of the ease with which the sealing resin can enter the concave portion 8. 5
It is preferable that it is in the range of 0 to 400 μm.

【００２２】金属層５は、Ｎｉ、Ｓｎ、Ａｇ、Ｐｄ、Ａ
ｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のいずれかからな
る単層、あるいは、２種以上の組み合わせの多層であ
り、厚みは２〜２０μｍ程度である。この金属層５の突
出部５ａの突出量（図２のＷ１、Ｗ２）は、１０〜１０
０μｍ程度の範囲内にあることが好ましい。また、接続
用のめっき部材６は、金、パラジウム、銀等のいずれか
からなる単層めっきであり、厚みは２〜５μｍ程度であ
る。The metal layer 5 is made of Ni, Sn, Ag, Pd, A
It is a single layer made of any one of u, Pt, Rh, Ru and an alloy thereof, or a multilayer of a combination of two or more kinds, and has a thickness of about 2 to 20 μm. The protrusion amount of the protrusion 5a of the metal layer 5 (W1, W2 in FIG. 2) is 10 to 10
It is preferable that it is within a range of about 0 μm. The connection plating member 6 is a single-layer plating made of any of gold, palladium, silver, and the like, and has a thickness of about 2 to 5 μm.

【００２３】このような回路部材１の材質は、４２合金
（Ｎｉ４１％のＦｅ合金）、銅、銅合金等とすることが
できる。The material of the circuit member 1 can be 42 alloy (Fe alloy of 41% Ni), copper, copper alloy or the like.

【００２４】また、本発明の回路部材１は、ダイパッド
７の表面７Ａ（半導体素子搭載面）側に電気絶縁性の両
面接着テープを設けたものであってもよい。両面接着テ
ープは、電気絶縁性のベースフィルムの両面に接着剤層
を備えたもの、例えば、ユーピレックス（宇部興産
（株）製の電気絶縁性のベースフィルム）の両面にＲＸ
Ｆ（（株）巴川製紙所製の接着剤）層を備えたＵＸ１Ｗ
（（株）巴川製紙所製）のような両面接着テープを使用
することができる。回路部材の第２の実施形態 図５は本発明の回路部材の他の実施形態を示す図２相当
の断面図である。図５において、本発明の回路部材１１
は、表面にも金属層を備えている点、および、端子部１
３の内部端子１３ａが薄肉部である点を除いて、上述の
回路部材１と同様である。すなわち、外枠部材１２と、
この外枠部材１２から接続リード１４を介して相互に独
立して配設された複数の端子部１３と、外枠部材１２か
ら接続リード（図示せず）を介して配設されたダイパッ
ド１７とを備えている。そして、回路部材１１は、端子
部１３の裏面１３Ｂとダイパッド１７の裏面１７Ｂを含
む裏面側に金属層１５を備え、さらに、表面側にも金属
層１５を備えている。The circuit member 1 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface 7A (semiconductor element mounting surface) side of the die pad 7. The double-sided adhesive tape is provided with an adhesive layer on both sides of an electrically insulating base film, for example, RXIX on both sides of Upilex (an electrically insulating base film manufactured by Ube Industries, Ltd.).
UX1W with F (adhesive manufactured by Tomoegawa Paper Mill) layer
Double-sided adhesive tape such as (manufactured by Hamakawa Paper Mill) can be used. Second Embodiment of Circuit Member FIG. 5 is a sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention. In FIG. 5, the circuit member 11 of the present invention is shown.
Has a metal layer on the surface and
3 is the same as the above-described circuit member 1 except that the internal terminal 13a is a thin portion. That is, the outer frame member 12 and
A plurality of terminal portions 13 are provided independently from the outer frame member 12 via connection leads 14, and a die pad 17 is provided from the outer frame member 12 via connection leads (not shown). It has. The circuit member 11 includes the metal layer 15 on the back surface including the back surface 13B of the terminal portion 13 and the back surface 17B of the die pad 17, and further includes the metal layer 15 on the front surface.

【００２５】外枠部材１２は、上記の外枠部材２と同様
であり、外形形状および内側開口形状が矩形であり、各
接続リード１４は外枠部材１２の内側開口の各辺から同
一平面内に突設されている。The outer frame member 12 is the same as the above-described outer frame member 2 and has a rectangular outer shape and an inner opening shape, and each connection lead 14 is within the same plane from each side of the inner opening of the outer frame member 12. It is projected.

【００２６】端子部１３は、上記の端子部３と同様に接
続リード１４の先端に設けられ、先端側に薄肉部であり
半導体素子との接続部位である内部端子１３ａを、接続
リード寄りに外部端子１３ｂを有している。外枠部材１
２と端子部１３と接続リード１４の表面および裏面には
金属層１５が設けられている。ただし、薄肉部である内
部端子１３ａの表面には金属層１５は設けられていな
い。このような金属層１５は、端子部１３の側面部へ突
出する突出部１５ａを有しており、この突出部１５ａ
が、樹脂封止型半導体装置の製造において、封止樹脂に
端子部１３を確実に固定する作用をなす。尚、図示例で
は端子部１３の内部端子１３ａの薄肉部の表面には半導
体素子の端子との接続用のめっき部材１６が設けられて
いる。The terminal portion 13 is provided at the distal end of the connection lead 14 in the same manner as the terminal portion 3 described above. It has a terminal 13b. Outer frame member 1
A metal layer 15 is provided on the front and back surfaces of the terminal 2, the terminal portion 13, and the connection lead 14. However, the metal layer 15 is not provided on the surface of the thin internal terminal 13a. Such a metal layer 15 has a protruding portion 15 a protruding to the side surface of the terminal portion 13.
However, in the production of the resin-encapsulated semiconductor device, it has an effect of securely fixing the terminal portion 13 to the encapsulation resin. In the illustrated example, a plating member 16 for connection to the terminal of the semiconductor element is provided on the surface of the thin portion of the internal terminal 13a of the terminal portion 13.

【００２７】ダイパッド１７は、上述のダイパッド７と
同様に、外枠部材１２の内側開口の各隅部から延設され
た４本の接続リード（図示せず）に支持され、裏面１７
Ｂ側には複数の凹部１８が形成され、さらに、ダイパッ
ド１７および接続リードの表面および裏面には金属層１
５が設けられている。ダイパッド１７の裏面１７Ｂ側に
設けられた凹部１８は略半球形状の凹部（ディンプル）
であり、上記の金属層１５は、ダイパッド１７の側面部
へ突出する突出部１５ａと、凹部１８の開口部１８ａへ
突出する突出部１５ａを有している。このような突出部
１５ａが、樹脂封止型半導体装置の製造において、封止
樹脂にダイパッド１７を確実に固定する作用をなす。The die pad 17 is supported by four connection leads (not shown) extending from each corner of the inner opening of the outer frame member 12 similarly to the die pad 7 described above.
A plurality of recesses 18 are formed on the B side, and a metal layer 1 is formed on the front and back surfaces of the die pad 17 and the connection leads.
5 are provided. The concave portion 18 provided on the back surface 17B side of the die pad 17 has a substantially hemispherical concave portion (dimple).
The metal layer 15 has a projection 15a projecting to the side surface of the die pad 17 and a projection 15a projecting to the opening 18a of the concave portion 18. Such a protruding portion 15a functions to securely fix the die pad 17 to the sealing resin in manufacturing the resin-sealed semiconductor device.

【００２８】回路部材１１の材質、金属層１５の材質や
厚み、ダイパッド１７に設ける凹部１８の形状、寸法、
個数、この開口部１８ａに突出している突出部１５ａの
開口幅等は、上述の回路部材１の該当する部位と同様と
することができ、ここでの説明は省略する。The material of the circuit member 11, the material and thickness of the metal layer 15, the shape and size of the concave portion 18 provided in the die pad 17,
The number, the opening width of the protruding portion 15a protruding from the opening 18a, and the like can be the same as the corresponding portions of the circuit member 1 described above, and description thereof is omitted here.

【００２９】また、本発明の回路部材１１は、ダイパッ
ド１７の表面１７Ａ（半導体素子搭載面）側に電気絶縁
性の両面接着テープを設けたものであってもよい。両面
接着テープは、上述のような両面接着テープを使用する
ことができる。回路部材の第３の実施形態 図６は本発明の回路部材の他の実施形態を示す図２相当
の部分拡大断面図である。図６において、本発明の回路
部材２１は、端子部、接続リード部、ダイパッド、接続
リードの各側面と、ダイパッドに設けられた凹部内と、
金属層の側端面とにめっき層を備えている点、および、
端子部２３の内部端子２３ａが薄肉部である点を除い
て、上述の回路部材１と同様である。すなわち、回路部
材２１は、外枠部材２２（図示せず）と、この外枠部材
２２から接続リード２４を介して相互に独立して配設さ
れた複数の端子部２３と、外枠部材２２から接続リード
２９（図示せず）を介して配設されたダイパッド２７と
を備えている。また、端子部２３の裏面２３Ｂとダイパ
ッド２７の裏面２７Ｂを含む裏面に金属層２５を備えて
いる。そして、端子部２３、接続リード部２４、ダイパ
ッド２７、接続リード２９の各側面と、ダイパッド２７
に設けられた凹部２８内と、金属層２５の側端面とに、
めっき層３０を備えている。The circuit member 11 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface 17A (semiconductor element mounting surface) side of the die pad 17. As the double-sided adhesive tape, the double-sided adhesive tape as described above can be used. Third Embodiment of Circuit Member FIG. 6 is a partially enlarged sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention. In FIG. 6, the circuit member 21 of the present invention includes a terminal portion, a connection lead portion, a die pad, each side surface of a connection lead, a recess provided in the die pad,
A point that a plating layer is provided on a side end face of the metal layer, and
It is the same as the above-described circuit member 1 except that the internal terminal 23a of the terminal portion 23 is a thin portion. That is, the circuit member 21 includes an outer frame member 22 (not shown), a plurality of terminal portions 23 that are independently provided from the outer frame member 22 via the connection leads 24, and an outer frame member 22. And a die pad 27 arranged via connection leads 29 (not shown). The metal layer 25 is provided on the back surface including the back surface 23B of the terminal portion 23 and the back surface 27B of the die pad 27. Then, each side surface of the terminal portion 23, the connection lead portion 24, the die pad 27, the connection lead 29, and the die pad 27
In the concave portion 28 provided on the side surface of the metal layer 25,
A plating layer 30 is provided.

【００３０】外枠部材２２は、上記の外枠部材２と同様
であり、外形形状および内側開口形状が矩形であり、各
接続リード２４は外枠部材２２の内側開口の各辺から同
一平面内に突設されている。The outer frame member 22 is the same as the outer frame member 2 described above, and has a rectangular outer shape and an inner opening shape, and each connection lead 24 is located on the same plane from each side of the inner opening of the outer frame member 22. It is projected.

【００３１】端子部２３は、上記の端子部３と同様に接
続リード２４の先端に設けられ、先端側に薄肉部であり
半導体素子との接続部位である内部端子２３ａを、接続
リード寄りに外部端子２３ｂを有している。外枠部材２
２と端子部２３と接続リード２４の裏面には金属層２５
が設けられている。このような金属層２５は、端子部２
３の側面部へ突出する突出部２５ａを有しており、この
突出部２５ａが、樹脂封止型半導体装置の製造におい
て、封止樹脂に端子部２３を確実に固定する作用をな
す。尚、図示例では端子部２３の内部端子２３ａの薄肉
部の表面には半導体素子の端子との接続用のめっき部材
２６が設けられている。The terminal portion 23 is provided at the distal end of the connection lead 24 in the same manner as the terminal portion 3 described above. It has a terminal 23b. Outer frame member 2
2, a metal layer 25 on the back surface of the terminal portion 23 and the connection lead 24.
Is provided. Such a metal layer 25 is formed on the terminal portion 2.
3 has a protruding portion 25a that protrudes to the side surface portion, and the protruding portion 25a functions to securely fix the terminal portion 23 to the sealing resin in the production of the resin-sealed semiconductor device. In the illustrated example, a plating member 26 for connection with the terminal of the semiconductor element is provided on the surface of the thin portion of the internal terminal 23a of the terminal portion 23.

【００３２】ダイパッド２７は、上述のダイパッド７と
同様に、外枠部材２２の内側開口の各隅部から延設され
た４本の接続リード２９（図示せず）に支持され、裏面
２７Ｂ側には複数の凹部２８が形成され、さらに、ダイ
パッド２７および接続リードの裏面には金属層２５が設
けられている。ダイパッド２７の裏面２７Ｂ側に設けら
れた凹部２８は略半球形状の凹部（ディンプル）であ
り、上記の金属層２５は、ダイパッド２７の側面部へ突
出する突出部２５ａと、凹部２８の開口部２８ａへ突出
する突出部２５ａを有している。このような突出部２５
ａが、樹脂封止型半導体装置の製造において、封止樹脂
にダイパッド２７を確実に固定する作用をなす。The die pad 27 is supported by four connection leads 29 (not shown) extending from each corner of the inner opening of the outer frame member 22, similarly to the above-mentioned die pad 7, and is provided on the back surface 27B side. A plurality of concave portions 28 are formed, and a metal layer 25 is provided on the back surface of the die pad 27 and the connection lead. The concave portion 28 provided on the back surface 27B side of the die pad 27 is a substantially hemispherical concave portion (dimple), and the metal layer 25 includes a protruding portion 25a protruding to the side surface of the die pad 27 and an opening 28a of the concave portion 28. It has a protruding portion 25a that protrudes toward Such a protrusion 25
“a” functions to reliably fix the die pad 27 to the sealing resin in the manufacture of the resin-sealed semiconductor device.

【００３３】めっき層３０は、上述のように、端子部２
３、接続リード２４、ダイパッド２７、接続リード２９
の各側面と、ダイパッド２７に設けられた凹部２８内
と、金属層２５の側端面（突出部２５ａ）との設けられ
ており、特に金属層２５の側端面（突出部２５ａ）で
は、めっき層３０の成長が進み大きな突出部がめっき層
３０によって形成されている。これにより、上記の突出
部２５ａによる封止樹脂と端子部２３やダイパッド２７
との密着性向上の効果が更に大きなものとなる。As described above, the plating layer 30 is formed on the terminal 2
3, connection lead 24, die pad 27, connection lead 29
Of the metal layer 25, the inside of the concave portion 28 provided in the die pad 27, and the side end surface (projection 25a) of the metal layer 25. The growth of 30 has progressed and a large protrusion is formed by the plating layer 30. As a result, the sealing resin formed by the protruding portions 25a and the terminal portions 23 and the die pads 27 are formed.
The effect of improving the adhesion to the substrate is further enhanced.

【００３４】めっき層３０は、Ｃｕ、Ｎｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層であり、金属層２５の側面（突出部２５ａ）にお
けるめっき層３０の厚みは１〜２０μｍ程度とすること
が好ましい。The plating layer 30 is made of Cu, Ni, Sn, A
g, a single layer of Pd, Au, Pt, Rh, Ru, or an alloy thereof, or a multilayer of a combination of two or more of them, and the thickness of the plating layer 30 on the side surface (projection 25 a) of the metal layer 25. Is preferably about 1 to 20 μm.

【００３５】尚、回路部材２１の材質、金属層２５の材
質や厚み、ダイパッド２７に設ける凹部２８の形状、寸
法、個数、この開口部２８ａに突出している突出部２５
ａ（めっき層３０）の開口幅等は、上述の回路部材１の
該当する部位と同様とすることができ、ここでの説明は
省略する。The material of the circuit member 21, the material and thickness of the metal layer 25, the shape, size, and number of the concave portions 28 provided in the die pad 27, the protruding portions 25 protruding from the openings 28a.
The opening width and the like of a (plating layer 30) can be the same as the corresponding portions of the circuit member 1 described above, and description thereof is omitted here.

【００３６】また、本発明の回路部材２１は、ダイパッ
ド２７の表面２７Ａ（半導体素子搭載面）側に電気絶縁
性の両面接着テープを設けたものであってもよい。両面
接着テープは、上述のような両面接着テープを使用する
ことができる。The circuit member 21 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface 27A (semiconductor element mounting surface) side of the die pad 27. As the double-sided adhesive tape, the double-sided adhesive tape as described above can be used.

【００３７】本実施形態においても、図５に示される実
施形態と同様に、回路部材の表面にも金属層を備えるも
のであってよい。回路部材の第４の実施形態 図７は本発明の回路部材の他の実施形態を示す図２相当
の部分拡大断面図である。図７において、本発明の回路
部材３１は、端子部、接続リード、ダイパッド、接続リ
ードの各側面と、ダイパッドに設けられた凹部内と、金
属層上とにめっき層を備えている点を除いて、上述の回
路部材１１と同様である。すなわち、回路部材３１は、
外枠部材３２（図示せず）と、この外枠部材３２から接
続リード３４を介して相互に独立して配設された複数の
端子部３３と、外枠部材３２から接続リード３９（図示
せず）を介して配設されたダイパッド３７とを備えてい
る。また、回路部材３１は、端子部３３の裏面３３Ｂと
ダイパッド３７の裏面３７Ｂを含む裏面側に金属層３５
を備え、かつ、表面側にも金属層３５を備えている。そ
して、端子部３３、接続リード３４、ダイパッド３７、
接続リード３９の各側面と、ダイパッド３７に設けられ
た凹部３８内と、金属層３５上とに、めっき層４０を備
えている。In this embodiment, as in the embodiment shown in FIG. 5, a metal layer may be provided also on the surface of the circuit member. Fourth Embodiment of Circuit Member FIG. 7 is a partially enlarged sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention. In FIG. 7, the circuit member 31 of the present invention is provided with a plating layer on each side surface of the terminal portion, the connection lead, the die pad, and the connection lead, the inside of the concave portion provided in the die pad, and the metal layer. Thus, it is the same as the circuit member 11 described above. That is, the circuit member 31
An outer frame member 32 (not shown), a plurality of terminal portions 33 arranged independently from each other via connection leads 34 from the outer frame member 32, and a connection lead 39 (not shown) And a die pad 37 disposed therebetween. The circuit member 31 includes a metal layer 35 on the back surface including the back surface 33B of the terminal portion 33 and the back surface 37B of the die pad 37.
And a metal layer 35 on the surface side. Then, the terminal portion 33, the connection lead 34, the die pad 37,
A plating layer 40 is provided on each side surface of the connection lead 39, inside the concave portion 38 provided in the die pad 37, and on the metal layer 35.

【００３８】外枠部材３２は、上記の外枠部材２と同様
であり、外形形状および内側開口形状が矩形であり、各
接続リード３４は外枠部材３２の内側開口の各辺から同
一平面内に突設されている。The outer frame member 32 is the same as the above-described outer frame member 2 and has a rectangular outer shape and an inner opening shape, and each connection lead 34 is within the same plane from each side of the inner opening of the outer frame member 32. It is projected.

【００３９】端子部３３は、上記の端子部３と同様に接
続リード３４の先端に設けられ、先端側に薄肉部であり
半導体素子との接続部位である内部端子３３ａを、接続
リード寄りに外部端子３３ｂを有している。外枠部材３
２と端子部３３と接続リード３４の表面および裏面には
金属層３５が設けられている。ただし、薄肉部である内
部端子３３ａの表面には金属層３５は設けられていな
い。このような金属層３５は、端子部３３の側面部へ突
出する突出部３５ａを有しており、この突出部３５ａ
が、樹脂封止型半導体装置の製造において、封止樹脂に
端子部３３を確実に固定する作用をなす。The terminal portion 33 is provided at the distal end of the connection lead 34 in the same manner as the terminal portion 3 described above. It has a terminal 33b. Outer frame member 3
A metal layer 35 is provided on the front and back surfaces of the terminal 2, the terminal portion 33, and the connection lead 34. However, the metal layer 35 is not provided on the surface of the thin internal terminal 33a. Such a metal layer 35 has a protruding portion 35a protruding to the side surface of the terminal portion 33.
However, in the manufacture of the resin-encapsulated semiconductor device, it has an effect of securely fixing the terminal portion 33 to the sealing resin.

【００４０】ダイパッド３７は、上述のダイパッド７と
同様に、外枠部材３２の内側開口の各隅部から延設され
た４本の接続リード３９（図示せず）に支持され、裏面
３７Ｂ側には複数の凹部３８が形成され、さらに、ダイ
パッド３７および接続リードの表面および裏面には金属
層３５が設けられている。ダイパッド３７の裏面３７Ｂ
側に設けられた凹部３８は略半球形状の凹部（ディンプ
ル）であり、上記の金属層３５は、ダイパッド３７の側
面部へ突出する突出部３５ａと、凹部３８の開口部３８
ａへ突出する突出部３５ａを有している。このような突
出部３５ａが、樹脂封止型半導体装置の製造において、
封止樹脂にダイパッド３７を確実に固定する作用をな
す。The die pad 37 is supported by four connection leads 39 (not shown) extending from each corner of the inner opening of the outer frame member 32, similarly to the above-mentioned die pad 7, and is provided on the back surface 37B side. A plurality of concave portions 38 are formed, and a metal layer 35 is provided on the front and back surfaces of the die pad 37 and the connection leads. Back surface 37B of die pad 37
The concave portion 38 provided on the side is a substantially hemispherical concave portion (dimple), and the metal layer 35 includes a protruding portion 35 a protruding to the side surface of the die pad 37 and an opening portion 38 of the concave portion 38.
a has a protruding portion 35a that protrudes to a. Such a protruding portion 35a is used for manufacturing a resin-encapsulated semiconductor device.
It functions to securely fix the die pad 37 to the sealing resin.

【００４１】めっき層４０は、上述のように、端子部３
３、接続リード３４、ダイパッド３７、接続リード３９
の各側面と、ダイパッド３７に設けられた凹部３８内
と、金属層３５上とに設けられているが、特に金属層３
５の側端面（突出部３５ａ）では、めっき層４０の成長
が進み大きな突出部がめっき層４０によって形成されて
いる。これにより、上記の突出部３５ａによる封止樹脂
と端子部３３やダイパッド３７との密着性向上の効果が
更に大きなものとなる。As described above, the plating layer 40 is formed on the terminal 3
3, connection lead 34, die pad 37, connection lead 39
, The inside of the recess 38 provided in the die pad 37, and on the metal layer 35.
On the side end surface 5 (projection 35 a), the growth of the plating layer 40 progresses and a large projection is formed by the plating layer 40. Thereby, the effect of improving the adhesion between the sealing resin and the terminal portion 33 or the die pad 37 by the above-mentioned protruding portion 35a is further increased.

【００４２】尚、めっき層４０の材質、厚みは、上述の
回路部材２１と同様とすることができる。また、回路部
材３１の材質、金属層３５の材質や厚み、ダイパッド３
７に設ける凹部３８の形状、寸法、個数、この開口部３
８ａに突出している突出部３５ａ（めっき層４０）の開
口幅等は、上述の回路部材１の該当する部位と同様とす
ることができ、ここでの説明は省略する。The material and thickness of the plating layer 40 can be the same as those of the circuit member 21 described above. Further, the material of the circuit member 31, the material and thickness of the metal layer 35, the die pad 3
7, the shape, size, and number of the concave portions 38,
The opening width and the like of the protruding portion 35a (plating layer 40) protruding from 8a can be the same as the corresponding portion of the circuit member 1 described above, and description thereof is omitted here.

【００４３】また、本発明の回路部材３１は、ダイパッ
ド３７の表面３７Ａ（半導体素子搭載面）側に電気絶縁
性の両面接着テープを設けたものであってもよい。両面
接着テープは、上述のような両面接着テープを使用する
ことができる。The circuit member 31 of the present invention may be provided with an electrically insulating double-sided adhesive tape on the surface 37A (semiconductor element mounting surface) side of the die pad 37. As the double-sided adhesive tape, the double-sided adhesive tape as described above can be used.

【００４４】尚、上述の回路部材１、１１、２１、３１
における端子数、端子配列等は例示であり、本発明の回
路部材がこれに限定されないことは勿論である。また、
上述の回路部材では、いずれもダイパッドの裏面側に凹
部が形成されているが、表面側に半導体素子搭載領域外
の余地がある場合、この部分に凹部を設けてもよい。 回路部材の製造方法の第１の実施形態 次に、本発明の回路部材の製造方法について説明する。The above-mentioned circuit members 1, 11, 21, 31
The terminal numbers, terminal arrangements, and the like in
Of course, the road member is not limited to this. Also,
In the above circuit members, all are concave on the back side of the die pad.
Part is formed, but outside the semiconductor element mounting area on the front side
If there is room, the concave portion may be provided in this portion. First Embodiment of Circuit Member Manufacturing Method Next, a method for manufacturing a circuit member according to the present invention will be described.

【００４５】図８は、図１乃至図４に示される本発明の
回路部材１を例とした本発明の回路部材の製造方法の一
実施形態を示す工程図である。各工程は、上記の図２に
対応する回路部材の縦断面図で示してある。FIG. 8 is a process diagram showing one embodiment of a method for manufacturing a circuit member of the present invention using the circuit member 1 of the present invention shown in FIGS. 1 to 4 as an example. Each step is shown in a longitudinal sectional view of the circuit member corresponding to FIG. 2 described above.

【００４６】図８において、まず、金属層形成工程とし
て、導電性基板５１の一方の面に金属層５を形成する
（図８（Ａ））。導電性基板５１としては、上述のよう
に４２合金（Ｎｉ４１％のＦｅ合金）、銅、銅合金等の
金属基板（厚み１００〜２５０μｍ）を使用することが
でき、この導電性基板５１は、両面を脱脂等を行い洗浄
処理を施したものを使用することが好ましい。金属層５
は、導電性基板５１よりもエッチング加工性の低い材料
を用いてめっき法、真空蒸着法、スパッタリング法等の
公知の成膜方法により形成することができる。例えば、
Ｃｕ、Ｎｉ、Ｓｎ、Ａｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒ
ｕおよびその合金のなかから、導電性基板５１のエッチ
ング加工性との差を考慮して適宜選択した１種の材料か
らなる単層、あるいは、２種以上の組み合わせの多層と
することができる。金属層５の厚みは導電性基板５１の
エッチング加工性との差を考慮して設定することがで
き、例えば、２〜２０μｍ程度の厚みとすることができ
る。In FIG. 8, first, as a metal layer forming step, a metal layer 5 is formed on one surface of a conductive substrate 51 (FIG. 8A). As the conductive substrate 51, as described above, a metal substrate (thickness: 100 to 250 μm) of 42 alloy (Ni 41% Fe alloy), copper, copper alloy, or the like can be used. It is preferable to use those which have been subjected to degreasing and washing treatment. Metal layer 5
Can be formed by a known film formation method such as a plating method, a vacuum evaporation method, and a sputtering method using a material having lower etching workability than the conductive substrate 51. For example,
Cu, Ni, Sn, Ag, Pd, Au, Pt, Rh, R
Among u and its alloys, a single layer made of one kind of material appropriately selected in consideration of the difference from the etching processability of the conductive substrate 51 or a multilayer of two or more kinds can be used. The thickness of the metal layer 5 can be set in consideration of the difference from the etching processability of the conductive substrate 51, and can be, for example, about 2 to 20 μm.

【００４７】次に、エッチング工程を行う。このエッチ
ング工程では、まず、金属層５を有する導電性基板５１
の両面に感光性レジストを塗布、乾燥し、これを所望の
フォトマスクを介して露光した後、現像して、導電性基
板５１の表面側にレジストパターン５３Ａを、裏面側
（金属層５上）にレジストパターン５３Ｂを形成する
（図８（Ｂ））。感光性レジストとしては、従来公知の
ものを使用することができる。次いで、レジストパター
ン５３Ａ，５３Ｂを耐腐蝕膜として導電性基板５１およ
び金属層５に対して腐蝕液でエッチングを行う（図８
（Ｃ））。腐蝕液は、通常、塩化第二鉄水溶液を使用
し、導電性基板５１の両面からスプレーエッチングにて
行う。このエッチング工程により、外枠部材２と、接続
リード４を介して相互に独立するように外枠部材２に連
結された複数の端子部３と、接続リード９（図示せず）
を介して外枠部材２に連結されたダイパッド７が形成さ
れる。また、エッチングで除去された端子部３、接続リ
ード４、ダイパッド７および接続リード９（図示せず）
の側面部は、導電性基板５１がエッチング加工性の低い
金属層５よりも内側まで腐蝕除去され、その結果、金属
層５は側面部へ突出する突出部５ａを有するものとな
る。また、形成されたダイパッド７は、裏面７Ｂに複数
の凹部８が形成されており、この凹部８は導電性基板５
１がエッチング加工性の低い金属層５よりも内側まで腐
蝕除去され形成されたものである。したがって、凹部８
の開口部８ａは、この開口部８ａに突出している金属層
５の突出部５ａの開口幅よりも大きくなっている。Next, an etching step is performed. In this etching step, first, the conductive substrate 51 having the metal layer 5
A photosensitive resist is applied to both sides of the conductive substrate 51, dried, exposed through a desired photomask, and then developed to form a resist pattern 53A on the front surface of the conductive substrate 51, and a back surface (on the metal layer 5). Then, a resist pattern 53B is formed (FIG. 8B). A conventionally known photosensitive resist can be used. Next, the conductive substrate 51 and the metal layer 5 are etched with a corrosion liquid using the resist patterns 53A and 53B as a corrosion-resistant film (FIG. 8).
(C)). The etchant is usually an aqueous ferric chloride solution, and is spray-etched from both sides of the conductive substrate 51. By this etching step, the outer frame member 2, the plurality of terminals 3 connected to the outer frame member 2 via the connection leads 4 so as to be independent from each other, and the connection leads 9 (not shown).
The die pad 7 connected to the outer frame member 2 through the fin is formed. Also, the terminal portion 3, the connection lead 4, the die pad 7, and the connection lead 9 (not shown) removed by etching.
Is etched away from the conductive substrate 51 to the inside of the metal layer 5 having low etching processability, and as a result, the metal layer 5 has a protrusion 5a projecting to the side surface. The formed die pad 7 has a plurality of recesses 8 formed on the back surface 7B.
No. 1 is formed by removing corrosion to the inside of the metal layer 5 having low etching processability. Therefore, the recess 8
Of the metal layer 5 projecting from the opening 8a is larger than the opening width of the projection 5a.

【００４８】次いで、レジストパターン５３Ａ，５３Ｂ
を剥離して除去し、内部端子３ａ上の所定位置に、端子
接続用のめっき部材６を形成して、図１乃至図４に示さ
れる本発明の回路部材１が得られる（図８（Ｄ）。Next, resist patterns 53A and 53B
Is peeled off and a plating member 6 for terminal connection is formed at a predetermined position on the internal terminal 3a to obtain the circuit member 1 of the present invention shown in FIGS. 1 to 4 (FIG. 8 (D)). ).

【００４９】尚、図５に示される本発明の回路部材１１
の製造は、両面に金属層５を設けた導電性基板５１を使
用することにより、上記の回路部材１の製造方法と同様
の工程で行うことができる。The circuit member 11 of the present invention shown in FIG.
By using the conductive substrate 51 provided with the metal layers 5 on both sides, the production of the circuit member 1 can be performed in the same steps as the method of producing the circuit member 1 described above.

【００５０】次に、本発明の回路部材１を用いた樹脂封
止型半導体装置の製造方法について、図９を参照して説
明する。Next, a method of manufacturing a resin-sealed semiconductor device using the circuit member 1 of the present invention will be described with reference to FIG.

【００５１】図９において、まず、上述の本発明の製造
方法により製造した回路部材１を用い、この回路部材１
のダイパッド７の表面７Ａ側に半導体素子１０２の回路
形成面反対側を電気絶縁性の両面接着テープ１０５を介
して固着することにより、半導体素子１０２を搭載する
（図９（Ａ））。In FIG. 9, first, the circuit member 1 manufactured by the above-described manufacturing method of the present invention is used.
The semiconductor element 102 is mounted by fixing the opposite side of the circuit forming surface of the semiconductor element 102 to the surface 7A side of the die pad 7 via an electrically insulating double-sided adhesive tape 105 (FIG. 9A).

【００５２】次に、搭載した半導体素子１０２の端子１
０２ａと、回路部材の内部端子３ａのめっき部材６と
を、ボンディングワイヤ１０４で電気的に接続する（図
９（Ｂ））。Next, the terminal 1 of the mounted semiconductor element 102
02a and the plating member 6 of the internal terminal 3a of the circuit member are electrically connected by the bonding wire 104 (FIG. 9B).

【００５３】次いで、端子部３、ダイパッド７、半導体
素子１０２およびボンディングワイヤ１０４を封止樹脂
１０６で封止する（図９（Ｃ））。次いで、回路部材１
の各接続リード４および接続リード９を切断し外枠部材
２を除去し、封止樹脂１０６から突出している外部端子
３ｂを所定の形状に加工して、樹脂封止型の半導体装置
１０１を得ることができる（図９（Ｄ））。回路部材の製造方法の第２の実施形態 図１０および図１１は、図６に示される本発明の回路部
材２１を例とした本発明の回路部材の製造方法の一実施
形態を示す工程図である。各工程は、図６に対応する回
路部材の縦断面図で示してある。Next, the terminal 3, the die pad 7, the semiconductor element 102, and the bonding wire 104 are sealed with a sealing resin 106 (FIG. 9C). Next, the circuit member 1
The connection lead 4 and the connection lead 9 are cut off, the outer frame member 2 is removed, and the external terminals 3b protruding from the sealing resin 106 are processed into a predetermined shape to obtain the resin-sealed semiconductor device 101. (FIG. 9D). Second Embodiment of Method for Manufacturing Circuit Member FIGS. 10 and 11 are process diagrams showing an embodiment of a method for manufacturing a circuit member of the present invention using the circuit member 21 of the present invention shown in FIG. 6 as an example. is there. Each step is shown in a longitudinal sectional view of the circuit member corresponding to FIG.

【００５４】図１０および図１１において、まず、金属
層形成工程として、導電性基板６１の一方の面に金属層
２５を形成する（図１０（Ａ））。使用する導電性基板
６１、および、導電性基板６１に形成する金属層２５
は、上述の製造方法の第１の実施形態における導電性基
板５１、金属層５と同様である。10 and 11, first, as a metal layer forming step, a metal layer 25 is formed on one surface of a conductive substrate 61 (FIG. 10A). The conductive substrate 61 to be used and the metal layer 25 formed on the conductive substrate 61
Are the same as the conductive substrate 51 and the metal layer 5 in the first embodiment of the manufacturing method described above.

【００５５】次に、上述の製造方法の第１の実施形態と
同様に、エッチング工程を行う。このエッチング工程で
は、まず、金属層２５を有する導電性基板６１の両面に
感光性レジストを塗布、乾燥し、これを所望のフォトマ
スクを介して露光した後、現像して、導電性基板６１の
表面側にレジストパターン６３Ａを、裏面側（金属層２
５上）にレジストパターン６３Ｂを形成する（図１０
（Ｂ））。次いで、レジストパターン６３Ａ，６３Ｂを
耐腐蝕膜として導電性基板６１および金属層２５に対し
て腐蝕液でエッチングを行う（図１０（Ｃ））。このエ
ッチング工程により、外枠部材２２（図示せず）と、接
続リード２４（図示せず）を介して相互に独立するよう
に外枠部材２２に連結された複数の端子部２３と、接続
リード２９（図示せず）を介して外枠部材２２に連結さ
れたダイパッド２７が形成される。形成された端子部２
３の内部端子２３ａはハーフエッチングによる薄肉部と
なっている。また、エッチングで除去された端子部２
３、接続リード２４、ダイパッド２７および接続リード
２９の側面部は、導電性基板６１がエッチング加工性の
低い金属層２５よりも内側まで腐蝕除去され、その結
果、金属層２５は側面部へ突出する突出部２５ａを有す
るものとなる。また、形成されたダイパッド２７は、裏
面２７Ｂに複数の凹部２８が形成されており、この凹部
２８は導電性基板６１がエッチング加工性の低い金属層
２５よりも内側まで腐蝕除去され形成されたものであ
る。したがって、凹部２８の開口部２８ａは、この開口
部２８ａに突出している金属層２５の突出部２５ａの開
口幅よりも大きくなっている。Next, an etching step is performed in the same manner as in the first embodiment of the manufacturing method described above. In this etching step, first, a photosensitive resist is applied to both surfaces of the conductive substrate 61 having the metal layer 25, dried, exposed through a desired photomask, developed, and developed. A resist pattern 63A is formed on the front side, and
5) is formed (FIG. 10).
(B)). Next, the conductive substrate 61 and the metal layer 25 are etched with a corrosion liquid using the resist patterns 63A and 63B as a corrosion-resistant film (FIG. 10C). By this etching step, the outer frame member 22 (not shown), the plurality of terminals 23 connected to the outer frame member 22 via connection leads 24 (not shown) so as to be independent from each other, and the connection leads Die pad 27 connected to outer frame member 22 via 29 (not shown) is formed. Terminal part 2 formed
The third internal terminal 23a is a thin portion formed by half etching. Also, the terminal portion 2 removed by etching
3. The side surfaces of the connection lead 24, the die pad 27, and the connection lead 29 are removed by corrosion of the conductive substrate 61 to the inside of the metal layer 25 having low etching processability, and as a result, the metal layer 25 projects to the side surface. It has a protruding portion 25a. The formed die pad 27 has a plurality of recesses 28 formed on the back surface 27B, and the recesses 28 are formed by etching and removing the conductive substrate 61 to the inside of the metal layer 25 having low etching processability. It is. Therefore, the opening 28a of the recess 28 is larger than the opening width of the protrusion 25a of the metal layer 25 projecting from the opening 28a.

【００５６】次に、めっき工程として、エッチング加工
が終了した導電性基板６１をめっき浴に浸漬し、残って
いるレジストパターン６３Ａ，６３Ｂをマスクとして、
導電性基板６１と金属層２５の露出部位に電気めっきに
よりめっき層３０を形成する（図１１（Ａ））。めっき
層３０は、端子部２３、接続リード２４、ダイパッド２
７、接続リード２９の各側面と、ダイパッド２７に設け
られた凹部２８内と、金属層２５の側端面とに設けられ
ている。特に、上記の突出部２５ａの端面である金属層
２５の側端面では、金属析出が大きくめっき層３０の厚
みが大きいものとなる。Next, as a plating step, the conductive substrate 61 after the etching is immersed in a plating bath, and the remaining resist patterns 63A and 63B are used as masks.
The plating layer 30 is formed on the exposed portions of the conductive substrate 61 and the metal layer 25 by electroplating (FIG. 11A). The plating layer 30 includes the terminal portion 23, the connection lead 24, and the die pad 2.
7, are provided on each side surface of the connection lead 29, in the concave portion 28 provided in the die pad 27, and on the side end surface of the metal layer 25. In particular, on the side end surface of the metal layer 25 which is the end surface of the protruding portion 25a, the metal deposition is large and the thickness of the plating layer 30 is large.

【００５７】めっき層３０は、Ｃｕ、Ｎｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層とすることができる。The plating layer 30 is made of Cu, Ni, Sn, A
It may be a single layer composed of any of g, Pd, Au, Pt, Rh, Ru and alloys thereof, or a multilayer composed of a combination of two or more.

【００５８】次いで、レジストパターン６３Ａ，６３Ｂ
を剥離して除去し、内部端子２３ａ上の所定位置に、端
子接続用のめっき部材２６を形成して、図６に示される
本発明の回路部材２１が得られる（図１１（Ｂ））。Next, the resist patterns 63A, 63B
Is peeled off, and a plating member 26 for terminal connection is formed at a predetermined position on the internal terminal 23a to obtain the circuit member 21 of the present invention shown in FIG. 6 (FIG. 11B).

【００５９】尚、めっき工程で形成しためっき層３０に
樹脂封止部材との密着性を向上させるために、化学的結
合強化処理や粗面化処理（物理的結合強化処理）を施し
てもよい。粗面化処理は、Ｚｎ−Ｃｒ合金等のめっき層
形成（米国オーリン社のＡ２プロセス）、もしくはニッ
ケルめっきに対する種々のクロメート処理等が挙げら
れ、めっき層３０の表面粗さＲａを３０ｎｍ以上程度に
設定することが好ましい。このような粗面化処理を施す
ことにより、めっき層３０の封止樹脂に対する密着性が
向上する。The plating layer 30 formed in the plating step may be subjected to a chemical bond strengthening treatment or a roughening treatment (physical bond strengthening treatment) in order to improve the adhesion to the resin sealing member. . Examples of the surface roughening treatment include formation of a plating layer of a Zn—Cr alloy or the like (A2 process of Ohlin Co., USA) or various chromate treatments for nickel plating. The surface roughness Ra of the plating layer 30 is reduced to about 30 nm or more. It is preferable to set. By performing such a roughening treatment, the adhesion of the plating layer 30 to the sealing resin is improved.

【００６０】このような本発明の回路部材２１を用いた
樹脂封止型半導体装置の製造方法は、上述の図９に示し
たものと同様である。回路部材の製造方法の第３の実施形態 図１２および図１３は、図７に示される本発明の回路部
材３１を例とした本発明の回路部材の製造方法の一実施
形態を示す工程図である。各工程は、図７に対応する回
路部材の縦断面図で示してある。The method of manufacturing a resin-encapsulated semiconductor device using such a circuit member 21 of the present invention is the same as that shown in FIG. Third Embodiment of Circuit Member Manufacturing Method FIGS. 12 and 13 are process diagrams showing an embodiment of a circuit member manufacturing method of the present invention using the circuit member 31 of the present invention shown in FIG. 7 as an example. is there. Each step is shown in a longitudinal sectional view of the circuit member corresponding to FIG.

【００６１】図１２および図１３において、まず、金属
層形成工程として、導電性基板７１の両面に金属層３５
を形成する（図１２（Ａ））。使用する導電性基板７
１、および、導電性基板７１に形成する金属層３５は、
上述の製造方法の第１の実施形態における導電性基板５
１、金属層５と同様である。12 and 13, first, as a metal layer forming step, a metal layer 35 is formed on both surfaces of a conductive substrate 71.
Is formed (FIG. 12A). Used conductive substrate 7
1, and the metal layer 35 formed on the conductive substrate 71
Conductive substrate 5 in the first embodiment of the above-described manufacturing method
1. Same as the metal layer 5.

【００６２】次に、上述の製造方法の第１の実施形態と
同様に、エッチング加工を行う。このエッチング工程で
は、まず、電性基板７１の両面（金属層３５上）に感光
性レジストを塗布、乾燥し、これを所望のフォトマスク
を介して露光した後、現像して、導電性基板７１の表面
側にレジストパターン７３Ａを、裏面側にレジストパタ
ーン７３Ｂを形成する（図１２（Ｂ））。次いで、レジ
ストパターン７３Ａ，７３Ｂを耐腐蝕膜として導電性基
板７１および金属層３５に対して腐蝕液でエッチングを
行う（図１２（Ｃ））。このエッチング工程により、外
枠部材３２（図示せず）と、接続リード３４（図示せ
ず）を介して相互に独立するように外枠部材３２に連結
された複数の端子部３３と、接続リード３９を介して外
枠部材３２に連結されたダイパッド３７が形成される。
形成された端子部３３の内部端子３３ａはハーフエッチ
ングによる薄肉部となっている。また、エッチングで除
去された端子部３３、接続リード３４、ダイパッド３７
および接続リード３９の側面部は、導電性基板７１がエ
ッチング加工性の低い金属層３５よりも内側まで腐蝕除
去され、その結果、金属層３５は側面部へ突出する突出
部３５ａを有するものとなる。また、形成されたダイパ
ッド３７は、裏面３７Ｂに複数の凹部３８が形成されて
おり、この凹部３８は導電性基板７１がエッチング加工
性の低い金属層３５よりも内側まで腐蝕除去され形成さ
れたものである。したがって、凹部３８の開口部３８ａ
は、この開口部３８ａに突出している金属層３５の突出
部３５ａの開口幅よりも大きくなっている。Next, etching is performed in the same manner as in the first embodiment of the manufacturing method described above. In this etching step, first, a photosensitive resist is applied to both surfaces (on the metal layer 35) of the conductive substrate 71, dried, exposed through a desired photomask, and developed, and then developed. A resist pattern 73A is formed on the front side and a resist pattern 73B is formed on the back side (FIG. 12B). Next, the resist pattern 73A, 73B is used as a corrosion-resistant film, and the conductive substrate 71 and the metal layer 35 are etched with a corrosion liquid (FIG. 12C). By this etching step, the outer frame member 32 (not shown), the plurality of terminal portions 33 connected to the outer frame member 32 via connection leads 34 (not shown) so as to be independent from each other, and the connection leads A die pad 37 connected to the outer frame member 32 via 39 is formed.
The internal terminal 33a of the formed terminal portion 33 is a thin portion formed by half etching. Further, the terminal portion 33, the connection lead 34, and the die pad 37 removed by the etching are used.
The conductive substrate 71 is corroded and removed from the side surfaces of the connection leads 39 to the inside of the metal layer 35 having low etching processability. As a result, the metal layer 35 has a protrusion 35a protruding to the side surface. . The formed die pad 37 has a plurality of recesses 38 formed on the back surface 37B, and the recesses 38 are formed by etching and removing the conductive substrate 71 to the inside of the metal layer 35 having low etching processability. It is. Therefore, the opening 38a of the recess 38
Is larger than the opening width of the protruding portion 35a of the metal layer 35 protruding from the opening 38a.

【００６３】次いで、レジストパターン７３Ａ，７３Ｂ
を剥離して除去する（図１３（Ａ）レジスト除去工
程）。Next, resist patterns 73A and 73B
Is removed (FIG. 13 (A) resist removing step).

【００６４】次に、めっき工程として、レジスト除去が
終了した導電性基板７１をめっき浴に浸漬して、導電性
基板７１と金属層３５の露出部位に電気めっきによりめ
っき層４０を形成して、図７に示される本発明の回路部
材３１が得られる（図１３（Ｂ））。めっき層４０は、
端子部３３、接続リード３４、ダイパッド３７、接続リ
ード３９の各側面と、ダイパッド３７に設けられた凹部
３８内と、金属層３５上とに設けられている。特に、上
記の突出部３５ａでは、金属析出が大きくめっき層４０
の厚みが大きいものとなる。Next, as a plating step, the conductive substrate 71 from which the resist has been removed is immersed in a plating bath to form a plating layer 40 on the exposed portions of the conductive substrate 71 and the metal layer 35 by electroplating. The circuit member 31 of the present invention shown in FIG. 7 is obtained (FIG. 13B). The plating layer 40
The side surfaces of the terminal portion 33, the connection lead 34, the die pad 37, and the connection lead 39, the inside of the concave portion 38 provided in the die pad 37, and the metal layer 35 are provided. In particular, in the protruding portion 35a, the metal deposition is large and the plating layer 40
Becomes thicker.

【００６５】めっき層４０は、Ｃｕ、Ｎｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層とすることができる。The plating layer 40 is made of Cu, Ni, Sn, A
It may be a single layer composed of any of g, Pd, Au, Pt, Rh, Ru and alloys thereof, or a multilayer composed of a combination of two or more.

【００６６】尚、めっき工程で形成しためっき層４０に
樹脂封止部材との密着性を向上させるために、化学的結
合強化処理や粗面化処理（物理的結合強化処理）を施し
てもよい。粗面化処理は、Ｚｎ−Ｃｒ合金等のめっき層
形成（米国オーリン社のＡ２プロセス）、もしくはニッ
ケルめっきに対する種々のクロメート処理等が挙げら
れ、めっき層４０の表面粗さＲａを３０ｎｍ以上程度に
設定することが好ましい。このような粗面化処理を施す
ことにより、めっき層４０の封止樹脂に対する密着性が
向上する。The plating layer 40 formed in the plating step may be subjected to a chemical bond strengthening treatment or a roughening treatment (physical bond strengthening treatment) in order to improve the adhesion to the resin sealing member. . Examples of the surface roughening treatment include formation of a plating layer of a Zn—Cr alloy or the like (A2 process of U.S.A. U.S.A.) or various chromate treatments for nickel plating, and the like. It is preferable to set. By performing such a roughening treatment, the adhesion of the plating layer 40 to the sealing resin is improved.

【００６７】このような本発明の回路部材３１を用いた
樹脂封止型半導体装置の製造方法は、上述の図９に示し
たものと同様である。A method for manufacturing a resin-encapsulated semiconductor device using such a circuit member 31 of the present invention is the same as that shown in FIG.

【００６８】[0068]

【実施例】次に、具体的な実施例を挙げて本発明を更に
詳細に説明する。 （実施例１）導電性基板として厚み０．１５ｍｍのＣｕ
合金基板（古河電気工業（株）製ＥＦＴＥＣ６４Ｔ−１
／２Ｈ）を準備し、脱脂処理、洗浄処理を行った後、こ
の導電性基板の片面にＮｉ電気めっき（ワット浴）によ
り厚み２μｍのＮｉ金属層を形成した。Next, the present invention will be described in more detail with reference to specific examples. (Example 1) Cu having a thickness of 0.15 mm was used as a conductive substrate.
Alloy substrate (EFTEC64T-1 manufactured by Furukawa Electric Co., Ltd.)
/ 2H), and after performing a degreasing treatment and a washing treatment, a Ni metal layer having a thickness of 2 μm was formed on one surface of the conductive substrate by Ni electroplating (watt bath).

【００６９】このようにＮｉ金属層を形成したＣｕ合金
基板に、紫外線硬化型レジスト（東京応化工業（株）製
ＯＦＰＲ１３０５）を掛け流し法により塗布して乾燥し
た。次いで、表面側および裏面側のレジスト層を、２０
８ピンＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
タイプの回路部材作製用のフォトマスクを介してそれぞ
れ露光した後、現像してレジストパターンを形成した。
上記のフォトマスクは、ダイパッドの裏面（Ｎｉ金属層
形成面側）にハーフエッチング加工により半球形状の凹
部（ディンプル）が形成される設計となっている。次
に、導電性基板の両面から塩化第二鉄水溶液を使用して
スプレーエッチングを行い、洗浄後、有機アルカリ溶液
を用いてレジストパターンを剥離除去した。An ultraviolet-curable resist (OFPR1305, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to the Cu alloy substrate on which the Ni metal layer had been formed in this manner by a flowing method and dried. Next, the resist layer on the front side and the back side is
8-pin QFP (Quad Flat Package)
After each exposure through a photomask for producing a type circuit member, development was performed to form a resist pattern.
The photomask is designed such that hemispherical concave portions (dimples) are formed by half-etching on the back surface of the die pad (on the side where the Ni metal layer is formed). Next, spray etching was performed on both surfaces of the conductive substrate using an aqueous ferric chloride solution, and after cleaning, the resist pattern was peeled off using an organic alkali solution.

【００７０】上記のエッチング工程では、Ｃｕ合金基板
がエッチング加工性の低いＮｉ金属層よりも内側まで腐
蝕除去された。その結果、得られた回路部材は、図１〜
図４に示されるように裏面にＮｉ金属層を備え、このＮ
ｉ金属層は端子部、接続リード部の側面部へ突出する突
出部、ダイパッドの側面部へ突出する突出部、および、
ダイパッドの凹部の開口部へ突出する突出部とを有する
ものであった。 （実施例２）導電性基板として厚み０．１５ｍｍのＣｕ
合金基板（古河電気工業（株）製ＥＦＴＥＣ６４Ｔ−１
／２Ｈ）を準備し、脱脂処理、洗浄処理を行った後、こ
の導電性基板の片面にＮｉ電気めっき（ワット浴）によ
り厚み２μｍのＮｉ金属層を形成した。In the above etching step, the Cu alloy substrate was etched away to the inside of the Ni metal layer having low etching processability. As a result, the obtained circuit members are shown in FIGS.
As shown in FIG. 4, a Ni metal layer is provided on the
The i metal layer has a terminal portion, a projecting portion projecting to a side portion of the connection lead portion, a projecting portion projecting to a side portion of the die pad, and
And a protrusion protruding into the opening of the concave portion of the die pad. (Example 2) Cu having a thickness of 0.15 mm was used as a conductive substrate.
Alloy substrate (EFTEC64T-1 manufactured by Furukawa Electric Co., Ltd.)
/ 2H), and after performing a degreasing treatment and a washing treatment, a Ni metal layer having a thickness of 2 μm was formed on one surface of the conductive substrate by Ni electroplating (watt bath).

【００７１】このようにＮｉ金属層を形成したＣｕ合金
基板に、紫外線硬化型レジスト（東京応化工業（株）製
ＯＦＰＲ１３０５）を掛け流し法により塗布して乾燥し
た。次いで、表面側および裏面側のレジスト層を、２０
８ピンＱＦＰタイプの回路部材作製用のフォトマスクを
介してそれぞれ露光した後、現像してレジストパターン
を形成した。上記のフォトマスクは、ダイパッドの裏面
（Ｎｉ金属層形成面側）にハーフエッチング加工により
半球形状の凹部（ディンプル）が形成される設計となっ
ている。次に、導電性基板の両面から塩化第二鉄水溶液
を使用してスプレーエッチングを行い洗浄した。上記の
エッチング工程では、Ｃｕ合金基板がエッチング加工性
の低いＮｉ金属層よりも内側まで腐蝕除去された。An ultraviolet-curable resist (OFPR1305, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to the Cu alloy substrate on which the Ni metal layer had been formed in this manner by a flowing method and dried. Next, the resist layer on the front side and the back side is
After each exposure through a photomask for producing an 8-pin QFP type circuit member, development was performed to form a resist pattern. The photomask is designed such that hemispherical concave portions (dimples) are formed by half-etching on the back surface of the die pad (on the side where the Ni metal layer is formed). Next, both surfaces of the conductive substrate were washed by spray etching using an aqueous ferric chloride solution. In the above etching step, the Cu alloy substrate was etched away to the inside of the Ni metal layer having low etching processability.

【００７２】次に、残存しているレジストパターンをマ
スクとして、Ｃｕ電気めっき（シアン浴）により厚み２
μｍのＣｕめっき層を形成した。その後、有機アルカリ
溶液を用いてレジストパターンを剥離除去して回路部材
を得た。得られた回路部材は、図６に示されるように裏
面にＮｉ金属層を備え、このＮｉ金属層は端子部、接続
リード部の側面部へ突出する突出部、ダイパッドの側面
部へ突出する突出部、および、ダイパッドの凹部の開口
部へ突出する突出部を有するものであった。そして、端
子部のハーフエッチング部（薄肉部）や側面部、ダイパ
ッドの側面部や凹部内面、および、Ｎｉ金属層の突出部
にはＣｕめっき層が形成され、一方、回路部材の表面に
はＣｕめっき層が形成されていないことが確認された。 （実施例３）導電性基板として厚み０．１５ｍｍのＣｕ
合金基板（古河電気工業（株）製ＥＦＴＥＣ６４Ｔ−１
／２Ｈ）を準備し、脱脂処理、洗浄処理を行った後、こ
の導電性基板の両面にＮｉ電気めっき（ワット浴）によ
り厚み２μｍのＮｉ金属層を形成した。Next, using the remaining resist pattern as a mask, Cu electroplating (cyan bath) is applied to a thickness of 2 mm.
A μm Cu plating layer was formed. Thereafter, the resist pattern was peeled off using an organic alkali solution to obtain a circuit member. The obtained circuit member is provided with a Ni metal layer on the back surface as shown in FIG. 6, and the Ni metal layer has a protrusion protruding to the side surface of the terminal portion, the connection lead portion, and a protrusion protruding to the side surface of the die pad. And a protrusion protruding into the opening of the concave portion of the die pad. Then, a Cu plating layer is formed on the half-etched portion (thin portion) and the side surface of the terminal portion, the side surface and the inner surface of the concave portion of the die pad, and the protruding portion of the Ni metal layer. It was confirmed that the plating layer was not formed. (Example 3) Cu having a thickness of 0.15 mm as a conductive substrate
Alloy substrate (EFTEC64T-1 manufactured by Furukawa Electric Co., Ltd.)
/ 2H) was prepared, subjected to a degreasing treatment and a cleaning treatment, and then a Ni metal layer having a thickness of 2 μm was formed on both surfaces of the conductive substrate by Ni electroplating (watt bath).

【００７３】このようにＮｉ金属層を形成したＣｕ合金
基板に、紫外線硬化型レジスト（東京応化工業（株）製
ＯＦＰＲ１３０５）を掛け流し法により塗布して乾燥し
た。次いで、表面側および裏面側のレジスト層を、２０
８ピンＱＦＰタイプの回路部材作製用のフォトマスクを
介してそれぞれ露光した後、現像してレジストパターン
を形成した。上記のフォトマスクは、ダイパッドの裏面
にハーフエッチング加工により半球形状の凹部（ディン
プル）が形成される設計となっている。その後、導電性
基板の両面から塩化第二鉄水溶液を使用してスプレーエ
ッチングを行い、洗浄後、有機アルカリ溶液を用いてレ
ジストパターンを剥離除去した。上記のエッチング工程
では、Ｃｕ合金基板がエッチング加工性の低いＮｉ金属
層よりも内側まで腐蝕除去された。その結果、レジスト
パターン除去段階で得られた回路部材は、表面および裏
面にＮｉ金属層を備え、このＮｉ金属層は端子部、接続
リード部の側面部へ突出する突出部、ダイパッドの側面
部へ突出する突出部、および、ダイパッドの凹部の開口
部へ突出する突出部とを有するものであった。An ultraviolet-curable resist (OFPR1305 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to the Cu alloy substrate on which the Ni metal layer had been formed in this manner by a flowing method and dried. Next, the resist layer on the front side and the back side is
After each exposure through a photomask for producing an 8-pin QFP type circuit member, development was performed to form a resist pattern. The above photomask is designed so that a half-spherical concave portion (dimple) is formed on the back surface of the die pad by half etching. Thereafter, spray etching was performed on both surfaces of the conductive substrate using an aqueous ferric chloride solution, and after cleaning, the resist pattern was peeled off using an organic alkali solution. In the above etching step, the Cu alloy substrate was etched away to the inside of the Ni metal layer having low etching processability. As a result, the circuit member obtained in the resist pattern removing step has a Ni metal layer on the front and back surfaces, and this Ni metal layer is formed on the terminal portion, the protrusion protruding to the side portion of the connection lead portion, and the side portion of the die pad. It had a protruding portion and a protruding portion that protruded into the opening of the concave portion of the die pad.

【００７４】次に、上記の回路部材にＮｉ電気めっき
（ワット浴）により厚み１μｍのＮｉめっき層を形成
し、この上にＰｄ電気めっき（アンミン浴）により厚み
０．１μｍのＰｄめっき層を形成して２層構造のＮｉ−
Ｐｄめっき層を設けた。これにより得られた回路部材
は、図７に示されるように表面および裏面の全体にＮｉ
−Ｐｄめっき層が形成されたものであった。Next, a 1 μm thick Ni plating layer was formed on the above circuit member by Ni electroplating (Watt bath), and a 0.1 μm thick Pd plating layer was formed thereon by Pd electroplating (ammine bath). To form a two-layer Ni-
A Pd plating layer was provided. The circuit member thus obtained has Ni over the entire front and back surfaces as shown in FIG.
-A Pd plating layer was formed.

【００７５】尚、比較として、Ｃｕ合金基板上にＮｉめ
っき層を形成しない他は、実施例１と同様にして回路部
材（比較例１）を作製した。As a comparison, a circuit member (Comparative Example 1) was produced in the same manner as in Example 1 except that no Ni plating layer was formed on a Cu alloy substrate.

【００７６】さらに、比較として、Ｃｕ合金基板上にＮ
ｉめっき層を形成せず、かつ、ダイパッド裏面に凹部
（ディンプル）を形成しない他は、実施例１と同様にし
て回路部材（比較例２）を作製した。 （半導体装置の作製）まず、上記の回路部材のうち実施
例１〜２、比較例１〜２の内部端子上に銀めっき層（厚
み約５μｍ）を形成した。Further, for comparison, N on a Cu alloy substrate
A circuit member (Comparative Example 2) was produced in the same manner as in Example 1 except that no i-plated layer was formed and no concave portion (dimple) was formed on the back surface of the die pad. (Preparation of Semiconductor Device) First, a silver plating layer (about 5 μm in thickness) was formed on the internal terminals of Examples 1 and 2 and Comparative Examples 1 and 2 among the above circuit members.

【００７７】次に、上記の回路部材（実施例１〜３、比
較例１〜２）のダイパッド表面側に両面接着テープ
（（株）巴川製紙所製ＵＸ１Ｗ）を介して半導体素子の
回路形成面の裏面側を圧着して加熱（１８０℃）するこ
とにより固着して半導体素子を搭載した。次いで、回路
部材の内部端子と搭載した半導体素子の端子とを金線に
より結線した。その後、外部端子の一部を外部に露出さ
せるようにして、端子部、ダイパッド、半導体素子およ
び金線を封止樹脂（日東電工（株）製ＭＰ−８０００）
で封止した。Next, the circuit forming surface of the semiconductor element was applied to the surface of the die pad of the above-mentioned circuit members (Examples 1 to 3 and Comparative Examples 1 and 2) via a double-sided adhesive tape (UX1W manufactured by Tomagawa Paper Co., Ltd.). The semiconductor element was mounted by pressing the back surface of the substrate and pressing (180 ° C.) to fix it. Next, the internal terminal of the circuit member and the terminal of the mounted semiconductor element were connected by a gold wire. Thereafter, the terminal portion, the die pad, the semiconductor element, and the gold wire are sealed with a sealing resin (MP-8000 manufactured by Nitto Denko Corporation) so that a part of the external terminal is exposed to the outside.
And sealed.

【００７８】次に、露出している回路部材の各接続リー
ドを切断して外枠部材を除去し、封止樹脂から外部に突
出している外部端子を所定形状に折り曲げて、樹脂封止
型半導体装置（２０８ピンＱＦＰ（２．２ｍｍ厚））を
作製した。Next, each connection lead of the exposed circuit member is cut to remove the outer frame member, and the external terminal projecting outside from the sealing resin is bent into a predetermined shape to form a resin-sealed semiconductor. An apparatus (208-pin QFP (2.2 mm thickness)) was manufactured.

【００７９】このようにして作製した樹脂封止型半導体
装置（実施例１〜３、比較例１〜２）に対して、下記の
パッケージクラック試験を実施し、実体顕微鏡（倍率１
０〜４０）で外観を観察し、パッケージクラックの発生
数を測定した。この結果を下記の表１に示した。The following package crack test was performed on the resin-encapsulated semiconductor devices (Examples 1 to 3 and Comparative Examples 1 and 2) manufactured as described above, and a stereoscopic microscope (magnification: 1) was used.
0 to 40), the appearance was observed, and the number of occurrences of package cracks was measured. The results are shown in Table 1 below.

【００８０】パッケージクラック試験 ２４０℃の共晶はんだ浴に浸漬（１０秒間×３回）する
操作を、樹脂封止型半導体装置の作製後、４時間、８時
間、１６時間、３２時間、６４時間の経時で行う。尚、
１回の浸漬操作には５個の樹脂封止型半導体装置を使用
し、また、樹脂封止型半導体装置は８５℃、８５％ＲＨ
の環境下で保管する。 Package Crack Test The operation of immersing in a eutectic solder bath at 240 ° C. (10 seconds × 3 times) was performed for 4 hours, 8 hours, 16 hours, 32 hours, and 64 hours after the production of the resin-encapsulated semiconductor device. With time. still,
One immersion operation uses five resin-encapsulated semiconductor devices, and the resin-encapsulated semiconductor device is 85 ° C. and 85% RH.
Store in the environment.

【００８１】[0081]

【表１】 表１に示されるように、本発明の回路部材を使用した樹
脂封止型半導体装置（実施例１〜３）は、いずれも６４
時間経過後もパッケージクラックが発生せず、高い耐性
を有していることが確認された。[Table 1] As shown in Table 1, the resin-encapsulated semiconductor devices using the circuit member of the present invention (Examples 1 to 3) were all 64.
Even after a lapse of time, no package crack occurred, and it was confirmed that the package had high resistance.

【００８２】一方、比較の回路部材（比較例１〜２）を
用いた樹脂封止型半導体装置は、８時間経過、あるいは
１６時間経過でパッケージクラックが発生した。On the other hand, in the resin-encapsulated semiconductor device using the comparative circuit member (Comparative Examples 1 and 2), a package crack occurred after a lapse of 8 hours or 16 hours.

【００８３】[0083]

【発明の効果】以上詳述したように、本発明によれば金
属層が、端子部の側面部へ突出し、ダイパッドの側面部
や凹部の開口部へ突出し、この金属層の突出部によっ
て、封止樹脂と端子部、ダイパッドが確実に固定される
ので、端子部やダイパッドの剥離が防止され、封止樹脂
にクラックの発生がない耐久性および信頼性に優れた樹
脂封止型の半導体装置が可能となる。As described above in detail, according to the present invention, the metal layer protrudes to the side surface of the terminal portion, protrudes to the side surface of the die pad and the opening of the concave portion, and is sealed by the protruding portion of the metal layer. Since the resin, the terminal portion, and the die pad are securely fixed, the terminal portion and the die pad are prevented from peeling off, and a resin-encapsulated semiconductor device having excellent durability and reliability without cracks in the sealing resin is provided. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の回路部材の一実施形態を示す平面図で
ある。FIG. 1 is a plan view showing one embodiment of a circuit member of the present invention.

【図２】図１に示される回路部材のＡ−Ａ線における縦
断面図である。FIG. 2 is a longitudinal sectional view of the circuit member shown in FIG. 1 taken along line AA.

【図３】図１に示される回路部材の端子部の部分拡大斜
視図である。FIG. 3 is a partially enlarged perspective view of a terminal portion of the circuit member shown in FIG.

【図４】図１に示される回路部材のダイパッドの裏面側
の斜視図である。FIG. 4 is a perspective view of a back surface side of a die pad of the circuit member shown in FIG. 1;

【図５】本発明の回路部材の他の実施形態を示す図２相
当の断面図である。FIG. 5 is a sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図６】本発明の回路部材の他の実施形態を示す図２相
当の断面図である。FIG. 6 is a sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図７】本発明の回路部材の他の実施形態を示す図２相
当の断面図である。FIG. 7 is a sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図８】図１乃至図４に示される回路部材の製造方法の
一実施形態を示す工程図である。FIG. 8 is a process chart showing one embodiment of a method for manufacturing the circuit member shown in FIGS. 1 to 4;

【図９】本発明の回路部材を用いた樹脂封止型半導体装
置の製造方法の一例を示す工程図である。FIG. 9 is a process chart showing an example of a method for manufacturing a resin-encapsulated semiconductor device using the circuit member of the present invention.

【図１０】図６に示される回路部材の製造方法の一実施
形態を示す工程図である。10 is a process chart showing one embodiment of a method for manufacturing the circuit member shown in FIG.

【図１１】図６に示される回路部材の製造方法の一実施
形態を示す工程図である。FIG. 11 is a process chart showing one embodiment of a method for manufacturing the circuit member shown in FIG.

【図１２】図７に示される回路部材の製造方法の一実施
形態を示す工程図である。12 is a process chart showing one embodiment of a method for manufacturing the circuit member shown in FIG.

【図１３】図７に示される回路部材の製造方法の一実施
形態を示す工程図である。13 is a process chart showing one embodiment of a method for manufacturing the circuit member shown in FIG.

【符号の説明】[Explanation of symbols]

１，１１，２１，３１…回路部材 ２，１２，２２，３２…外枠部材 ３，１３，２３，３３…端子部 ３ａ，１３ａ，２３ａ，３３ａ…内部端子 ３ｂ，１３ｂ，２３ｂ，３３ｂ…外部端子 ４，９，１４…接続リード ５，１５，２５，３５…金属層 ５ａ，１５ａ，２５ａ，３５ａ…突出部 ７，１７，２７，３７…ダイパッド ８，１８，２８，３８…凹部 ８ａ，１８ａ，２８ａ，３８ａ…凹部の開口部 ３０，４０…めっき層 ５１，６１，７１…導電性基板 ５３Ａ，５３Ｂ，６３Ａ，６３Ｂ，７３Ａ，７３Ｂ…レ
ジストパターン １０１…樹脂封止型半導体装置 １０２…半導体素子 １０２ａ…端子 １０４…ワイヤ １０６…封止樹脂1, 11, 21, 31 ... circuit member 2, 12, 22, 32 ... outer frame member 3, 13, 23, 33 ... terminal portion 3a, 13a, 23a, 33a ... internal terminal 3b, 13b, 23b, 33b ... outside Terminals 4, 9, 14 ... Connection leads 5, 15, 25, 35 ... Metal layers 5a, 15a, 25a, 35a ... Projection parts 7, 17, 27, 37 ... Die pads 8, 18, 28, 38 ... Concave parts 8a, 18a .., 28a, 38a... Recessed openings 30, 40... Plating layers 51, 61, 71... Conductive substrates 53A, 53B, 63A, 63B, 73A, 73B... Resist patterns 101. 102a: terminal 104: wire 106: sealing resin

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 外枠部材と、該外枠部材から各々接続リ
ードを介して相互に独立して配設された複数の端子部
と、前記外枠部材から接続リードを介して配設されたダ
イパッドとを備え、前記端子部は少なくとも一方の面に
側面部へ突出するような金属層を有し、前記ダイパッド
は少なくとも一方の面に凹部を有するとともに、少なく
とも該凹部の開口部へ突出するような金属層を有するこ
とを特徴とする樹脂封止型半導体装置用の回路部材。1. An outer frame member, a plurality of terminals arranged independently from each other via connection leads from the outer frame member, and a plurality of terminal portions provided from the outer frame member via connection leads. A die pad, wherein the terminal portion has a metal layer protruding to a side portion on at least one surface, and the die pad has a concave portion on at least one surface and protrudes at least to an opening of the concave portion. A circuit member for a resin-sealed semiconductor device, comprising: a metal layer. 【請求項２】 前記金属層はＮｉ、Ｓｎ、Ａｇ、Ｐｄ、
Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のいずれかから
なる単層、あるいは、２種以上の組み合わせの多層であ
ることを特徴とする請求項１に記載の樹脂封止型半導体
装置用の回路部材。2. The method according to claim 1, wherein the metal layer is formed of Ni, Sn, Ag, Pd,
The circuit member for a resin-encapsulated semiconductor device according to claim 1, wherein the circuit member is a single layer made of any one of Au, Pt, Rh, Ru, and an alloy thereof, or a multilayer of a combination of two or more kinds. . 【請求項３】 前記端子部の側面部と、前記ダイパッド
の凹部内表面と、前記金属層の少なくとも側端面とに、
めっき層を有することを特徴とする請求項１または請求
項２に記載の樹脂封止型半導体装置用の回路部材。3. A side surface of the terminal portion, an inner surface of a concave portion of the die pad, and at least a side end surface of the metal layer.
The circuit member for a resin-encapsulated semiconductor device according to claim 1, further comprising a plating layer. 【請求項４】 前記めっき層はＣｕ、Ｎｉ、Ｓｎ、Ａ
ｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよびその合金のい
ずれかからなる単層、あるいは、２種以上の組み合わせ
の多層であることを特徴とする請求項３に記載の樹脂封
止型半導体装置用の回路部材。4. The plating layer is made of Cu, Ni, Sn, A
4. The resin-encapsulated semiconductor device according to claim 3, wherein the device is a single layer made of any one of g, Pd, Au, Pt, Rh, Ru, and an alloy thereof, or a multilayer of a combination of two or more. Circuit members for 【請求項５】 導電性基板の少なくとも一方の面に、該
導電性基板よりもエッチング加工性の低い材料で金属層
を形成する金属層形成工程と、 金属層が形成された導電性基板の両面に所定の形状でレ
ジストパターンを形成し、該レジストパターンを耐腐蝕
膜として前記金属層および導電性基板をエッチングし
て、外枠部材と、接続リードを介して相互に独立するよ
うに前記外枠部材に連結された複数の端子部と、接続リ
ードを介して前記外枠部材に連結され少なくとも一方の
面に凹部を有するダイパッドを形成するエッチング工程
と、 レジストパターンを除去するレジスト除去工程と、を有
することを特徴とする回路部材の製造方法。5. A metal layer forming step of forming a metal layer on at least one surface of a conductive substrate with a material having lower etching workability than the conductive substrate, and both surfaces of the conductive substrate on which the metal layer is formed. Forming a resist pattern in a predetermined shape, etching the metal layer and the conductive substrate using the resist pattern as a corrosion-resistant film, and forming an outer frame member and the outer frame so as to be independent from each other via connection leads. A plurality of terminal portions connected to the member, an etching step of forming a die pad connected to the outer frame member via connection leads and having a concave portion on at least one surface, and a resist removing step of removing a resist pattern, A method for manufacturing a circuit member, comprising: 【請求項６】 前記エッチング工程と前記レジスト除去
工程との間に、露出している前記端子部の側面部と、前
記ダイパッドの側面部および凹部内表面と、前記金属層
の側端面とに、めっき層を形成するめっき工程を有する
ことを特徴とする請求項５に記載の回路部材の製造方
法。6. Between the etching step and the resist removing step, the exposed side surface of the terminal portion, the side surface of the die pad and the inner surface of the recess, and the side end surface of the metal layer, The method for manufacturing a circuit member according to claim 5, further comprising a plating step of forming a plating layer. 【請求項７】 前記レジスト除去工程の後に、露出して
いる前記端子部の側面部と、前記ダイパッドの側面部お
よび凹部内表面と、前記金属層とに、めっき層を形成す
るめっき工程を有することを特徴とする請求項５に記載
の回路部材の製造方法。7. A plating step of forming a plating layer on the exposed side surface of the terminal portion, the side surface portion of the die pad and the inner surface of the recess, and the metal layer after the resist removing process. The method for manufacturing a circuit member according to claim 5, wherein 【請求項８】 前記金属層形成工程において、金属層を
Ｎｉ、Ｓｎ、Ａｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕおよ
びその合金のいずれかからなる単層、あるいは、２種以
上の組み合わせの多層として形成することを特徴とする
請求項５乃至請求項７のいずれかに記載の回路部材の製
造方法。8. In the metal layer forming step, the metal layer is a single layer made of any one of Ni, Sn, Ag, Pd, Au, Pt, Rh, Ru, and an alloy thereof, or a multilayer of two or more kinds. The method for manufacturing a circuit member according to claim 5, wherein the circuit member is formed as: 【請求項９】 前記めっき工程において、めっき層をＣ
ｕ、Ｎｉ、Ｓｎ、Ａｇ、Ｐｄ、Ａｕ、Ｐｔ、Ｒｈ、Ｒｕ
およびその合金のいずれかからなる単層、あるいは、２
種以上の組み合わせの多層として形成することを特徴と
する請求項６乃至請求項８のいずれかに記載の回路部材
の製造方法。9. In the plating step, the plating layer is formed of C
u, Ni, Sn, Ag, Pd, Au, Pt, Rh, Ru
And a single layer of any of its alloys, or 2
9. The method for manufacturing a circuit member according to claim 6, wherein the circuit member is formed as a multilayer of a combination of more than one kind.
JP10321313A 1998-10-26 1998-10-26 Circuit member for resin-sealing semiconductor device and manufacture thereof Pending JP2000133763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10321313A JP2000133763A (en) 1998-10-26 1998-10-26 Circuit member for resin-sealing semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10321313A JP2000133763A (en) 1998-10-26 1998-10-26 Circuit member for resin-sealing semiconductor device and manufacture thereof

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JP2006108279A (en) * 2004-10-04 2006-04-20 Matsushita Electric Ind Co Ltd Lead frame and its manufacturing method
JP2006269903A (en) * 2005-03-25 2006-10-05 Shinko Electric Ind Co Ltd Lead frame for semiconductor device
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JP2009302209A (en) * 2008-06-11 2009-12-24 Nec Electronics Corp Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device
JP2011114223A (en) * 2009-11-27 2011-06-09 Hitachi Chem Co Ltd Surface treatment method of semiconductor-mounting conductive base material, conductive base material formed by using the same, and semiconductor package
JP2016046488A (en) * 2014-08-26 2016-04-04 Ｓｈマテリアル株式会社 Lead frame and manufacturing method of the same
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JP2004063742A (en) * 2002-07-29 2004-02-26 Hitachi Chem Co Ltd Wiring board, semiconductor package and method for manufacturing them
CN1331224C (en) * 2002-12-06 2007-08-08 三菱电机株式会社 Resin packaging semiconductor device
JP2006108279A (en) * 2004-10-04 2006-04-20 Matsushita Electric Ind Co Ltd Lead frame and its manufacturing method
JP2006269903A (en) * 2005-03-25 2006-10-05 Shinko Electric Ind Co Ltd Lead frame for semiconductor device
JP2009302209A (en) * 2008-06-11 2009-12-24 Nec Electronics Corp Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device
KR101611911B1 (en) * 2009-03-10 2016-04-12 해성디에스 주식회사 Method of manufacturing lead frame
JP2011114223A (en) * 2009-11-27 2011-06-09 Hitachi Chem Co Ltd Surface treatment method of semiconductor-mounting conductive base material, conductive base material formed by using the same, and semiconductor package
CN106575646A (en) * 2014-08-26 2017-04-19 友立材料株式会社 Lead frame and production method therefor
JP2016046488A (en) * 2014-08-26 2016-04-04 Ｓｈマテリアル株式会社 Lead frame and manufacturing method of the same
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KR102333434B1 (en) * 2014-08-26 2021-11-30 오쿠치 마테리얼스 가부시키가이샤 Lead frame and production method therefor
JP2017076764A (en) * 2015-10-16 2017-04-20 新光電気工業株式会社 Lead frame, manufacturing method therefor, and semiconductor device
CN107068643A (en) * 2015-10-16 2017-08-18 新光电气工业株式会社 Lead frame and its manufacture method, semiconductor device
CN107068643B (en) * 2015-10-16 2021-12-14 新光电气工业株式会社 Lead frame, method of manufacturing the same, and semiconductor device
JP2017092060A (en) * 2015-11-02 2017-05-25 Ｓｈマテリアル株式会社 Lead frame and method of manufacturing the same
JP2017092186A (en) * 2015-11-06 2017-05-25 Ｓｈマテリアル株式会社 Method of manufacturing lead frame
JP2018056165A (en) * 2016-09-26 2018-04-05 株式会社ジェイデバイス Semiconductor device and semiconductor device manufacturing method
JP2021170679A (en) * 2016-09-26 2021-10-28 株式会社アムコー・テクノロジー・ジャパン Semiconductor device
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