CN116759321A - Semiconductor chip bonding pad, manufacturing method thereof and chip packaging method - Google Patents
Semiconductor chip bonding pad, manufacturing method thereof and chip packaging method Download PDFInfo
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- CN116759321A CN116759321A CN202311053433.9A CN202311053433A CN116759321A CN 116759321 A CN116759321 A CN 116759321A CN 202311053433 A CN202311053433 A CN 202311053433A CN 116759321 A CN116759321 A CN 116759321A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
The application relates to the technical field of semiconductor chips, in particular to a semiconductor chip bonding pad, a manufacturing method thereof and a chip packaging method, wherein the manufacturing method of the semiconductor chip bonding pad comprises the following steps: s11, forming a patterned mask on a bonding pad of a semiconductor chip; s12, etching the bonding pad based on a wet etching process and a patterned mask to form a groove on the bonding pad, wherein the area of an opening of the groove is smaller than the largest cross-sectional area in the groove; s13, filling the grooves based on a ball implantation process to form convex points covering the grooves; the manufacturing method of the semiconductor chip bonding pad can effectively solve the problem that the bonding pad and the bump are reduced after the chip is used for a long time or subjected to external stress due to the fact that the bump is formed on the surface of the bonding pad of the chip in the prior art, and therefore the reliability problems of poor stability, poor electrical contact, falling off of the chip from a packaging substrate, chip failure and the like due to the fact that the bonding pad and the bump are reduced in adhesion are effectively solved.
Description
Technical Field
The application relates to the technical field of semiconductor chips, in particular to a semiconductor chip bonding pad, a manufacturing method thereof and a chip packaging method.
Background
In the field of semiconductor chip packaging technology, the packaging processes include ball contact (BGA) processes, flip chip (Flip-chip) processes, dual in-line package (DIP) processes, and the like. The flip chip process is one of the mainstream packaging processes in the semiconductor chip packaging technology field, because of its advantages such as excellent electrothermal properties and reduced package size.
The flip chip process comprises the following steps: bumps (a in fig. 1 and 2) are formed on pads (pad, b in fig. 1 and 2) of a chip (c in fig. 2) based on a ball mounting process, and then the chip is flipped over and soldered to a package substrate (d in fig. 1 and 2). The existing flip chip technology only forms the salient points on the surface of the bonding pads of the chip, and the adhesiveness between the bonding pads and the salient points gradually decreases along with the increase of the service time of the chip, so that the existing flip chip technology has the reliability problems of poor stability of the salient points, poor electrical contact, falling off of the chip from the packaging substrate, chip failure and the like due to the fact that the adhesiveness between the bonding pads and the salient points decreases after the chip is used for a long time or subjected to external stress.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide a semiconductor chip bonding pad, a manufacturing method thereof and a chip packaging method, which can effectively solve the problems of poor bump stability, poor electrical contact, falling off of a chip from a packaging substrate, chip failure and the like caused by the fact that the bonding pad is used for a long time or the adhesion between the bonding pad and the bump is reduced after external stress is applied to the chip because the bonding pad is formed on the surface of the bonding pad of the chip in the prior art.
In a first aspect, the present application provides a method for manufacturing a semiconductor chip pad, comprising the steps of:
s11, forming a patterned mask on a bonding pad of a semiconductor chip;
s12, etching the bonding pad based on a wet etching process and a patterned mask to form a groove on the bonding pad, wherein the area of an opening of the groove is smaller than the largest cross-sectional area in the groove;
s13, filling the grooves based on a ball implantation process to form convex points covering the grooves.
According to the manufacturing method of the semiconductor chip bonding pad, the patterned mask is firstly formed on the bonding pad of the semiconductor chip, then the groove is formed on the bonding pad based on the wet etching process and the patterned mask, finally the bump covering the groove is formed based on the ball implanting process, when the bump is stressed in the horizontal direction, the bump covers the groove, namely the bump is mutually abutted against the side wall of the groove, the side wall of the groove can resist the stress in the horizontal direction, so that the groove can resist the bump to move transversely, when the bump is stressed in the vertical direction, the opening area of the groove is smaller than the largest cross section area in the groove, the bottom and the opening of the groove can resist the stress in the vertical direction, and the opening of the groove can resist the bump to drop, namely the manufacturing method can prevent the bump from moving longitudinally, namely the bump can be prevented from moving transversely or longitudinally by forming the groove with the opening area smaller than the largest cross section area in the bonding pad, even if the chip is used for a long time or is stressed externally, the bump can not drop, and therefore the problem that the bump drops due to the fact that the chip is formed on the surface of the bonding pad of the chip in the prior art is poor in contact with the bonding pad or poor in adhesion with the bonding pad and poor in electrical stability is solved.
Optionally, the patterned mask is a patterned photoresist mask, and the steps between step S12 and step S13 further include:
s14, removing the patterned mask.
Optionally, the area of the bump covering the pad surface is larger than the area of the opening of the recess.
Because the coverage area of the convex points in the technical scheme is larger than the area of the opening of the groove, the technical scheme is equivalent to forming the convex points clamped by internal and external fastening on the bonding pad, thereby effectively increasing the contact area between the convex points and the packaging substrate in the subsequent packaging process and further effectively improving the adhesiveness between the convex points and the packaging substrate.
Optionally, the patterned mask is a hard mask blocking layer, and an etching rate of the etchant on the hard mask blocking layer is smaller than an etching rate of the etchant on the bonding pad.
When the bump receives the stress of horizontal direction, because the bump covers the through-hole of hard mask shielding layer, the bump is contradicted with the lateral wall of through-hole each other, and the lateral wall of through-hole can resist the stress of this horizontal direction, consequently the through-hole on the graphical mask can block bump lateral shifting, and the hard mask shielding layer of this technical scheme is equivalent to the additional strengthening of recess promptly to further prevent taking place the bump condition that drops after the chip uses for a long time or receives external stress.
Optionally, the hard mask shielding layer is made of a dielectric material or a metal material.
Optionally, the pad is made of aluminum copper alloy, the hard mask shielding layer is made of tungsten, and the etchant used in etching the pad is sulfuric acid solution with concentration less than 55%.
In a second aspect, the present application also provides a chip packaging method, which includes the following steps:
s21, forming a patterned mask on a bonding pad of a semiconductor chip;
s22, etching the bonding pad based on a wet etching process and a patterned mask to form a groove on the bonding pad, wherein the area of an opening of the groove is smaller than the largest cross-sectional area in the groove;
s23, filling the grooves based on a ball implantation process to form convex points covering the grooves;
s24, welding the semiconductor chip comprising the convex points covering the grooves on the packaging substrate based on the flip chip technology.
According to the chip packaging method provided by the application, the patterned mask is firstly formed on the bonding pad of the semiconductor chip, then the groove is formed on the bonding pad based on the wet etching process and the patterned mask, finally the bump covering the groove is formed based on the ball mounting process and the semiconductor chip including the bump covering the groove is welded on the packaging substrate based on the flip chip process, when the bump is stressed in the horizontal direction, the bump covering the groove, namely the bump is mutually abutted against the side wall of the groove, the side wall of the groove can resist the stress in the horizontal direction, so that the groove can resist the bump to move transversely, when the bump is stressed in the vertical direction, the opening area of the groove is smaller than the largest cross section area in the groove, the bottom and the opening of the groove can resist the stress in the vertical direction, and the opening of the groove can resist the bump to fall off, namely the bump can be prevented from moving longitudinally by forming the groove with the opening area smaller than the largest cross section area in the bonding pad, and the bump covering the groove can be prevented from moving transversely or longitudinally, even if the chip is stressed in the horizontal direction, the bump is not collided with the side wall of the bump, the bump can not fall off, and the chip can not fall off due to poor electrical adhesion with the bonding pad or the chip due to poor electrical adhesion caused by the prior art after the chip is used, and the chip is effectively reduced due to the poor adhesion with the chip.
In a third aspect, the present application further provides a semiconductor chip pad, the semiconductor chip pad including a groove and a bump covering the groove, an opening of the groove having an area smaller than a maximum cross-sectional area in the groove, an bottom of the bump being filled in the groove and covering the groove.
The semiconductor chip bonding pad comprises the groove and the salient points covered on the groove, when the salient points are stressed in the horizontal direction, the salient points cover the groove, namely the salient points are mutually abutted against the side walls of the groove, the side walls of the groove can resist the stress in the horizontal direction, so that the groove can resist the transverse movement of the salient points, when the salient points are stressed in the vertical direction, the bottom and the opening of the groove can resist the stress in the vertical direction, and the opening of the groove can resist the falling of the salient points, so that the groove can resist the longitudinal movement of the salient points, namely, the semiconductor chip bonding pad can prevent the salient points from moving in the transverse direction or the longitudinal direction by forming the groove with the opening area smaller than the maximum internal cross section area on the bonding pad, even if the chip is used for a long time or is stressed by the external stress, the situation that the salient points fall off can not occur, so that the bonding pad and the chip are used for a long time or the bonding pad are stressed by the external stress is only formed on the bonding pad surface of the chip in the prior art, and the problem that the bonding pad and the bonding pad fall off is poor in electrical stability and the chip are solved, and the problem of poor electrical contact stability and reliability are caused by the chip.
Optionally, the surface of the semiconductor chip bonding pad is covered with a hard mask shielding layer, the hard mask shielding layer is provided with a through hole exposing the groove, and the area of the through hole of the hard mask shielding layer is smaller than the area of the opening of the groove.
When the bump receives the stress of horizontal direction, because bump cover through-hole, the bump is contradicted with the lateral wall of through-hole each other, the lateral wall of through-hole can resist this horizontal direction's stress, consequently, recess on the graphical mask can block bump lateral shifting, and receive the stress of vertical direction at the bump, the through-hole of stereoplasm mask shielding layer can resist the stress of vertical direction, and because the area of the through-hole of stereoplasm mask shielding layer is less than the open-ended area of recess, even the opening of recess can't block the bump and drop, the stereoplasm mask shielding layer of this technical scheme also can block the bump and drop, therefore the stereoplasm mask shielding layer of this technical scheme is equivalent to the additional strengthening of recess, thereby further prevent taking place the bump condition that drops after the chip uses for a long time or receives external stress.
Optionally, the groove includes an expansion portion and a contraction portion provided in a direction from an opening of the groove to a bottom of the groove.
According to the semiconductor chip bonding pad, the manufacturing method and the chip packaging method thereof provided by the application, the patterned mask is firstly formed on the bonding pad of the semiconductor chip, then the groove is formed on the bonding pad based on the wet etching process and the patterned mask, and finally the bump covering the groove is formed based on the ball implanting process.
Drawings
Fig. 1 is a schematic diagram of a conventional pad and bump structure.
Fig. 2 is a schematic structural diagram of a package structure obtained by a conventional flip-chip process.
Fig. 3 is a flowchart of a method for manufacturing a semiconductor chip pad according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a method for manufacturing a semiconductor chip pad when the patterned mask is a patterned photoresist mask according to an embodiment of the present application.
Fig. 5 is a schematic top view of a pad and bump obtained by the method for manufacturing a semiconductor chip pad of fig. 4.
Fig. 6 is a schematic diagram of a method for manufacturing a semiconductor chip pad when the patterned mask is a hard mask shielding layer according to an embodiment of the present application.
Fig. 7 is a flowchart of a chip packaging method according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a chip packaging method when the patterned mask is a patterned photoresist mask according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a chip packaging method when the patterned mask is a hard mask shielding layer according to an embodiment of the present application.
Reference numerals: 1. a bonding pad; 2. patterning the mask; 3. a groove; 4. a bump; 5. a semiconductor chip; 6. and packaging the substrate.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, as shown in fig. 3-6, the present application provides a method for manufacturing a semiconductor chip pad, which includes the following steps:
s11, forming a patterned mask 2 on a bonding pad 1 of a semiconductor chip 5;
s12, etching the bonding pad 1 based on a wet etching process and the patterned mask 2 to form a groove 3 on the bonding pad 1, wherein the area of an opening of the groove 3 is smaller than the largest cross-sectional area in the groove 3;
and S13, filling the grooves 3 based on a ball implantation process to form the convex points 4 covering the grooves 3.
Wherein the patterned mask 2 of step S11 is a mask having a predetermined pattern, it should be understood that, since the recess 3 needs to be formed on the pad 1 based on the patterned mask 2 in step S12, the patterned mask 2 of step S11 is a mask including at least one opening, i.e. the predetermined pattern is an opening. Step S11 forms a patterned mask 2 (refer to a in fig. 4 or fig. 6) on the pad 1 of the semiconductor chip 5 based on the existing mask manufacturing process.
The wet etching process of step S12 is a process of peeling off the substance to be etched by using a chemical reaction between the etchant and the substance to be etched, specifically, the substance to be etched of this embodiment is the pad 1 where the groove 3 is located (refer to C in fig. 4 or B in fig. 6). The existing wet etching process can be divided into a patterned wet etching process and a non-patterned wet etching process, and since the patterned mask 2 plays a role in defining the area where the etched substance is located during etching, and the patterned wet etching process defines the area of the surface material to be etched by using the masking layer, step S12 belongs to the patterned wet etching process. Step S12 etches the pad 1 based on the wet etching process and the patterned mask 2 to form a groove 3 on the pad 1, specifically, the area of the opening of the groove 3 is smaller than the largest cross-sectional area in the groove 3, and the groove 3 may be a structure with a changed cross-sectional area such as a prismatic table, a spherical shape, a truncated cone shape, etc. It should be understood that in the wet etching process, since the wet etching process has an isotropic characteristic, when the etchant contacts the pad 1 through the opening in the patterned mask 2, the etchant etches the pad 1 in all directions and the etching rate in all directions is the same, so that the opening area of the groove 3 formed in the pad 1 in step S12 is smaller than the maximum cross-sectional area in the groove 3.
The ball mounting process of step S13 may be a conventional solder paste printing ball mounting process, a laser ball mounting process, or the like capable of forming the bump 4 on the chip pad 1, and the bump 4 of this embodiment is made of a metal material, and the bump 4 of this embodiment is preferably made of any one or more of gold, tin, and copper, because the bump 4 of this embodiment is formed by filling the groove 3 on the pad 1 based on the ball mounting process to form the bump 4 (see D in fig. 4 or C in fig. 6). It should be understood that after the execution of step S13 is completed, the recess 3 is filled with metal, and the bump 4 of this embodiment is a protruding portion having an opening that is exposed and completely covers the recess 3.
The working principle of the embodiment is as follows: according to the manufacturing method of the semiconductor chip bonding pad, the patterned mask 2 is firstly formed on the bonding pad 1 of the semiconductor chip 5, then the groove 3 is formed on the bonding pad 1 based on the wet etching process and the patterned mask 2, finally the bump 4 covering the groove 3 is formed based on the ball implanting process, when the bump 4 is stressed in the horizontal direction, the bump 4 covers the groove 3, namely, the bump 4 is mutually abutted with the side wall of the groove 3, the side wall of the groove 3 can resist the stress in the horizontal direction, the groove 3 can resist the bump 4 from transversely moving, when the bump 4 is stressed in the vertical direction, the opening area of the groove 3 is smaller than the largest cross section area in the groove 3, the bottom and the opening of the groove 3 can resist the stress in the vertical direction, and the opening of the groove 3 can resist the bump 4 from longitudinally moving, namely, when the bump 4 is stressed in the horizontal direction, the groove 3 is covered by the bump 4, namely, the bump 4 is formed on the bonding pad 1, namely, the bump 4 is prevented from transversely or longitudinally moving, the bump 4 can resist the stress in the horizontal direction, the chip is prevented from falling off, and the chip is prevented from being electrically and the bonding pad 4 is prevented from falling off due to poor in the adhesion between the chip 1 and the chip 1, and the chip is effectively prevented from falling off due to poor in the adhesion due to the fact that the chip is not stressed on the surface of the bonding pad 1.
In some embodiments, the patterned mask 2 is a patterned photoresist mask, and the steps between step S12 and step S13 further include:
s14, removing the patterned mask 2.
The patterned mask 2 in this embodiment is a patterned photoresist mask, and specifically, the forming process (i.e. step S11) of the patterned mask 2 in this embodiment may be that the photoresist is first spin-coated and baked on the pad 1 of the semiconductor chip 5 to form a photoresist layer on the pad 1, and then the photoresist layer is exposed and developed by a person or by using an existing developing system based on a mask plate with a preset pattern to form the patterned mask 2. Specifically, in step S12 of this embodiment, a corresponding etchant is required to be configured according to the material of the pad 1, and taking the material of the pad 1 as an example of an aluminum copper alloy, the etchant of this embodiment is a mixed solution including phosphoric acid, nitric acid and acetic acid. Step S14 removes the patterned mask 2 from the pad 1 using the existing photoresist removal method (refer to C in fig. 4). It should be understood that if the patterned mask 2 is not removed, the metal filled in step S13 will have a transition narrowed region to form the bump 4 with an i-shaped cross section, and the i-shaped bump 4 has better stability, i.e. the retention of the patterned mask 2 can improve the stability of the bump 4; if the patterned mask 2 is removed, the distance between the semiconductor chip 5 and the package substrate 6 is minimized to reduce the package volume of the semiconductor chip 5, i.e., removing the patterned mask 2 can reduce the package volume of the semiconductor chip 5.
In some embodiments, the area of the bump 4 covering the surface of the pad 1 is larger than the area of the opening of the recess 3. Step S13 is based on filling metal into the groove 3 by ball-implanting process, after the groove 3 is filled with metal, the metal overflows from the opening of the groove 3 to the surface of the bonding pad 1, and the width of the overflowed metal is larger than the width of the opening of the groove 3. Since the coverage area of the bump 4 in this embodiment is larger than the area of the opening of the recess 3, this embodiment is equivalent to forming the bump 4 clamped by fastening inside and outside on the pad 1, so that in the subsequent packaging process, the contact area between the bump 4 and the package substrate 6 is effectively increased, and the adhesion between the bump 4 and the package substrate 6 is effectively improved. Preferably, the maximum cross-sectional area of the bump 4 outside the groove 3 in this embodiment is larger than the maximum cross-sectional area inside the groove 3, i.e. the width of the overflowed metal is larger than the maximum width inside the groove.
In some embodiments, patterned mask 2 is a hard mask blocking layer, and the etching rate of the etchant on the hard mask blocking layer is much smaller than the etching rate of the etchant on pad 1. In this embodiment, the hard mask shielding layer is used as the patterned mask 2, and since the etching rate of the hard etchant on the hard mask shielding layer is far smaller than the etching rate of the etchant on the pad 1, the etchant will hardly etch the hard mask shielding layer and will etch the pad 1 in a large amount when executing step S12, so that the area of the through hole of the hard mask shielding layer is smaller than the area of the opening of the groove 3. Since the hard mask blocking layer of this embodiment is not removed after the execution of step S12 is completed and the hard mask blocking layer has a via hole thereon for defining the region where the recess 3 is located, step S13 of this embodiment is to fill the recess 3 and the via hole based on the ball-mounting process to form the bump 4 covering the recess 3 and the via hole. When the bump 4 is stressed in the horizontal direction, the bump 4 covers the through hole of the hard mask shielding layer, that is, the bump 4 is mutually abutted against the side wall of the through hole, and the side wall of the through hole can resist the stress in the horizontal direction, so that the through hole on the patterned mask 2 can block the bump 4 from moving transversely, that is, the hard mask shielding layer in the embodiment corresponds to the reinforcing structure of the groove 3, so that the bump 4 is further prevented from falling off after the chip is used for a long time or subjected to external stress. Preferably, the area of the through hole in this embodiment is smaller than the area of the opening of the recess 3, the stress in the vertical direction is applied to the bump 4, the opening of the recess 3 and the through hole of the hard mask shielding layer can resist the stress in the vertical direction, and the opening of the recess 3 and the through hole of the hard mask shielding layer can block the bump 4 from falling off, so this embodiment can further prevent the bump 4 from falling off after the chip is used for a long time or is subjected to external stress, and it should be understood that, since the area of the through hole of the hard mask shielding layer is smaller than the area of the opening of the recess 3, even if the opening of the recess 3 cannot block the bump 4 from falling off, the hard mask shielding layer in this embodiment can block the bump 4 from falling off. Preferably, the ratio of the depth of the recess 3 to the thickness of the hard mask blocking layer in this embodiment is 1:0.5-1:1, the ratio of the depth of the groove 3 to the thickness of the hard mask shielding layer is 1: and when the ratio of the hard mask to the bump is 0.5-1:1, the through holes of the hard mask shielding layer are filled with enough metal, so that the structural stability of the bump is effectively improved.
In some embodiments, the hard mask shielding layer is made of a dielectric material or a metal material. The material of the hard mask shielding layer in this embodiment may be a dielectric material (such as silicon dioxide and silicon nitride), and the material of the hard mask shielding layer in this embodiment may also be a metal material.
In some embodiments, the material of the pad 1 is aluminum copper alloy, the material of the hard mask shielding layer is tungsten, and the etchant used for etching the pad 1 is sulfuric acid solution with concentration less than 55%.
In some embodiments, the cross section of the groove 3 is circular, the ratio of the depth of the groove 3 to the thickness of the pad 1 is 2:5-3:5, and the ratio of the diameter of the opening of the groove 3 to the length of the pad is 3:10-9:20. The cross section of the groove 3 in this embodiment is circular, since the bump 4 spreads along all directions after soldering, and when the ratio of the depth of the groove 3 to the thickness of the pad 1 is 2:5-3:5, and the ratio of the diameter of the opening of the groove 3 to the length of the pad is 3:10-9:20, the soldering area of the semiconductor chip 5 and the package substrate 6 is large enough, and the situation that the metal of the bump 4 overflows out of the pad 1 does not occur, so this embodiment is equivalent to avoiding the situation that the metal is wasted due to the metal overflowing out of the pad on the premise of ensuring the structural stability of the soldering structure.
In the pull-push force test, the push-pull force of the salient point formed after the ball planting process in the prior art is generally in the range of 30g-40g, and the push-pull force of the salient point formed after the ball planting process can reach more than 42.5 g.
As can be seen from the above, according to the method for manufacturing the semiconductor chip bonding pad provided by the application, the patterned mask 2 is firstly formed on the bonding pad 1 of the semiconductor chip 5, then the groove 3 is formed on the bonding pad 1 based on the wet etching process and the patterned mask 2, and finally the bump 4 covering the groove 3 is formed based on the ball implanting process, when the bump 4 is stressed in the horizontal direction, the bump 4 covers the groove 3, namely, the bump 4 is mutually abutted against the side wall of the groove 3, the side wall of the groove 3 can resist the stress in the horizontal direction, so that the groove 3 can resist the bump 4 from moving transversely, when the bump 4 is stressed in the vertical direction, the bottom and the opening of the groove 3 can resist the stress in the vertical direction, and the opening of the groove 3 can resist the bump 4 from falling off, namely, when the bump 4 is stressed in the horizontal direction, the bonding pad 1 is stressed in the horizontal direction, the bump 4 covers the groove 3, the bump 4 can be prevented from moving transversely or longitudinally, the chip can not fall off, and the chip 4 can not fall off due to the poor adhesion between the chip 1 and the chip 4 and the chip 1 due to poor electrical adhesion caused by the fact that the chip is not stressed on the surface of the prior art, and the chip 1 is not stressed on the chip 1.
In a second aspect, as shown in fig. 7-9, the present application further provides a chip packaging method, which includes the following steps:
s21, forming a patterned mask 2 on the pad 1 of the semiconductor chip 5 (refer to a in fig. 8 or 9);
s22, etching the bonding pad 1 based on a wet etching process and the patterned mask 2 to form a groove 3 on the bonding pad 1, wherein the area of an opening of the groove 3 is smaller than the largest cross-sectional area in the groove 3 (refer to C in FIG. 8 or B in FIG. 9);
s23, filling the recess 3 based on the ball-mounting process to form a bump 4 (refer to D in fig. 8 or C in fig. 9) covering the recess 3;
s24, the semiconductor chip 5 including the bump 4 covering the groove 3 is soldered on the package substrate 6 based on the flip-chip process (refer to E in fig. 8 or D in fig. 9).
The steps S21-S23 of this embodiment are the same as the steps S11-S13 of the foregoing embodiment, that is, the chip packaging method of this embodiment applies the semiconductor chip pad manufacturing method provided in the foregoing first aspect, and the working principles of the steps S21-S23 are the same as the working principles of the steps S11-S13 of the foregoing embodiment, which are not discussed in detail herein. The specific workflow of step S24 is: the semiconductor chip 5 including the bumps 4 covering the grooves 3 is flipped over, and the semiconductor chip 5 is soldered to the package substrate 6. It should be understood that after the semiconductor chip 5 is bonded to the package substrate 6, the bumps 4 may spread out around.
In some embodiments, the patterned mask 2 is a patterned photoresist mask, and the steps between step S22 and step S23 further include:
s25, the patterned mask 2 is removed (refer to C in fig. 8).
The chip packaging method provided by the application comprises the steps of firstly forming a patterned mask 2 on a bonding pad 1 of a semiconductor chip 5, then forming a groove 3 on the bonding pad 1 based on a wet etching process and the patterned mask 2, finally forming a bump 4 covering the groove 3 based on a ball-planting process and bonding the semiconductor chip 5 comprising the bump 4 covering the groove 3 on a packaging substrate 6 based on a flip chip process, when the bump 4 is stressed in the horizontal direction, the bump 4 covers the groove 3, namely the bump 4 is mutually abutted with the side wall of the groove 3, the side wall of the groove 3 can resist the stress in the horizontal direction, so that the groove 3 can resist the lateral movement of the bump 4, and when the bump 4 is stressed in the vertical direction, the bottom and the opening of the groove 3 can resist the stress in the vertical direction because the opening area of the groove 3 is smaller than the maximum cross section area in the groove 3, the opening of the groove 3 can prevent the bump 4 from falling off, so the groove 3 can prevent the bump 4 from moving longitudinally, namely, the packaging method can prevent the bump 4 from moving transversely or longitudinally by forming the groove 3 with an opening area smaller than the largest internal cross-sectional area on the bonding pad 1 and covering the groove 3 with the bump 4, even if the chip is used for a long time or subjected to external stress, the packaging method can not cause the bump 4 to fall off, thereby effectively solving the problems of long-time use of the chip or reduced adhesion between the bonding pad 1 and the bump 4 after the chip is only used for a long time or subjected to external stress due to the bump 4 formed on the bonding pad 1 of the chip in the prior art, and further effectively solving the problems of poor stability, poor electrical contact and falling off of the chip from the packaging substrate 6 due to the reduced adhesion between the bonding pad 1 and the bump 4, chip failure and other reliability problems.
In a third aspect, the present application also provides a semiconductor chip pad, the semiconductor chip pad including a groove 3 and a bump 4 covering the groove 3, an opening of the groove 3 having an area smaller than a maximum cross-sectional area in the groove 3, an bottom of the bump 4 being filled in the groove 3 and covering the groove 3.
The embodiment of the application provides a semiconductor chip bonding pad, which is preferably manufactured by the manufacturing method of the semiconductor chip bonding pad provided by the first aspect.
The working principle of the embodiment is as follows: the semiconductor chip bonding pad provided by the application comprises the groove 3 and the convex point 4 covered on the groove 3, when the convex point 4 is stressed in the horizontal direction, the convex point 4 covers the groove 3, namely, the convex point 4 is mutually abutted against the side wall of the groove 3, the side wall of the groove 3 can resist the stress in the horizontal direction, so that the groove 3 can resist the transverse movement of the convex point 4, when the convex point 4 is stressed in the vertical direction, the opening area of the groove 3 is smaller than the largest cross section area in the groove 3, the bottom and the opening of the groove 3 can resist the stress in the vertical direction, and the opening of the groove 3 can resist the falling of the convex point 4, so that the groove 3 can resist the longitudinal movement of the convex point 4, namely, the semiconductor chip bonding pad can prevent the convex point 4 from moving in the transverse direction or the longitudinal direction by forming the groove 3 with the opening area smaller than the largest cross section area in the inside on the bonding pad 1, even if the chip is used for a long time or is stressed externally, the situation of the convex point 4 can not happen, thus the situation that the convex point 4 is effectively solved, the problem that the bonding pad 1 falls off due to the prior art, the bonding pad 1 is not used or the chip 4 falls off, the problem of poor electrical adhesion is caused by the poor electrical adhesion, and the bonding pad 4 is caused by the poor electrical adhesion, and the problem is solved.
In some embodiments, the surface of the semiconductor chip pad is covered with a hard mask shielding layer, the hard mask shielding layer is provided with a through hole exposing the groove 3, and the area of the through hole of the hard mask shielding layer is smaller than the area of the opening of the groove 3. When bump 4 receives the stress of horizontal direction, because bump 4 covers the through-hole, i.e. bump 4 and the lateral wall of through-hole are contradicted each other, the lateral wall of through-hole can resist this horizontal direction's stress, consequently, the through-hole of hard mask shielding layer can block bump 4 lateral shifting, and receive the stress of vertical direction at bump 4, the through-hole of hard mask shielding layer can resist the stress of vertical direction, and because the area of the through-hole of hard mask shielding layer is less than the area of recess 3, even if the opening of recess 3 can't block bump 4 to drop, the hard mask shielding layer of this embodiment also can block bump 4 to drop, therefore the hard mask shielding layer of this embodiment is equivalent to the additional strengthening of recess 3, thereby further prevent the condition that bump 4 drops after the chip uses for a long time or receives external stress.
In some embodiments, the groove 3 includes an expansion and a contraction disposed in a direction from an opening of the groove 3 to a bottom of the groove 3. Since the groove 3 includes the expanded portion and the contracted portion provided in the direction from the opening of the groove 3 to the bottom of the groove 3, the cross-sectional area of the groove 3 of this embodiment gradually decreases toward the opening or bottom of the groove 3 along the center of the groove 3, i.e., the cross-sectional area at the boundary of the expanded portion and the contracted portion is maximized. And since the minimum distance of the expansion portion from the opening of the groove 3 is smaller than the minimum distance of the contraction portion from the opening of the groove 3, the expansion portion is closer to the surface of the pad 1 than the contraction portion. Preferably, the expansion portion and the contraction portion of this embodiment smoothly transition.
As can be seen from the above, the semiconductor chip bonding pad provided by the application comprises the groove 3 and the bump 4 covered on the groove 3, when the bump 4 is stressed in the horizontal direction, the bump 4 covers the groove 3, that is, the bump 4 is mutually abutted against the side wall of the groove 3, so that the groove 3 can block the bump 4 from moving transversely, when the bump 4 is stressed in the vertical direction, the opening area of the groove 3 is smaller than the largest cross-sectional area in the groove 3, the bottom and the opening of the groove 3 can resist the stress in the vertical direction, and the opening of the groove 3 can block the bump 4 from falling off, so that the groove 3 can block the bump 4 from moving longitudinally, that is, the semiconductor chip bonding pad can prevent the bump 4 from moving transversely or longitudinally by forming the groove 3 with the opening area smaller than the largest cross-sectional area inside on the bonding pad 1, even if the chip is used for a long time or is stressed externally, the semiconductor chip bonding pad can not generate the situation that the bump 4 falls off, so that the chip bonding pad 1 is not contacted with the chip 1 for a long time, and the problem of poor adhesion is solved, and the chip bonding pad 4 is not lost, and the problem of poor electrical adhesion is caused by the chip 1 is solved, and the problem of the chip bonding pad is not being well-being sealed by the chip 4 after the chip is formed by the chip 1.
As can be seen from the above, according to the semiconductor chip bonding pad, the manufacturing method and the chip packaging method thereof provided by the application, the patterned mask 2 is firstly formed on the bonding pad 1 of the semiconductor chip 5, then the groove 3 is formed on the bonding pad 1 based on the wet etching process and the patterned mask 2, and finally the bump 4 covering the groove 3 is formed based on the ball implanting process, when the bump 4 is stressed in the horizontal direction, the bump 4 covers the groove 3, namely, the bump 4 is mutually abutted against the side wall of the groove 3, the side wall of the groove 3 can resist the stress in the horizontal direction, so that the groove 3 can resist the bump 4 from moving transversely, when the bump 4 is stressed in the vertical direction, the bottom and the opening of the groove 3 can resist the stress in the vertical direction, and the groove 3 can resist the bump 4 from falling off, namely, the manufacturing method can prevent the bump 4 from moving longitudinally by forming the groove 3 with the opening area smaller than the inner maximum cross section area on the bonding pad 1 and enabling the bump 4 to cover the groove 3, namely, the bump 4 can resist the stress in the horizontal direction or the side wall of the groove 3 from abutting against the side wall of the groove 3, and the chip 4 falls off due to the poor adhesion between the bonding pad 1 and the chip 1 or the chip 1 due to poor adhesion after the chip is exposed to the chip 1, and the chip is not effectively used, and the chip is not stressed, and the chip is not effectively adhered, and the chip is well is prevented from being formed due to the problem due to the chip is due to the fact that the chip is due to the poor adhesion after the chip is due to the fact the surface is exposed to the surface has the poor to the surface has the chip.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. The manufacturing method of the semiconductor chip bonding pad is characterized by comprising the following steps of:
s11, forming a patterned mask on a bonding pad of a semiconductor chip;
s12, etching the bonding pad based on a wet etching process and the patterned mask to form a groove on the bonding pad, wherein the area of an opening of the groove is smaller than the largest cross-sectional area in the groove;
and S13, filling the grooves based on a ball implantation process to form convex points covering the grooves.
2. The method of manufacturing a semiconductor chip pad according to claim 1, wherein the patterned mask is a patterned photoresist mask, and the steps between the step S12 and the step S13 further comprise:
s14, removing the patterned mask.
3. The method of manufacturing a semiconductor die pad according to claim 1, wherein an area of the bump covering the pad surface is larger than an area of an opening of the recess.
4. The method of claim 1, wherein the patterned mask is a hard mask layer, and the etching rate of the etchant on the hard mask layer is substantially less than the etching rate of the etchant on the pad.
5. The method of manufacturing a semiconductor chip pad according to claim 4, wherein the hard mask shielding layer is made of a dielectric material or a metal material.
6. The method of manufacturing a semiconductor chip bonding pad according to claim 4, wherein the bonding pad is made of aluminum-copper alloy, the hard mask shielding layer is made of tungsten, and the etching agent used for etching the bonding pad is sulfuric acid solution with concentration less than 55%.
7. A chip packaging method, characterized in that the chip packaging method comprises the steps of:
s21, forming a patterned mask on a bonding pad of a semiconductor chip;
s22, etching the bonding pad based on a wet etching process and the patterned mask to form a groove on the bonding pad, wherein the area of an opening of the groove is smaller than the largest cross-sectional area in the groove;
s23, filling the grooves based on a ball-planting process to form convex points covering the grooves;
and S24, welding the semiconductor chip comprising the convex points covering the grooves on the packaging substrate based on the flip chip technology.
8. A semiconductor chip bonding pad manufactured by a manufacturing method of the semiconductor chip bonding pad according to any one of claims 1 to 6, wherein the semiconductor chip bonding pad comprises a groove and a bump covering the groove, an opening area of the groove is smaller than a maximum cross-sectional area in the groove, and an bottom of the bump is filled in the groove and covers the groove.
9. The semiconductor die pad of claim 8, wherein the semiconductor die pad surface is covered with a hard mask blocking layer having a via exposing the recess, the via area of the hard mask blocking layer being smaller than the area of the opening of the recess.
10. The semiconductor die pad of claim 8, wherein the recess includes an expansion and a contraction disposed along a direction from the recess opening to the recess bottom.
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