JP4218479B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4218479B2 JP4218479B2 JP2003331873A JP2003331873A JP4218479B2 JP 4218479 B2 JP4218479 B2 JP 4218479B2 JP 2003331873 A JP2003331873 A JP 2003331873A JP 2003331873 A JP2003331873 A JP 2003331873A JP 4218479 B2 JP4218479 B2 JP 4218479B2
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- JP
- Japan
- Prior art keywords
- igbt
- chip
- current
- voltage
- turn
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
Description
(1)IGBTチップの定常オン電流のばらつき
(2)IGBTチップのターンオフ時間(ストレージ時間、フォール時間)のばらつき
(3)IGBTチップユニットのターンオフ可能遮断電流の低下
などが考えられる。
(1)IGBTパックのターンオフ可能遮断電流を増大できる。これはターンオフ能力(RBSOA)が向上したことを意味する。
(2)IGBTチップのターンオフ可能遮断電流を10%以上増大することができる。
(3)IGBTパックのターンオフ能力の向上は、応用の電力変換装置においても、過電流に対する余裕度が増加し、装置故障率が低下すると考えられる。また、応用の電力変換装置によっては、IGBTパック面内の加圧状態のばらつきが大きいことも考えられるので、本発明は、加圧状態のばらつき増大に対するIGBTパックのターンオフ能力低下を低減する。
(4)IGBTチップは従来工程とほぼ同じ工程で製造できる。つまりしきい値を高めるには、pベース層形成のためのボロンイオン注入工程時のイオン注入量を従来より多くするのみの変更であるので、工数も増えず、コストアップにならない。
(5)しきい値を高めることで、IGBTパックのターンオフ能力(RBSOA)、短絡耐量は大幅に増大し、信頼性が向上する。
(6)このしきい値をゲート駆動電圧の0.5倍から0.7倍とするとよい。
2 耐圧構造部
3 ゲートパッド
4 エミッタ電極
5 エミッタ金属端子体
5a アノード金属端子体
6 コレクタ金属端子体
6a カソード金属端子体
7 チップ固定枠
8 エミッタ共通電極板
9 コレクタ共通電極板
10 ダイオードチップ
11 ゲートボンディングワイヤ
12 ゲート外部導出端子
13 位置決めガイド
14 絶縁筒体
20 IGBTパック
21 IGBTチップユニット
21a ダイオードチップユニット
31 n- ドリフト領域
32 pベース領域
33 n+ エミッタ領域
34 ゲート絶縁膜
35 ゲート電極
36 層間絶縁膜
37 n+ バッファ領域
38 p+ コレクタ領域
39 コレクタ電極
Claims (6)
- 複数のMOS制御型半導体チップをパッケージ内に並列接続して配設した半導体装置において、
MOS制御半導体チップを、定格電流で定格オン電圧以下となるゲート駆動電圧で駆動するとき、該チップの主電流の飽和値が定格電流の3倍以下となるように、該チップのゲートしきい値電圧を設定することを特徴とする半導体装置。 - 複数のMOS制御型半導体チップをパッケージ内に並列接続して配設した半導体装置において、
MOS制御半導体チップを、定格接合温度、定格電流で定格オン電圧以下となるゲート駆動電圧で駆動するとき、該チップの主電流の飽和値が定格電流の3倍以下となるように、該チップのゲートしきい値電圧を設定することを特徴とする半導体装置。 - 前記主電流の飽和値が定格電流の2.4倍以下であることを特徴とする請求項1または2に記載の半導体装置。
- 前記ゲートしきい値電圧が、前記ゲート駆動電圧の0.5倍以上で、0.7倍以下であることを特徴とする請求項1または2に記載の半導体装置。
- 前記パッケージが加圧接触型であることを特徴とする請求項1または2に記載の半導体装置。
- 前記MOS制御型半導体チップが、MOSトランジスタチップであることを特徴とする請求項1または2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003331873A JP4218479B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003331873A JP4218479B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005101198A JP2005101198A (ja) | 2005-04-14 |
JP4218479B2 true JP4218479B2 (ja) | 2009-02-04 |
Family
ID=34460402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003331873A Expired - Fee Related JP4218479B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4218479B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107305886B (zh) * | 2016-04-25 | 2024-04-05 | 华北电力大学 | 一种便于串联使用的大功率igbt模块 |
CN112768438B (zh) * | 2019-11-05 | 2022-07-15 | 深圳第三代半导体研究院 | 一种压接式功率模块及其制备方法 |
-
2003
- 2003-09-24 JP JP2003331873A patent/JP4218479B2/ja not_active Expired - Fee Related
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JP2005101198A (ja) | 2005-04-14 |
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