JP4208719B2 - 能動電圧レベルバススイッチ（又はパスゲート）変換器 - Google Patents

能動電圧レベルバススイッチ（又はパスゲート）変換器 Download PDF

Info

Publication number
JP4208719B2
JP4208719B2 JP2003548405A JP2003548405A JP4208719B2 JP 4208719 B2 JP4208719 B2 JP 4208719B2 JP 2003548405 A JP2003548405 A JP 2003548405A JP 2003548405 A JP2003548405 A JP 2003548405A JP 4208719 B2 JP4208719 B2 JP 4208719B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
node
low
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003548405A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005510935A (ja
JP2005510935A5 (enExample
Inventor
クラーク，シーン，エックス
ブーマー，ジェイムス，ビー
Original Assignee
フェアチャイルド セミコンダクター コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by フェアチャイルド セミコンダクター コーポレイション filed Critical フェアチャイルド セミコンダクター コーポレイション
Priority claimed from PCT/US2002/037815 external-priority patent/WO2003047106A1/en
Publication of JP2005510935A publication Critical patent/JP2005510935A/ja
Publication of JP2005510935A5 publication Critical patent/JP2005510935A5/ja
Application granted granted Critical
Publication of JP4208719B2 publication Critical patent/JP4208719B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2003548405A 2001-11-27 2002-11-25 能動電圧レベルバススイッチ（又はパスゲート）変換器 Expired - Fee Related JP4208719B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33565001P 2001-11-27 2001-11-27
PCT/US2002/037815 WO2003047106A1 (en) 2001-11-27 2002-11-25 Active voltage level bus switch (or pass gate) translator

Publications (3)

Publication Number Publication Date
JP2005510935A JP2005510935A (ja) 2005-04-21
JP2005510935A5 JP2005510935A5 (enExample) 2006-01-19
JP4208719B2 true JP4208719B2 (ja) 2009-01-14

Family

ID=34549083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003548405A Expired - Fee Related JP4208719B2 (ja) 2001-11-27 2002-11-25 能動電圧レベルバススイッチ（又はパスゲート）変換器

Country Status (3)

Country Link
US (1) US6781415B2 (enExample)
JP (1) JP4208719B2 (enExample)
TW (1) TWI276304B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956402B2 (en) * 2003-01-30 2005-10-18 Agilent Technologies, Inc. Multi-device system and method for controlling voltage peaking of an output signal transmitted between integrated circuit devices
JP3746273B2 (ja) * 2003-02-12 2006-02-15 株式会社東芝 信号レベル変換回路
ES2308253T3 (es) * 2003-09-09 2008-12-01 Thomson Licensing Aparato de pull-up (igualacion) activo para bus de datos.
GB2422258A (en) * 2005-01-12 2006-07-19 Sharp Kk Bufferless switched capacitor digital to analogue converter
GB2425006A (en) * 2005-04-05 2006-10-11 Sharp Kk Switched capacitor digital/analogue converter arrangement
US7236002B2 (en) * 2005-09-15 2007-06-26 Dialog Semiconductor Gmbh Digital CMOS-input with N-channel extended drain transistor for high-voltage protection
US20070063738A1 (en) * 2005-09-16 2007-03-22 Fischer Timothy C CMOS logic circuitry
US7446565B2 (en) * 2006-06-15 2008-11-04 California Micro Devices Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode
EP2039006A4 (en) * 2006-06-15 2013-10-09 Semiconductor Components Ind DEVICE AND METHOD FOR PROVIDING ACTIVE PULLUP AND LOGIC TRANSLATION FROM ONE SIGNAL MODE TO ANOTHER SIGNAL MODE
JP4810338B2 (ja) * 2006-07-12 2011-11-09 株式会社東芝 レベル変換バススイッチ
US7786759B2 (en) * 2006-12-22 2010-08-31 Fairchild Semiconductor Corporation Bidirectional signal interface and related system and method
US7928766B2 (en) * 2007-01-10 2011-04-19 Texas Instruments Incorporated Semi-buffered auto-direction-sensing voltage translator
JP2014239300A (ja) * 2013-06-06 2014-12-18 株式会社東芝 バススイッチ回路
US9432005B2 (en) * 2014-06-12 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pull-up circuit and related method
US9780647B2 (en) 2014-11-26 2017-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Input-output circuits
CN105939157B (zh) * 2015-03-03 2019-08-06 卡西欧计算机株式会社 电平变换电路以及投影装置
US9997208B1 (en) 2017-03-29 2018-06-12 Qualcomm Incorporated High-speed level shifter
US10566975B1 (en) 2019-05-14 2020-02-18 Nxp B.V. Level translator for SPMI bus
JP7312045B2 (ja) * 2019-07-19 2023-07-20 ローム株式会社 双方向レベルシフト回路
US12165715B2 (en) * 2020-11-25 2024-12-10 Yangtze Memory Technologies Co., Ltd. Complementary metal oxide semiconductor circuit of memory device
US12095520B2 (en) 2021-11-30 2024-09-17 Nxp Usa, Inc. Bidirectional bypass mode
CN119921758B (zh) * 2025-04-03 2025-08-12 江苏润石科技有限公司 一种适用于开漏和推挽应用的双向电平转换器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381062A (en) * 1993-10-28 1995-01-10 At&T Corp. Multi-voltage compatible bidirectional buffer
US5751168A (en) * 1995-04-28 1998-05-12 Texas Instruments Incorporated Bus switch integrated circuit with voltage translation
US5926056A (en) * 1998-01-12 1999-07-20 Lucent Technologies Inc. Voltage tolerant output buffer
US6005432A (en) * 1998-04-01 1999-12-21 S3 Incorporated Voltage level shift system and method
US6114876A (en) * 1999-05-20 2000-09-05 Pericom Semiconductor Corp. Translator switch transistor with output voltage adjusted to match a reference by controlling gate and substrate charge pumps
US6188243B1 (en) * 1999-06-09 2001-02-13 United Integrated Circuits Corp. Input/output circuit with high input/output voltage tolerance
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits

Also Published As

Publication number Publication date
TW200301621A (en) 2003-07-01
JP2005510935A (ja) 2005-04-21
US20030098714A1 (en) 2003-05-29
US6781415B2 (en) 2004-08-24
TWI276304B (en) 2007-03-11

Similar Documents

Publication Publication Date Title
JP4208719B2 (ja) 能動電圧レベルバススイッチ（又はパスゲート）変換器
KR100233172B1 (ko) 반도체 칩을 위한 출력 구동 회로
JP2863817B2 (ja) 低電圧ｃｍｏｓ出力バッファ
JP3031195B2 (ja) 入出力バッファ回路装置
EP0621692B1 (en) Overvoltage protection circuitry
JP6603287B2 (ja) 構成可能なクランプ回路
KR100194128B1 (ko) 높은 부의 클램프 전압 및 고장시 안전 동작 기능을 갖춘 모스게이트된 집적 파워 반도체 장치
CA2139008A1 (en) Output buffer circuit, input buffer circuit and bi-directional buffer circuit for plural voltage systems
JP4672126B2 (ja) 能動アンダシュート強化ｆｅｔスイッチ
US12218655B2 (en) Wide voltage gate driver using low gate oxide transistors
KR100189594B1 (ko) 전압 클램프 회로와 클램프 해제 회로를 갖는 bicmos 푸쉬-풀 형 논리 장치
JPH05259883A (ja) 低電圧出力駆動器
CN114204926A (zh) 半导体装置
US6538867B1 (en) FET switch with overvoltage protection
US6232818B1 (en) Voltage translator
US6420924B1 (en) Slew-controlled split-voltage output driver
US5570044A (en) BiCMOS output driver with reduced static power consumption
JP3742335B2 (ja) 入出力バッファ回路
US5815354A (en) Receiver input voltage protection circuit
KR100933594B1 (ko) 액티브 전압 레벨 버스 스위치(또는 통과 게이트) 변환기
US7239177B2 (en) High voltage tolerant off chip driver circuit
EP0735686B1 (en) Three-state CMOS output buffer circuit
US20020040984A1 (en) I/O circuit of semiconductor integrated device
KR100443512B1 (ko) 정전기 보호 회로
JP2000349617A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051124

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051124

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080218

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080318

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080618

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080625

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080826

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080930

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081021

R150 Certificate of patent or registration of utility model

Ref document number: 4208719

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121031

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121031

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131031

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees