JP4198792B2 - 信号線駆動回路 - Google Patents

信号線駆動回路 Download PDF

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Publication number
JP4198792B2
JP4198792B2 JP26088498A JP26088498A JP4198792B2 JP 4198792 B2 JP4198792 B2 JP 4198792B2 JP 26088498 A JP26088498 A JP 26088498A JP 26088498 A JP26088498 A JP 26088498A JP 4198792 B2 JP4198792 B2 JP 4198792B2
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JP
Japan
Prior art keywords
signal
potential
signal line
transistor
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26088498A
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English (en)
Japanese (ja)
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JP2000076868A5 (enExample
JP2000076868A (ja
Inventor
浩也 中村
Original Assignee
テキサス インスツルメンツ インコーポレイテツド
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Publication date
Application filed by テキサス インスツルメンツ インコーポレイテツド filed Critical テキサス インスツルメンツ インコーポレイテツド
Priority to JP26088498A priority Critical patent/JP4198792B2/ja
Priority to EP99202783A priority patent/EP0984360B1/en
Priority to DE69935559T priority patent/DE69935559T2/de
Priority to US09/385,344 priority patent/US6300799B1/en
Publication of JP2000076868A publication Critical patent/JP2000076868A/ja
Publication of JP2000076868A5 publication Critical patent/JP2000076868A5/ja
Application granted granted Critical
Publication of JP4198792B2 publication Critical patent/JP4198792B2/ja
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Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Dc Digital Transmission (AREA)
JP26088498A 1998-08-31 1998-08-31 信号線駆動回路 Expired - Fee Related JP4198792B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP26088498A JP4198792B2 (ja) 1998-08-31 1998-08-31 信号線駆動回路
EP99202783A EP0984360B1 (en) 1998-08-31 1999-08-26 Bus signal line driver
DE69935559T DE69935559T2 (de) 1998-08-31 1999-08-26 Bussignalleitungstreiber
US09/385,344 US6300799B1 (en) 1998-08-31 1999-08-30 Signal line driver having reduced transmission delay time and reduced power consumption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26088498A JP4198792B2 (ja) 1998-08-31 1998-08-31 信号線駆動回路

Publications (3)

Publication Number Publication Date
JP2000076868A JP2000076868A (ja) 2000-03-14
JP2000076868A5 JP2000076868A5 (enExample) 2005-11-04
JP4198792B2 true JP4198792B2 (ja) 2008-12-17

Family

ID=17354098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26088498A Expired - Fee Related JP4198792B2 (ja) 1998-08-31 1998-08-31 信号線駆動回路

Country Status (4)

Country Link
US (1) US6300799B1 (enExample)
EP (1) EP0984360B1 (enExample)
JP (1) JP4198792B2 (enExample)
DE (1) DE69935559T2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1334593A2 (en) 2000-11-13 2003-08-13 Primarion, Inc. Method and circuit for pre-emphasis equalization in high speed data communications
US7026847B2 (en) * 2003-12-31 2006-04-11 Altera Corporation Programmable current booster for faster edge-rate output in high speed applications
US20060244478A1 (en) * 2005-04-29 2006-11-02 Kent Smith Systems and methods for reducing signal ringing
KR100881195B1 (ko) * 2007-05-22 2009-02-05 삼성전자주식회사 고주파 성능을 개선한 ｏｄｔ 회로
JP5776418B2 (ja) * 2011-07-29 2015-09-09 富士通セミコンダクター株式会社 半導体記憶装置及び半導体記憶装置の制御方法
US9065544B2 (en) * 2012-09-28 2015-06-23 Osram Sylvania Inc. Pulse-based binary communication
CN112953496B (zh) * 2021-02-04 2022-04-22 电子科技大学 一种高速动态比较器
CN120825152B (zh) * 2025-09-17 2025-12-09 成都芯正微电子科技有限公司 一种能够自关断的边沿加速电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2560410B1 (fr) * 1984-02-24 1986-06-06 Efcis Circuit de precharge de bus de transfert de donnees logiques
US5134316A (en) * 1990-12-12 1992-07-28 Vlsi Technology, Inc. Precharged buffer with reduced output voltage swing
US5214320A (en) * 1992-06-12 1993-05-25 Smos Systems, Inc. System and method for reducing ground bounce in integrated circuit output buffers
KR960006911B1 (ko) * 1992-12-31 1996-05-25 현대전자산업주식회사 데이타 출력버퍼
US5453705A (en) * 1993-12-21 1995-09-26 International Business Machines Corporation Reduced power VLSI chip and driver circuit
KR0146169B1 (ko) * 1995-06-30 1998-12-01 김주용 포스트 차지 로직에 의한 펄스 전달 장치
US5760620A (en) * 1996-04-22 1998-06-02 Quantum Effect Design, Inc. CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks
KR0179930B1 (ko) * 1996-07-12 1999-04-01 문정환 출력 버퍼 제어 회로
US6054874A (en) * 1997-07-02 2000-04-25 Cypress Semiconductor Corp. Output driver circuit with switched current source
US6130556A (en) * 1998-06-16 2000-10-10 Lsi Logic Corporation Integrated circuit I/O buffer with 5V well and passive gate voltage

Also Published As

Publication number Publication date
US6300799B1 (en) 2001-10-09
DE69935559D1 (de) 2007-05-03
EP0984360A3 (en) 2004-03-17
DE69935559T2 (de) 2007-12-06
JP2000076868A (ja) 2000-03-14
EP0984360B1 (en) 2007-03-21
EP0984360A2 (en) 2000-03-08

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