JP4175982B2 - レベル比較器 - Google Patents
レベル比較器 Download PDFInfo
- Publication number
- JP4175982B2 JP4175982B2 JP2003320984A JP2003320984A JP4175982B2 JP 4175982 B2 JP4175982 B2 JP 4175982B2 JP 2003320984 A JP2003320984 A JP 2003320984A JP 2003320984 A JP2003320984 A JP 2003320984A JP 4175982 B2 JP4175982 B2 JP 4175982B2
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- JP
- Japan
- Prior art keywords
- output
- comparator
- time
- terminal
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Description
図5は従来のレベル比較器を示しており、図6は図5の動作波形図である。
同様に、時間経過に伴い映像信号が下がりはじめ、再び基準電圧と同レベルに至ったとき、即ちこの時点をT2とすると、T2時点を経過後は、また映像信号が基準電圧より低くなる。このとき、コンパレータ(101)の出力はハイレベルからローレベルへと状態変化をする。但し、コンパレータ(101)の出力がハイレベルからローレベルへと出力データの状態変化が起こる際、遅延時間TdHLが生じる。従って、映像信号が下降し、基準電圧と同レベルになるT2時点を起点とすると、実際にコンパレータ(101)の出力がハイレベルからローレベルへと状態変化を起こすタイミングは、T2時点からTdHLの遅延時間が経過した後になる。
Claims (3)
- 入力信号と基準信号とのレベルを比較するレベル比較器において、
前記入力信号が一方の端子に印加され、前記基準電圧が他方の端子に印加される第1コンパレータと、
前記入力信号が他方の端子に印加され、前記基準電圧が一方の端子に印加される第2コンパレータと、
前記第1及び第2コンパレータの出力信号を受け、選択して出力する制御回路と、を備え
前記制御回路は、クロックが到来する毎に前記第1及び第2コンパレータの出力信号の値を更新する第1及び第2フリップフロップ回路と、前記第1及び第2フリップフロップ回路の出力を受け、前記入力信号の変化を早く検知した前記第1及び第2フリップフロップ回路からの出力を選択して出力する組み合わせ回路と、を有することを特徴とするレベル比較器。 - 前記一方の端子は非反転入力端子とし、前記他方の端子は反転入力端子とし、前記制御回路は、前記入力信号が立ち上がり時は前記第2コンパレータの出力を選択し、前記入力信号が立下り時は前記第1コンパレータの出力信号を選択することを特徴とする請求項1記載のレベル比較器。
- 前記一方の端子は反転入力端子とし、前記他方の端子は非反転入力端子とし、前記制御回路は、前記入力信号が立ち上がり時は前記第1コンパレータの出力を選択し、前記入力信号が立下り時は前記第2コンパレータの出力信号を選択することを特徴とする請求項1記載のレベル比較器。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003320984A JP4175982B2 (ja) | 2003-09-12 | 2003-09-12 | レベル比較器 |
CNB2004100644113A CN1324879C (zh) | 2003-09-12 | 2004-08-24 | 电平比较器 |
TW093127217A TWI258283B (en) | 2003-09-12 | 2004-09-08 | Level comparator |
KR1020040072434A KR100611698B1 (ko) | 2003-09-12 | 2004-09-10 | 레벨 비교기 |
US10/938,873 US7332939B2 (en) | 2003-09-12 | 2004-09-13 | Comparator system and method for comparing an input signal with a reference level using said system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003320984A JP4175982B2 (ja) | 2003-09-12 | 2003-09-12 | レベル比較器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005094099A JP2005094099A (ja) | 2005-04-07 |
JP4175982B2 true JP4175982B2 (ja) | 2008-11-05 |
Family
ID=34452796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003320984A Expired - Fee Related JP4175982B2 (ja) | 2003-09-12 | 2003-09-12 | レベル比較器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7332939B2 (ja) |
JP (1) | JP4175982B2 (ja) |
KR (1) | KR100611698B1 (ja) |
CN (1) | CN1324879C (ja) |
TW (1) | TWI258283B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080061842A1 (en) * | 2006-09-07 | 2008-03-13 | Micron Technology, Inc. | Circuit and method for detecting timed amplitude reduction of a signal relative to a threshold voltage |
US7560959B2 (en) * | 2006-09-18 | 2009-07-14 | Micron Technology, Inc. | Absolute value peak differential voltage detector circuit and method |
JP6007806B2 (ja) * | 2013-01-30 | 2016-10-12 | 凸版印刷株式会社 | Cmosコンパレータ |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3683284A (en) * | 1968-06-25 | 1972-08-08 | Picker Corp | Pulse height analyzer |
US4418332A (en) * | 1981-06-24 | 1983-11-29 | Harris Corporation | Noise insensitive comparator |
GB8716144D0 (en) * | 1987-07-09 | 1987-08-12 | British Aerospace | Comparator circuits |
JP2897599B2 (ja) * | 1993-06-23 | 1999-05-31 | 松下電器産業株式会社 | 画像形成装置 |
JPH07240857A (ja) | 1994-02-28 | 1995-09-12 | Sony Corp | データスライサ |
JP2604549B2 (ja) * | 1994-06-16 | 1997-04-30 | 山形日本電気株式会社 | クランプパルス発生回路 |
JPH09135365A (ja) * | 1995-11-07 | 1997-05-20 | Matsushita Electric Ind Co Ltd | ブランキング回路 |
JPH10200709A (ja) * | 1997-01-07 | 1998-07-31 | Nikon Corp | 明暗情報読み取り方法およびその装置 |
US6326816B1 (en) * | 1999-12-09 | 2001-12-04 | Via Technologies, Inc. | Method and apparatus for minimal phase delay and zero-crossing filtering |
TW554606B (en) * | 2000-03-31 | 2003-09-21 | Sanyo Electric Co | Phase transfer circuit and FM wave detection circuit |
-
2003
- 2003-09-12 JP JP2003320984A patent/JP4175982B2/ja not_active Expired - Fee Related
-
2004
- 2004-08-24 CN CNB2004100644113A patent/CN1324879C/zh not_active Expired - Fee Related
- 2004-09-08 TW TW093127217A patent/TWI258283B/zh not_active IP Right Cessation
- 2004-09-10 KR KR1020040072434A patent/KR100611698B1/ko not_active IP Right Cessation
- 2004-09-13 US US10/938,873 patent/US7332939B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2005094099A (ja) | 2005-04-07 |
CN1324879C (zh) | 2007-07-04 |
KR100611698B1 (ko) | 2006-08-11 |
TWI258283B (en) | 2006-07-11 |
TW200511785A (en) | 2005-03-16 |
KR20050027052A (ko) | 2005-03-17 |
US20050174150A1 (en) | 2005-08-11 |
CN1595955A (zh) | 2005-03-16 |
US7332939B2 (en) | 2008-02-19 |
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