JP4157266B2 - 電力用半導体装置およびその製造方法 - Google Patents

電力用半導体装置およびその製造方法 Download PDF

Info

Publication number
JP4157266B2
JP4157266B2 JP2000303853A JP2000303853A JP4157266B2 JP 4157266 B2 JP4157266 B2 JP 4157266B2 JP 2000303853 A JP2000303853 A JP 2000303853A JP 2000303853 A JP2000303853 A JP 2000303853A JP 4157266 B2 JP4157266 B2 JP 4157266B2
Authority
JP
Japan
Prior art keywords
layer
type
conductivity type
semiconductor
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000303853A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002110979A5 (enExample
JP2002110979A (ja
Inventor
健一 都鹿野
芳彦 斉藤
渉 齋藤
一郎 大村
常雄 小倉
弘通 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000303853A priority Critical patent/JP4157266B2/ja
Publication of JP2002110979A publication Critical patent/JP2002110979A/ja
Publication of JP2002110979A5 publication Critical patent/JP2002110979A5/ja
Application granted granted Critical
Publication of JP4157266B2 publication Critical patent/JP4157266B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2000303853A 2000-10-03 2000-10-03 電力用半導体装置およびその製造方法 Expired - Fee Related JP4157266B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000303853A JP4157266B2 (ja) 2000-10-03 2000-10-03 電力用半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000303853A JP4157266B2 (ja) 2000-10-03 2000-10-03 電力用半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2002110979A JP2002110979A (ja) 2002-04-12
JP2002110979A5 JP2002110979A5 (enExample) 2005-06-16
JP4157266B2 true JP4157266B2 (ja) 2008-10-01

Family

ID=18784995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000303853A Expired - Fee Related JP4157266B2 (ja) 2000-10-03 2000-10-03 電力用半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP4157266B2 (enExample)

Also Published As

Publication number Publication date
JP2002110979A (ja) 2002-04-12

Similar Documents

Publication Publication Date Title
KR100732051B1 (ko) 고전압 ｍｏｓｆｅｔ 및 고전압 ｍｏｓｆｅｔ 형성 방법
JP4109565B2 (ja) 半導体装置の製造方法および半導体装置
US20090085111A1 (en) Semiconductor device and method of manufacturing the same
JP6319508B2 (ja) 半導体装置及び半導体装置の製造方法
US6821858B2 (en) Semiconductor devices and methods for manufacturing the same
JP2011505709A (ja) フローティングアイランドを形成するための雛壇状のトレンチを備えた電圧維持層を有するパワー半導体デバイスの製造方法
US7372088B2 (en) Vertical gate semiconductor device and method for fabricating the same
JP5211652B2 (ja) 横型ｍｏｓトランジスタの製造方法
JP3551251B2 (ja) 絶縁ゲート型電界効果トランジスタ及びその製造方法
JP4157266B2 (ja) 電力用半導体装置およびその製造方法
JP2797798B2 (ja) 突き抜け防止のための埋込コンタクトを有する半導体装置とその製造方法
CN111627984B (zh) 超结器件及其制造方法
US7144781B2 (en) Manufacturing method of a semiconductor device
JP2005044948A (ja) 半導体装置、および、その製造方法
JP2010027680A (ja) 半導体装置および半導体装置に製造方法
JPS60226120A (ja) 半導体装置における電極の引出し方法
KR100317688B1 (ko) 반도체장치의 제조방법
JP2006156989A (ja) 半導体装置及びその製造方法
JP7495257B2 (ja) 半導体集積回路、および半導体集積回路の製造方法
JP6973422B2 (ja) 半導体装置の製造方法
JP2009070848A (ja) 半導体装置
JPS5846648A (ja) 半導体装置の製造方法
JPH04255233A (ja) 半導体装置及びその製造方法
JPH1084111A (ja) 高耐圧ｍｏｓトランジスタ
JP5581977B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040917

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040917

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060119

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080415

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080613

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080708

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080711

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110718

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110718

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees