JP4149891B2 - コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法 - Google Patents

コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法 Download PDF

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Publication number
JP4149891B2
JP4149891B2 JP2003350842A JP2003350842A JP4149891B2 JP 4149891 B2 JP4149891 B2 JP 4149891B2 JP 2003350842 A JP2003350842 A JP 2003350842A JP 2003350842 A JP2003350842 A JP 2003350842A JP 4149891 B2 JP4149891 B2 JP 4149891B2
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JP
Japan
Prior art keywords
electrolytic capacitor
conductive
capacitor
metal body
valve metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003350842A
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English (en)
Japanese (ja)
Other versions
JP2004221534A5 (el
JP2004221534A (ja
Inventor
浩一 平野
雅憲 吉田
浩之 半田
嘉久 山下
誠一 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2003350842A priority Critical patent/JP4149891B2/ja
Publication of JP2004221534A publication Critical patent/JP2004221534A/ja
Publication of JP2004221534A5 publication Critical patent/JP2004221534A5/ja
Application granted granted Critical
Publication of JP4149891B2 publication Critical patent/JP4149891B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004Details
    • H01G9/008Terminals
    • H01G9/012Terminals specially adapted for solid capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231Capacitors or dielectric substances
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679Aligning added circuit layers or via connections relative to previous circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2003350842A 2002-12-27 2003-10-09 コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法 Expired - Fee Related JP4149891B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003350842A JP4149891B2 (ja) 2002-12-27 2003-10-09 コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002379231 2002-12-27
JP2003350842A JP4149891B2 (ja) 2002-12-27 2003-10-09 コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法

Publications (3)

Publication Number Publication Date
JP2004221534A JP2004221534A (ja) 2004-08-05
JP2004221534A5 JP2004221534A5 (el) 2006-07-06
JP4149891B2 true JP4149891B2 (ja) 2008-09-17

Family

ID=32911234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003350842A Expired - Fee Related JP4149891B2 (ja) 2002-12-27 2003-10-09 コンデンサとコンデンサ内蔵回路基板、ならびにそれらの製造方法

Country Status (1)

Country Link
JP (1) JP4149891B2 (el)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4599997B2 (ja) * 2004-11-08 2010-12-15 凸版印刷株式会社 固体電解コンデンサを内蔵した配線基板の製造方法
JP4736451B2 (ja) 2005-02-03 2011-07-27 パナソニック株式会社 多層配線基板とその製造方法、および多層配線基板を用いた半導体パッケージと電子機器
CN101180693B (zh) 2005-05-18 2011-10-26 三洋电机株式会社 层叠型固体电解电容器及其制造方法
JP4839824B2 (ja) * 2005-12-21 2011-12-21 パナソニック株式会社 コンデンサ内蔵基板およびその製造方法
JP2007201065A (ja) * 2006-01-25 2007-08-09 Hitachi Aic Inc コンデンサ内蔵基板
JP5003226B2 (ja) * 2007-03-20 2012-08-15 日本電気株式会社 電解コンデンサシート及び配線基板、並びに、それらの製造方法
JP4812118B2 (ja) 2007-03-23 2011-11-09 Necトーキン株式会社 固体電解コンデンサ及びその製造方法
JP5211777B2 (ja) * 2008-03-17 2013-06-12 富士通株式会社 電解キャパシタ及びその製造方法並びに配線基板
DE112018006091T5 (de) 2017-12-27 2020-08-20 Murata Manufacturing Co., Ltd. Halbleiter-verbund-bauelement und darin verwendete package-platine

Also Published As

Publication number Publication date
JP2004221534A (ja) 2004-08-05

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