JP4088582B2 - ブリッジ後メタライゼーション形成手順を用いた強固な超低誘電率の相互接続構造を形成する方法 - Google Patents
ブリッジ後メタライゼーション形成手順を用いた強固な超低誘電率の相互接続構造を形成する方法 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
110 ビア・レベル層間誘電体(ILD)
120 配線レベル層間誘電体(ILD)
130 ハードマスク層
140 フォトレジスト層
150 配線
160 トレンチ
170 ビア
180 ビア開口部
190 デュアル・ダマシン型トレンチとビア構造
200 材料スタック
210 充填材料(金属配線)
220 キャップ材料
230 層間配線キャビティ
240 (ピンチ・オフ)絶縁膜
250 エアー・ブリッジ構造
290 上位レベル
310 ビア部分
3110、3270、7270 絶縁(誘電体)層
3130、4130、7130、8130、9130 ハードマスク層
3140、4140、7140、8140、9140 フォトレジスト層
3150 配線レベル・パターン
3160 配線レベル凹部
3170、7170、8170、9170 ビア・パターン
3180、8180、9180 ビア開口部
3190、8190、9190 デュアル・ダマシン構造
3200、7200、8200、9200 ライナー層
3220、4220、7220 キャップ層
3270、4270 配線レベルILD(犠牲材料)
3280、8280 誘電体ブリッジ材料(ブリッジ層)
3290、4290、5290 孔パターン・ステンシル
3300、4300、5300、小孔
3310、3370 ILDコーティング
3320 キャップ層
4110 ILDスタックの底部層(ビア・レベル誘電体)
4220 キャップ
4280 共形ブリッジ層
4320 バリヤ層
4330 形状(トポグラフィ)
4340 エアー・ブリッジ構造
5270 単一犠牲材料層
5330 貫通層
5350、9380 エアー・ブリッジ
7160、8160 配線トレンチ(ギャップ)
7190 スタック構造
7200 ライナー
7210、9210 金属充填
7270、8270、9270、10270 パターン化された材料
7370、8360、9360、10360 サポート材料
8210 金属
8270 絶縁層
9160 ギャップ
9270、11270 犠牲材料
9280 ブリッジ層
9290 孔アレイ
9300 有孔膜
10390、10400 レベル
10410 多層エアー・ブリッジ
11180 ビア
11200、12200 ライナー
11210 導電充填材料
11220 キャップ
11270、12270 犠牲材料
11280 ブリッジ
11370 凹部
12100 基板
12130 ハードマスク
12160 ギャップ
12170 ビア・パターン
12210 金属
12220 キャップ層
12310 ハードマスク・スタック
12360 サポート材料
12430 部分的ビア
12910 デュアル・ダマシン構造
Claims (13)
- (a)絶縁層を基板表面の上に形成する工程と、
(b)複数の配線トレンチを形成する工程であって、前記トレンチの底表面は前記絶縁層内部に位置する、工程と、
(c)前記絶縁層および前記トレンチの表面を覆って誘電体ブリッジ層を堆積する工程と、
(d)前記複数の配線トレンチの少なくとも1つの底部を貫通し、前記誘電体ブリッジ層及び前記絶縁層を貫いて延長するビアを形成する工程と、
(e)前記ビアと前記複数の配線トレンチにライナーと充填金属を順次堆積しかつ充填し、前記充填金属の上面が前記誘電体ブリッジ層の上面と同一平面になるように、前記ライナーと前記充填金属を平坦化して、金属配線を形成する工程と、
(f)前記誘電体ブリッジ層に小孔アレイを形成する工程と、
(g)前記小孔アレイを介して、前記複数の金属配線の間から前記絶縁層の一部分を抽出する工程と、
を順次含む、相互接続構造を形成する方法。 - 前記金属配線は前記誘電体ブリッジ層により横方向に支持され、前記抽出する工程で残存する前記絶縁層により縦方向に支持される、請求項1に記載の方法。
- 前記小孔アレイの孔の直径は14ナノメートル未満である、請求項1に記載の方法。
- 前記ビアを形成する工程において、前記複数の配線トレンチの少なくとも1つのトレンチ内に絶縁側壁層を前もって形成する工程をさらに含む、請求項1に記載の方法。
- 前記小孔アレイが封止されるように、バリヤ誘電体を前記誘電体ブリッジ層の上に堆積する工程をさらに含む、請求項1に記載の方法。
- 前記小孔のアレイの形成は、インプリント・リソグラフィと、ソフト・リソグラフィと、CdSeおよびSiのようなナノ結晶と、自己組織化プロセスと、スピノイダル分解と、ポリマー混合物、共重合体、ブロック共重合体、もしくは混合物の相分離と、ジブロック共重合体の相分離、およびそれらの組み合わせからなるグループから選択されるプロセスによって実施される、請求項1に記載の方法。
- 前記絶縁層は、前記複数の配線トレンチのうちの1つのトレンチ底表面と同一平面にある上表面を有する下部絶縁層と、前記下部絶縁層より前記誘電体ブリッジ層に延長する上部絶縁層とを具備し、
前記絶縁層の前記一部分を抽出する前記工程は、前記上部絶縁層のみを抽出することを含み、それによって前記下部絶縁層は、前記複数の配線トレンチの下および間の両方に残存する、請求項1に記載の方法。 - 前記絶縁層は、前記複数の配線トレンチの前記すくなくとも1つのトレンチ底表面と同一平面にある上表面を有しかつ前記複数の配線トレンチの下のみで前記配線トレンチの側面にそって延長する第1の絶縁層と、前記基板表面から前記第1の絶縁層の外側の前記誘電体ブリッジ層まで延長する第2の絶縁層とを具備し、
前記絶縁層を形成する前記工程は、前記複数の配線トレンチと互いに側面にそって外延する前記第1の絶縁層のパターニング工程を含み、
前記絶縁層の一部分を抽出する前記工程は、前記第2の絶縁層のみを抽出することを含み、それによって前記第2の絶縁層は前記複数の配線トレンチの下に残存する、請求項1に記載の方法。 - 前記第2の絶縁層は、ポリメチルメタクリレート、ポリブタジエン、ポリスチレン、パリレン、ポリエチレン・オキシド、ポリウレタン、ポリカルボシラン、ポリシリザン、ポリメチレン・オキシド、ポリ(ノルボレン)、テフロン(登録商標)、ポリエチレン、ポリ
(メチレンオキサイド)、架橋不飽和ポリマー、多孔質架橋ポリマー、線状重合体(line
ar polymer)、分岐重合体(branched
polymer)、超分岐重合体(hyperbranched polyme
r)、樹状ポリマー(dendritic polymer)、脂肪族ポリマー、芳香族ポリマー、ダイヤモ
ンド・ライク・カーボン(DLC)、メチルシセスクオキサン、ハイドロシセスクオキサン
、ジメチルシロキサン、官能基ジメチルシロキサン、無機ポリマー、無機ガラス、および
スピン・オン・ガラスを含むグループから選択される、請求項8に記載の方法。 - 前記絶縁層は、抽出可能な誘電体の単一層を含み、かつ前記抽出する前記工程は、前記単一層を抽出することを含み、それによって前記絶縁層は前記トレンチ底表面の下から除去される、請求項1に記載の方法。
- 前記工程(b)において、
前記絶縁層の一部分を貫通する配線トレンチを形成し、かつ前記配線トレンチをサポート誘電体で充填する工程と、
前記サポート誘電体の一部分にビア深さまで凹部(くぼみ)を形成する工程と、
を含み、
前記工程(g)において、
前記絶縁層の残存する部分を抽出する工程と、
をさらに含む、請求項1に記載の方法。 - 前記サポート誘電体は、架橋有機ポリマーと、多孔質有機膜と、ダイヤモンド・ライク・カーボンと、二酸化シリコンと、Si、C、OおよびHをPECVDによる低k誘電体と、少なくともメチルシセスクオキサン、ハイドロシセスクオキサン、およびシセスクオキサン混合物を含むスピン・オン・ガラスと、これらの材料で多孔質の形態と、を含むグループから選択される、請求項11に記載の方法。
- 前記誘電体ブリッジ層は、二酸化シリコン、炭化シリコン、窒化シリコン、シリコン・オキシナイトライド、メチルシルセキオキサン、ハイドロシルセキオキサン、パリレン、官能基パリレン、ポリシロキサン、ポリカルボシラン、ポリジメチルシロキサン、有機ポリマー・シリレート、ポリハロカーボン、ポリフルオロカーボン、テトラエチルオルソシリケート、スピン・オン・ガラス、CVDによるポリマー膜、有機と無機CVD膜、およびSi、C、O、あるいはHを含む無機と有機PECVDによる膜、およびその組み合わせからなるグループから選択される、請求項1に記載の方法。
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2002
- 2002-12-27 US US10/331,038 patent/US6930034B2/en not_active Expired - Lifetime
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2003
- 2003-11-28 TW TW092133506A patent/TWI265572B/zh not_active IP Right Cessation
- 2003-12-08 KR KR1020030088561A patent/KR100596297B1/ko not_active IP Right Cessation
- 2003-12-18 JP JP2003421653A patent/JP4088582B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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CN1514478A (zh) | 2004-07-21 |
CN1295777C (zh) | 2007-01-17 |
KR20040060734A (ko) | 2004-07-06 |
US6930034B2 (en) | 2005-08-16 |
JP2004214648A (ja) | 2004-07-29 |
TW200426947A (en) | 2004-12-01 |
TWI265572B (en) | 2006-11-01 |
US20040127001A1 (en) | 2004-07-01 |
KR100596297B1 (ko) | 2006-06-30 |
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