JP4086365B2 - Serial semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial semiconductor memory that inputs or outputs data in a bit string for each bit.
[0002]
[Prior art]
The conventional serial semiconductor memory stores the storage data of each address as multi-bit data such as byte units or word units, and at the time of reading the storage data, the multi-bit storage data accessed by the memory is converted into a bit string. It is serially output bit by bit.
[0003]
[Problems to be solved by the invention]
However, the conventional serial semiconductor memory has a problem in that only specific bit information cannot be directly and quickly read from each stored data.
[0004]
That is, in the conventional serial semiconductor memory, the storage data of a plurality of bits is serially output one bit at a time, so that information on specific bits can be obtained unless waiting until bit data other than the specific bits are serially output. It was not possible to read only specific bits directly.
[0005]
In particular, when reading information of specific bits included in each of a plurality of stored data, it is necessary to repeat a plurality of serial outputs corresponding to the number of the stored data, and substantially all of the stored data Therefore, information of only a specific bit cannot be read continuously in a short time.
[0006]
There are the following cases as specific problems due to the fact that the information of the specific bit cannot be directly read. A management system for storing a plurality of file data and a plurality of management data for individually managing unique information of each file data in a conventional serial semiconductor memory and managing each file data based on these management data When it is constructed, it is not possible to directly read out only specific bit information (file data type, etc.) included in these multiple management data, so it is not possible to retrieve only necessary information in a short time. There was a problem.
[0007]
[Means for Solving the Problems]
The present invention has been made to overcome such problems of the prior art, storing stored data in units of a plurality of bits corresponding to each address, and storing the stored data by command data set from the outside. In a serial semiconductor memory that converts the stored data accessed in a plurality of bits into a bit string and outputs it serially when receiving a read command of
When the command data not including a specific bit read command is received, the memory-accessed storage data is transmitted in a bit string for each bit, and when a specific bit read command is received by the command data, the memory accessed A bidirectional shift register that outputs stored data in units of multiple bits;
A data selector for sending only the specified bit among the storage data output from the bidirectional shift register when reading the specified bit specified by the command data ;
The data transfer processing means having
[0008]
According to such a configuration, when a specific bit in the stored data is designated by the command data, only the information of the specific bit is read directly and quickly.
[0010]
In addition , switching between reading only a specific bit of the stored data and reading the stored data as it is is performed according to the contents of the command data.
[0011]
Further, the data transfer processing means, upon receiving a write command of a specific bit by the command data, transfers the write data only to the specified specific bit via the bidirectional shift register and accesses the memory. did.
[0012]
According to this configuration, when data write to a specific bit is designated by command data, data is written to only the specific bit from the outside.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS. A serial semiconductor memory that accesses memory in units of 8 bits will be described.
Furthermore, the manufacturing process of nonvolatile semiconductor memory such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, and the like, and the solid element manufacturing process such as FRAM (Ferro Electric Random Access Memory) A serial semiconductor memory to be manufactured will be described.
[0014]
FIG. 1 is a block diagram showing the configuration of the serial semiconductor memory of this embodiment. In this figure, this serial semiconductor memory includes a memory matrix section 1 having a large number of memory cells D _{00 to} D _N7 , a serial / parallel conversion circuit 2 as data transfer processing means, a control circuit 3, an address decoder 4, and An address counter 5 is provided. Further, the serial / parallel conversion circuit 2 includes a bidirectional shift register 6, a data selector 7, and a switching circuit 8 as 8-bit data conversion means.
[0015]
In the memory matrix portion 1, memory cells D _{00 to} DN ₇ are arranged in units of 8 bits (byte units). Byte lines A _{00 to} A _MN are individually connected to each array in the byte unit in the horizontal direction, and eight data lines d _{0 to} d ₇ are individually connected to each array in the same direction in the vertical direction. The byte lines A _{00 to} A _MN constitute an address bus, and the data lines d _{0 to} d ₇ constitute a memory bus.
[0016]
The bidirectional cyst register 6 is composed of an 8-bit B0 to B7 shift register, a serial input / output contact G connected to the 1-bit serial data bus Si, and a parallel input / output contact X0 connected to the memory bus. To X7 and parallel output contacts P0 to P7 connected to the eight parallel data lines S0 to S7 are provided.
[0017]
The bidirectional cyst register 6 performs a right shift or a left shift operation in synchronization with the clock signal CK, and performs the next data transfer process in accordance with the instruction of the control signal Csf from the control circuit 3.
[0018]
That is, when the “normal write mode” described later is instructed by the control signal Csf, the write data Dwt on the serial data bus Si is serially input bit by bit through the serial input / output contact G while performing a right shift operation. Each time 8-bit data is input, the data is transferred in parallel to the memory bus via the parallel input / output contacts X0 to X7.
[0019]
When a “normal read mode” to be described later is instructed by the control signal Csf, the 8-bit data transferred from the memory matrix portion 1 is input in parallel via the parallel input / output contacts X0 to X7, and then left The data is serially converted into bit string read data Drd by a shift operation and sent to the serial data bus Si bit by bit via the serial input / output contact G.
[0020]
When a “bit string designation read mode” to be described later is instructed by the control signal Csf, 8-bit data transferred from the memory matrix unit 1 is input in parallel via the parallel input / output contacts X0 to X7. The data is transferred in parallel to the data selector 7 via the parallel output contacts P0 to P7.
[0021]
The data selector 7 includes an 8-input 1-output multiplexer or the like. In the “bit string designation read mode”, only one bit data designated by the control signal Cmx from the control circuit 3 is selected from the 8-bit data B0 to B7 supplied from the bidirectional shift register 6, The selected 1-bit data Dbt is sent to the switching circuit 8 via the data line Sb.
[0022]
The switching circuit 8 is constituted by an analog switch or the like that performs switching operation according to the control signal Csw from the control circuit 3, and in the “normal write mode” and “normal read mode”, the 1-bit external data bus So and the serial data bus Si. And in the “bit string designation read mode”, the external data bus So and the data line Sb are connected.
[0023]
The control circuit 3 is composed of a decoder circuit or the like, and determines a command data COM in the input data Din input via the external data bus So, and controls a mode control signal Cad for controlling the address decoder 4; The control signals Csw, Cmx, Csf are generated. Further, the memory access request signal Cas for controlling the address counter 5 is generated by determining the address data ADR included in the input data Din. The memory access control in the “normal read mode”, “normal read mode”, and “bit string designation read mode” is performed by these control signals Csw, Cmx, Csf, Cad and the memory access request signal Cas.
[0024]
The address decoder 4 outputs an address clock signal CKad having a different cycle according to an instruction of the mode control signal Cad. That is, when “normal write mode” or “normal read mode” is instructed by the mode control signal Cad, one address clock signal CKad is output every time an 8-cycle clock signal CK is input, and “bit string designation read” is output. When “mode” is instructed, the address clock signal CKad having the same cycle as the clock signal CK is output.
[0025]
Address counter 5 is composed of a shift counter or the like for counting an address clock signal CKad, sequentially outputs the count value to a byte line A ₀₀ to A _MN address # 00~ # MN according to the memory access request signal Cas. As a result, addresses # 00 to #MN are sequentially set for each system clock signal CK of 8 cycles in the “normal read mode” or “normal write mode”, and in the “bit string designation read mode”, the clock signal CK It is set sequentially in synchronization with the cycle.
[0026]
Next, a memory access control operation by the control circuit 3 will be described with reference to FIG. 2A shows the configuration of input data Din for memory access and its transfer timing, and FIG. 2B shows the configuration of command data COM.
[0027]
As shown in FIG. 2A, 1-byte or multiple-byte address data ADR1, ADR2 and 1-byte command data COM for instructing memory access are synchronized with a clock signal CK to an external data bus So. Are input in series, the control circuit 3 generates the control signals Csw, Cmx, Csf, Cad and the memory access request signal Cas.
[0028]
Further, when bits 7 to 4 of the command data COM shown in FIG. 5B are set to 1H (0, 0, 0, 1), the “normal write mode” is set, and the switching circuit 8 is serially connected to the external data bus So. The data bus Si is connected, and the address counter 5 sets the address of the memory matrix unit 1 specified by the address data ADR1 and ADR2 based on the count value of the address clock signal CKad and the memory access request signal Cas. As a result, the write data Dwt input following the command data COM is transferred from the external data bus So to the serial data bus Si, and further designated by the address data ADR1 and ADR2 via the bidirectional shift register 6. The data is stored in bytes at the address of the memory matrix unit 1.
[0029]
When bits 7 to 4 of the command data COM are set to 0H (0, 0, 0, 0), the “normal read mode” is set, and the switching circuit 8 connects the external data bus So and the serial data bus Si, and addresses The counter 5 sets the address of the memory matrix portion 1 specified by the address data ADR1 and ADR2 based on the count value of the address clock signal CKad and the memory access request signal Cas. As a result, the byte-unit data accessed by the memory is sent to the serial data bus Si as read data Drd for each bit via the bidirectional shift register 6, and this read data Drd is externally output as the output data Dout. It is sent to the data bus So.
[0030]
That is, in the “normal read mode”, as shown in the timing chart of FIG. 3A, addresses # 00, # 01,... Are sequentially added in synchronization with the address clock signal CKad generated every eight cycles of the clock signal CK. Is set. Then, 8-bit data accessed by the memory is serially output for each bit in synchronization with the clock signal CK within the generation cycle of the address clock signal CKad.
[0031]
When bit 7 to bit 4 of the command data COM are set to FH (1, 1, 1, 1), the “bit string designation read mode” is set, the switching circuit 8 connects the external data bus So and the data line Sb, and the address counter 5 sets the memory address of the memory map 1 specified by the address data ADR1 and ADR2 based on the count value of the address clock signal CKad and the memory access request signal Cas. Further, the control circuit 3 determines a specific bit specified by bits 2 to 0 in the command data COM, and generates a control signal Cmx indicating the specific bit. Then, the data selector 7 connects one of the parallel data lines S0 to S7 specified by the control signal Cmx and the data line Sb. As a result, the byte-unit data accessed by the memory is transferred to the data selector 7 via the shift register 6, and the specific 1-bit data Dbt specified by the control signal Cmx is output as the output data Dout. Sent to So.
[0032]
That is, in the “bit string designation read mode”, as shown in the timing chart of FIG. 3B, addresses # 00, # 01, etc. are sequentially set in synchronization with the clock signal CK and the address clock signal CKad. The data of the specific bit designated by the command data COM is continuously read in synchronization with the clock signal CK and the address clock signal CKad. FIG. 3B shows, as an example, a case where specific data of the seventh bit is designated by command data COM.
[0033]
As described above, according to the serial semiconductor memory of the present embodiment, when the “bit string designation read mode” and the specific bit are designated by the command data COM, the specific bit is selected from the data of the memory address corresponding to the address data ADR1 and ADR2. Only information can be read directly.
[0034]
Furthermore, as shown in FIG. 3A, when trying to obtain information of only a specific bit in the “normal read mode”, the data of the specific bit is output every clock signal CK of 8 cycles. In the “bit string designation read mode”, as shown in FIG. 3B, data of a specific bit is output for each cycle of the clock signal CK. Therefore, according to the “bit string designation read mode”, it is possible to perform a high-speed read that is about eight times faster than the “normal read mode”.
[0035]
In addition, when reading a lot of data, set it to “normal read mode”, and when reading only the data of a specific bit that is necessary, set it to “bit string designation read mode”. Is possible.
[0036]
Next, a specific example using the serial semiconductor memory of this embodiment will be described with reference to FIG.
[0037]
A management system for managing unique information of image data recorded on a recording medium by attaching the serial semiconductor memory to a recording medium used in an imaging apparatus such as a digital camera, a camera using a silver salt film, and a video camera. To construct.
[0038]
As shown in the memory map of FIG. 4, an image information storage area and a management information storage area are allocated to the storage area of the serial semiconductor memory. Then, a plurality of image data assigned with file numbers §00 to §mn are stored in the image information storage area, and a plurality of management data for individually managing the unique information of each image data is stored in the management information storage area Like that. Further, as shown in FIG. 2C, necessary management information is allocated in bit units in common by encoding each management data in a predetermined format.
[0039]
By accessing the image information storage area and the management information storage area in the “normal write mode” and “normal read mode”, the image data and the management data are written and read. Further, when the information of the specific bit included in the management data shown in FIG. 2C is read, the above “bit string designation read mode” is set.
[0040]
By constructing such a management system, by setting the “bit string designation read mode”, only specific bit information can be read directly and continuously, and specific information of image data can be searched quickly. .
[0041]
As described above, the serial semiconductor memory according to the present embodiment stores a plurality of file data such as the above-described image data and sound data, and a plurality of management data for individually managing the unique information of each file data. The present invention is effective for use in applications such as building a management system for managing each file data based on these management data.
[0042]
In the above description, a serial semiconductor memory that accesses data in units of 8 bits has been described. However, the present invention is not limited to this. That is, the memory cells of the memory matrix unit 1 are arranged in word units (16-bit units) or other plural-bit units, and correspondingly, the control circuit 3, the address decoder 4, the address counter 5, the bidirectional shift register 6, The data selector 7, the switching circuit 8, and the like may be configured.
[0043]
In the present embodiment, the case where only the data of a specific bit in the memory matrix unit 1 is read in the “bit string designation read mode” has been described, but the present invention is not limited to this. That is, conversely, under the control of the control circuit 3 which has input the write data to the shift register 6 following the command data COM instructing writing to only a specific bit, the contents of the command data COM are determined. Alternatively, data may be written only to the designated specific bit.
[0044]
In this embodiment, the serial semiconductor memory manufactured by the process of manufacturing a rewritable semiconductor memory such as EPROM, EEPROM, flash memory, FRAM, etc. has been described. However, the present invention is not limited to this. Absent. It may be a serial semiconductor memory in which a read-only ROM (Read Only Memory) such as a mask ROM that cannot be rewritten is applied to the memory matrix portion. Also in this case, by setting the “bit string designation read mode”, it is possible to read only information of a specific bit in the data stored in advance.
[0045]
Further, the memory matrix portion may be manufactured by a manufacturing process of a volatile semiconductor memory such as SRAM (Static Randaom Access Memory). In other words, when it is necessary to keep data non-destructively even after the power supply is cut off, it is manufactured with EPROM, EEPROM, flash memory, FRAM, etc. DRAM or SRAM can be applied.
[0046]
【The invention's effect】
As described above, according to the present invention, when the specific bit in the stored data is designated by the command data, the specific bit in the stored data is accessed by the data transfer processing means. Can be read directly. Further, since the problem that the information of specific bits cannot be obtained unless all the stored data is read out as in the prior art is solved, only the information of necessary specific bits can be obtained quickly.
[0047]
In addition, when the command data is not instructed to read a specific bit, the stored data is read in a bit string for each bit. Therefore, according to the contents of the command data, only a specific bit of the stored data is read. The stored data can be switched to read as it is.
[0048]
In addition, when a specific bit write by command data is instructed, data write to only the specific bit is performed, so that necessary bit data can be written in a short time.
[0049]
In this way, data can be read from specific bits and written to specific bits, so only specific bit information (file data types, etc.) contained in multiple management data can be searched in a short time. Thus, it is possible to provide a serial semiconductor memory suitable for applications such as updating only specific bit information.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a serial semiconductor memory according to an embodiment.
FIG. 2 is an explanatory diagram showing a configuration of command data and management data used in the serial semiconductor memory according to the present embodiment;
FIG. 3 is a timing chart for explaining a data read operation in a normal read mode and a bit string designation read mode.
FIG. 4 is an explanatory diagram showing a memory map when the serial semiconductor memory according to the present embodiment is applied to a management system;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory matrix part 2 ... Serial / parallel conversion circuit 3 ... Control circuit 4 ... Address decoder 5 ... Address counter 7 ... Data selector 8 ... Switching circuit So ... External data bus Si ... Serial data bus Sb ... Data line

Claims (2)

Stores stored data in units of multiple bits corresponding to each address, and receives the read command of stored data by command data set from outside, converts the stored data in units of multiple bits accessed to memory into a bit string In serial semiconductor memory that outputs in series,
When the command data not including a specific bit read command is received, the memory-accessed storage data is transmitted in a bit string for each bit, and when a specific bit read command is received by the command data, the memory accessed A bidirectional shift register that outputs stored data in units of multiple bits;
A data selector for sending only the specified bit among the storage data output from the bidirectional shift register when reading the specified bit specified by the command data ;
A serial semiconductor memory comprising data transfer processing means having The data transfer processing means includes:
When receiving a write instruction of a specific bit by the command data, via said bidirectional shift register of claim 1, by transferring the write data only to the designated specific bit, characterized in that memory access Serial semiconductor memory.

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