JP4084541B2 - The method of manufacturing a semiconductor crystal and semiconductor light-emitting element - Google Patents

The method of manufacturing a semiconductor crystal and semiconductor light-emitting element Download PDF

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JP4084541B2
JP4084541B2 JP2001036604A JP2001036604A JP4084541B2 JP 4084541 B2 JP4084541 B2 JP 4084541B2 JP 2001036604 A JP2001036604 A JP 2001036604A JP 2001036604 A JP2001036604 A JP 2001036604A JP 4084541 B2 JP4084541 B2 JP 4084541B2
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protrusion
crystal growth
substrate
crystal
semiconductor
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JP2002241192A (en
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一義 冨田
誠二 永井
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株式会社豊田中央研究所
豊田合成株式会社
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【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより結晶成長基板を得る、半導体結晶の製造方法に関する。 The present invention utilizes a lateral crystal growth effect, obtaining a crystal growth substrate by forming a substrate layer made of a Group III nitride compound semiconductor on a base substrate, a manufacturing method of the semiconductor crystal.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
図5に例示する様に、例えばシリコン(Si)等から成る下地基板上に窒化ガリウム(GaN)等の窒化物半導体を結晶成長させ、その後常温まで冷却すると、窒化物半導体層に転位やクラックが多数入ることが一般に知られている。 As illustrated in FIG. 5, for example, silicon (Si) nitride semiconductor gallium nitride (GaN) or the like base substrate made of such as by crystal growth, after which the cooled to room temperature, dislocations and cracks in the nitride semiconductor layer able to enter a large number are generally known.
【0003】 [0003]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
この様に、成長層(窒化物半導体層)に転位やクラックが多数入ると、その上にデバイスを作製した場合に、デバイス中に格子欠陥や転位、変形、クラック等が多数生じる結果となり、デバイス特性の劣化を引き起こす原因となる。 Thus, the dislocations and cracks in the grown layer (nitride semiconductor layer) enters a number, when making a device thereon, lattice defects and dislocations in the device, deformation, results in a crack or the like is generated number, device responsible for causing the deterioration of the characteristics.
また、例えばシリコン(Si)等から成る下地基板を除去し、成長層のみを残して、独立した基板(結晶)を得ようとする場合、上記の転位やクラック等の作用により、大面積(1cm 2以上)のものが得られない。 Further, for example, silicon (Si) the underlying substrate is removed consisting of such, leaving only growth layer, in order to obtain an independent substrate (crystal) by the action such as the dislocation and cracks, large area (1cm 2 or more) can not be obtained ones.
【0004】 [0004]
本発明は、上記の課題を解決するために成されたものであり、その目的は、クラックが無く、転位の密度が低い高品質の半導体結晶(結晶成長基板)を得ることである。 The present invention has been made to solve the above problems, an object of cracks without is to obtain high quality semiconductor crystal low density of dislocations (crystal growth substrate).
【0005】 [0005]
【課題を解決するための手段、並びに、作用及び発明の効果】 Means for Solving the Problems, and the effect of the action and the Invention
上記の課題を解決するためには、以下の手段が有効である。 In order to solve the aforementioned problem, the following measures are effective.
即ち、第1の手段は、横方向結晶成長作用を利用して下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより下地基板から独立した半導体結晶を得る製造工程において、下地基板上に多数の突起部を形成する突起部形成工程と、この突起部の表面の少なくとも一部を基板層が結晶成長を開始する最初の成長面としてこの成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで基板層を結晶成長させる結晶成長工程と、突起部を破断することにより基板層と下地基板とを分離する分離工程とを設け、基板層と下地基板とを冷却または加熱することにより、基板層と下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して上記の突起部の破断を実施することである。 That is, the first means, in a manufacturing process to obtain a separate semiconductor crystal from the starting substrate by forming a substrate layer made of a Group III nitride compound semiconductor by using a lateral crystal growth effect on the underlying substrate, a protrusion forming step of forming a plurality of protrusions on a base substrate, at least the growth surface as the first growth surface of the substrate layer starts to crystal growth at least a part of the surface of the projecting portion is connected respectively to each other a crystal growth step of the crystal growth substrate layer to grow into a series of substantially planar, and a separation step of separating the substrate layer and the underlying substrate provided by breaking a protrusion, the substrate layer and the underlying substrate cooling or by heating, the stress based on the difference in thermal expansion coefficient between the substrate layer and the underlying substrate is generated, it is to implement the break of the protrusions by using this stress.
【0006】 [0006]
ただし、ここで言う「III族窒化物系化合物半導体」一般には、2元、3元、又は4元の「Al x Ga y In (1-xy) N(0≦x≦1,0≦y≦1,0≦x+y≦1)」成る一般式で表される任意の混晶比の半導体が含まれ、更に、p型或いはn型の不純物が添加された半導体も、本明細書の「III族窒化物系化合物半導体」の範疇とする。 However, here referred to the "Group III nitride compound semiconductor" Generally, binary, ternary, or quaternary "Al x Ga y In (1- xy) N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) "includes semiconductors any mixing ratio represented by the general formula comprising, further, p-type or even n-type semiconductor to which an impurity is added in," group III hereof the scope of the nitride-based compound semiconductor. "
また、上記のIII族元素(Al,Ga,In)の内の一部をボロン(B)やタリウム(Tl)等で置換したり、或いは、窒素(N)の一部をリン(P)、砒素(As)、アンチモン(Sb)、ビスマス(Bi)等で置換したりした半導体等もまた、本明細書の「III族窒化物系化合物半導体」の範疇とする。 Also, or replace the above group III element (Al, Ga, In) a portion of the boron (B) or thallium (Tl) or the like, or nitrogen phosphorous part of (N) (P), arsenic (as), antimony (Sb), bismuth (Bi) semiconductor, etc. were or substituted by an also a category of "group III nitride compound semiconductor" in this specification.
また、上記のp型の不純物としては、例えば、マグネシウム(Mg)や、或いはカルシウム(Ca)等を添加することができる。 As the p-type impurity of the above, for example, it can be added magnesium (Mg) or, or calcium (Ca) or the like.
また、上記のn型の不純物としては、例えば、シリコン(Si)や、硫黄(S)、セレン(Se)、テルル(Te)、或いはゲルマニウム(Ge)等を添加することができる。 Further, as the impurity of the n-type, for example, silicon (Si), sulfur (S), selenium (Se), can be added tellurium (Te), or germanium (Ge) or the like.
また、これらの不純物は、同時に2元素以上を添加しても良いし、同時に両型(p型とn型)を添加しても良い。 These impurities may be added two or more elements simultaneously, it may be added both types (p-type and n-type) at the same time.
【0007】 [0007]
例えば、図1に例示する様に、多数の突起部を有する下地基板上にIII族窒化物系化合物より成る基板層(半導体結晶)を成長させる場合、突起部の大きさや配置間隔や結晶成長諸条件等を調整することにより、各突起部間(突起部の側方)に、半導体結晶が積層されていない「空洞」が形成可能となる。 For example, as illustrated in FIG. 1, when growing a large number of substrate layers made of Group III nitride compound on a base substrate having a projecting portion (semiconductor crystals), size, arrangement interval and the crystal growth of the protrusions various by adjusting the conditions, between the protrusions (the side of the projections), the semiconductor crystal is not stacked "cavity" is be formed. このため、突起部の高さに比して基板層の厚さを十分に大きくすれば、内部応力または外部応力がこの突起部に集中的に作用し易くなる。 Therefore, if sufficiently large thickness of the substrate layer than the height of the protrusions, the internal stress or external stress is likely to act intensively on the protrusion. その結果、特にこれらの応力は、突起部に対する剪断応力等として作用し、この応力が大きくなった時に、突起部が破断する。 As a result, in particular, these stresses act as shear stress or the like for the projections, when the stress is increased, the protrusion may be broken. 従って、この応力を利用すれば、容易に下地基板と基板層とを分離(剥離)することが可能となる。 Therefore, given the benefit of this stress, it becomes possible to easily and starting substrate and the substrate layer separating (peeling). この手段により、下地基板から独立した結晶(基板層)を得ることができる。 This means, it is possible to obtain separate crystalline from the starting substrate (substrate layer).
また、上記の「空洞」が大きく形成される程、突起部に応力(剪断応力)が集中し易くなる。 Further, degree of "cavity" above are larger, they tend to concentrate stress (shear stress) in the protrusion.
【0008】 [0008]
また、例えば、図1からも分かる様に、上記の様な突起部を形成することにより、下地基板と基板層(又は、所望の半導体結晶層)との接触部位が狭く限定されるため、両者の格子定数差に基づく歪が生じ難くなり、「下地基板と基板層の間の格子定数差に基づく応力」が緩和される。 Further, for example, as can be seen from Figure 1, by forming the protruding portions, such as described above, since the base substrate and the substrate layer (or, a desired semiconductor crystal layer) is the site of contact as limited narrowly, both hardly distortion occurs based on a lattice constant difference, "stress based on the difference in lattice constant between the underlying substrate and the substrate layer" is relaxed. このため、基板層(所望の半導体結晶)が結晶成長する際に、成長中の基板層に働く不要な応力が抑制されて転位やクラックの発生密度が低減される。 Therefore, the substrate layer (desired semiconductor crystals) in crystal growth, generation density of dislocations and cracks unnecessary stress can be suppressed to act on the substrate layer during growth is reduced.
【0009】 [0009]
尚、下地基板と基板層とを分離(剥離)する際に、下地基板側に基板層の一部が残っても良いし、或いは、基板層側に下地基板の一部(例:突起部の破断残骸)が残っても良い。 Incidentally, when the starting substrate and the substrate layer separating (peeling) may remain part of the substrate layer to the underlying substrate, or a portion of the underlying substrate on the substrate layer side (e.g. the projections break debris) may remain. 即ち、上記の分離工程は、これらの材料の一部の残骸を皆無とする様な各材料の完全な分離を前提(必要条件)とするものではない。 That is, the separation step is not intended to complete separation of each such as to eradicate some debris of these materials materials assuming (necessary condition).
【0010】 [0010]
また、 基板層と下地基板との熱膨張係数差に基づく応力を容易に生成することが可能となる。 Further, it is possible to easily generate a stress based on the difference in thermal expansion coefficient between the substrate layer and the underlying substrate.
【0011】 [0011]
また、 第2の手段は、横方向結晶成長作用を利用して下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより半導体結晶を得る製造工程において、下地基板上に多数の突起部を形成する突起部形成工程と、この突起部の表面の少なくとも一部を基板層が結晶成長を開始する最初の成長面としてこの成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで基板層を結晶成長させる結晶成長工程とを設け、この結晶成長工程においてIII族窒化物系化合物半導体の原料供給量qを調整することにより、下地基板の突起部間の谷部の少なくとも一部の露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aと、突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することである。 The second means is the manufacturing process to obtain a semiconductor crystal by forming a substrate layer formed by utilizing the lateral crystal growth effect on the underlying substrate of a Group III nitride-based compound semiconductor, a large number on a base substrate of the projecting portion forming step of forming a protrusion, at the beginning of this growth surface are respectively connected to one another as the growth surface at least a set of substantially planar, at least a portion of the substrate layer starts to crystal growth on the surface of the protrusion a crystal growth step of growing crystals of the substrate layer to be grown is provided, by adjusting the material supply amount q of the group III nitride compound semiconductor in this crystal growth step, at least the valleys between protrusions of the base substrate and the crystal growth rate a group III nitride compound semiconductor in a portion of the exposed region, is to control the substantially maximum value the difference (b-a) between the crystal growth rate b at the top of the protrusion.
【0012】 [0012]
この手段によれば、突起部の頭頂部付近の結晶成長速度が相対的に大きくなり、上記の露出領域付近の結晶成長は比較的抑制されて、頭頂部付近からの結晶成長が支配的となる。 According to this means, the crystal growth rate in the vicinity of the top portion of the protrusion becomes relatively large, the crystal growth of the vicinity of the exposed region is relatively suppressed, crystal growth from the vicinity of the top portion is dominant . この結果、突起部の頭頂部付近から開始される基板層の横方向成長(ELO)が顕著となり、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和される。 As a result, the lateral growth of the substrate layer is started from the vicinity of the top portion of the protrusion (ELO) becomes remarkable, based on the lattice constant difference between the work in the substrate layer during crystal growth of the substrate layer "starting substrate and the substrate layer stress "is relaxed. 従って、基板層の結晶構造が安定し、基板層に転位やクラックが発生し難くなる。 Therefore, the crystal structure of the substrate layer is stabilized, dislocations and cracks hardly occur in the substrate layer.
また、基板層の横方向成長(ELO)が顕著となれば、例えば、突起部の側方(各突起部間)に比較的大きな空洞ができる場合もある。 Further, if the lateral growth of the substrate layer (ELO) is remarkable, for example, it can sometimes be a relatively large cavity on the side of the projections (between the protrusions).
【0013】 [0013]
例えば、図1に例示する様に、適当な大きさ、間隔、或いは周期で下地基板の表面上に凹凸を形成した場合、一般に、下地基板の外周側壁付近の周辺部分以外では、凸部(突起部)の上面付近に比べて、凹部(谷部)の方が結晶材料の単位時間・単位面積当たりの供給量は少なくなり易い。 For example, as illustrated in FIG. 1, an appropriate size, spacing, or in the case of forming the unevenness on the surface of the base substrate with a period, generally, other than the peripheral portion near the peripheral side wall of the base substrate, convex portions (projections compared to the vicinity of the upper surface of the part), the recess (supply amount of unit time and per unit area of ​​the crystal material towards valleys) tends to be reduced. この傾向は、結晶材料のガス流の流量、温度、方向等にも依存するが、これらの諸条件を最適、或いは好適に制御することにより、上記の差分(b−a)を略最大値に制御することが可能となる。 This tendency, the flow rate of the gas flow of the crystal material, the temperature, but also on the direction or the like, these conditions optimum, or by suitably controlling the above difference of (b-a) into a substantially maximum value it is possible to control.
【0014】 [0014]
また、 第3の手段は、上記の第1の手段の結晶成長工程において、III族窒化物系化合物半導体の原料供給量qを調整することにより、下地基板の突起部間の谷部の少なくとも一部の露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aと、突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することである。 The third means, in the crystal growth process of the first means of the, III nitride compound by adjusting the material supply amount q of the semiconductor, at least one valley between the projections of the underlying substrate crystal and growth rate a group III nitride compound semiconductor in the exposed regions of the part, is to control the substantially maximum value the difference (b-a) between the crystal growth rate b at the top of the protrusion.
【0015】 [0015]
この場合にも、上記の手段と同様に、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和され、基板層の結晶構造が安定し、基板層に転位やクラックが発生し難くなる。 In this case also, similarly to the above means, acting on the substrate layer during crystal growth of the substrate layer is relaxed "stress based on the difference in lattice constant between the underlying substrate and the substrate layer," the crystal structure of the substrate layer is stable , dislocations and cracks hardly occur in the substrate layer. この作用・効果は、各突起部間(突起部の側方)に空洞ができる程に横方向成長が顕著な場合に、比較的顕著となる。 The operation and effect, when lateral growth to the extent that it is hollow is noticeable between the protrusions (side of the protrusion), a relatively conspicuous.
また、突起部の側方(各突起部間)に空洞が形成されれば、突起部に剪断応力が集中し易くなり、上記の分離工程において下地基板と基板層とを剪断応力により分離し易くなる。 Further, if the cavity is formed on the side of the projections (between the protrusions), shear stress on the projecting portion is likely to concentrate, easily and starting substrate and the substrate layer was separated by shear stress in the separation step Become. この作用・効果は、各突起部間(突起部の側方)の空洞が大きくなる程、顕著となる。 The operation and effect, as the cavity becomes large between the protrusions (side of the protrusion), becomes remarkable.
【0016】 [0016]
また、 第4の手段は、上記の第2または第3の手段において、上記の原料供給量qを1μmol/min以上、100μmol/min以下とすることである。 The fourth means is in the second or third means of said, the material supply amount q of the 1 [mu] mol / min or more, is to less 100 [mu] mol / min.
【0017】 [0017]
より望ましくは、上記の原料供給量qは、5μmol/min以上、90μmol/min以下が良い。 More preferably, the raw material supply amount q The above, 5 [mu] mol / min or more, or less good 90 [mu] mol / min. 更に望ましい値としては、形成される突起部の大きさや形、配置間隔等の下地基板の仕様や、供給原料の種類や供給流方向、結晶成長法等の諸条件にも依るが、概ね10〜80μmol/min程度が理想的である。 Still desired value, the size and shape of the protrusions is formed, the specification and the underlying substrate, such as arrangement interval, feedstock type and feed direction, depending on the conditions such as crystal growth method, generally 10 to about 80μmol / min is ideal. この値は、大き過ぎると上記の差分(b−a)を略最大値に制御することが難しくなるので、各突起部間(突起部の側方)に大きな空洞を形成することが難しくなる。 Since this value is too large to control said difference a (b-a) into a substantially maximum value is difficult, it is difficult to form a large cavity between the protrusions (side of the protrusion). 従って、この様な場合には、格子定数差に基づく結晶内の応力が比較的緩和され難く、転位が発生する等、基板層の単結晶の結晶性が劣化し易くなってしまい望ましくない。 Therefore, in such a case, the stress in the crystal based on the lattice constant difference hardly can be relatively relaxed, like dislocation occurs, the crystallinity of the single crystal substrate layer undesirably becomes liable to deteriorate.
【0018】 [0018]
また、応力(剪断応力)により、下地基板と基板層とを分離する際にも、突起部側方の空洞が無いか或いはこの空洞が小さいと、突起部に応力が集中し難くなり、突起部の破断が起り難くなってしまい望ましくない。 Further, the stress (shear stress), even when separating the base substrate and the substrate layer, the protrusion side is or is smaller this cavity without cavities, the stress is hardly concentrated on the protrusion, the protrusion undesirable becomes difficult to occur is broken.
一方、原料供給量qが小さ過ぎると、結晶成長時間が掛かり過ぎて生産性の面で不利となり、望ましくない。 On the other hand, when the material supply amount q is too small, it is disadvantageous in terms of productivity and crystal growth time too long, undesirable.
【0019】 [0019]
また、 第5の手段は、上記の第1乃至第4の何れか1つの手段において、下地基板の材料として、シリコン(Si)または炭化シリコン(SiC)を用いることである。 The fifth means, in the first to fourth any one means described above, as the material of the base substrate, is the use of silicon (Si) or silicon carbide (SiC).
また、その他の下地基板の材料としては、例えば、GaN,AlN,GaAs,InP,GaP,MgO,ZnO,MgAl 24等が有用で、また、サファイア、スピネル、酸化マンガン、酸化ガリウムリチウム(LiGaO 2 )、硫化モリブデン(MoS)等も使用可能である。 Further, as the material of the other of the base substrate, for example, GaN, AlN, GaAs, InP , GaP, MgO, ZnO, MgAl 2 O 4 or the like is useful, also, sapphire, spinel, manganese oxide, gallium oxide lithium (LiGaO 2) it can be used also such as molybdenum sulfide (MoS).
ただし、熱膨張係数差に基づく剪断応力を用いて下地基板と基板層とを分離する場合には、両材料間の熱膨張係数差が小さくならない組み合わせを選択することが望ましく、また、下地基板側には、破断が起り易い材料を選択することが望ましい。 However, when separating the base substrate and the substrate layer using a shear stress due to thermal expansion coefficient difference, it is desirable to select a combination of thermal expansion coefficient difference between the two materials is not reduced, also, the base substrate the, it is desirable to select a material easily occur fracture.
【0020】 [0020]
また、 第6の手段は、上記の第1乃至第5の何れか1つの手段において、下地基板の材料としてSi(111)を用い、突起部形成工程において下地基板の突起部間の谷部の露出領域にSi(111)面が露出しない様に突起部を形成することである。 Further, a sixth means, in the first to fifth any one means described above, using a Si (111) as the material of the base substrate, the valleys between the protrusions of the base substrate in the protrusion forming step Si (111) plane on the exposed region is to form the protrusion so as not to expose.
本手段によれば、上記の谷部の露出面の結晶成長速度aを小さく抑制できるため、上記の差分(b−a)を、結晶性を維持したまま安定的に略最大化することが可能となる。 According to this means, since it is possible to reduce suppress the crystal growth rate a of the exposed surface of the valley, the above difference of (b-a), can be stably substantially maximized while maintaining the crystalline to become.
【0021】 [0021]
また、 第7の手段は、上記の第1乃至第6の何れか1つの手段の突起部形成工程後に、少なくとも突起部の表面に「Al x Ga 1-x N(0<x≦1)」より成るバッファ層を形成する工程を設けることである。 Further, means 7, after the protrusion forming step of any one of the first to sixth of the at least on the surface of the protrusion "Al x Ga 1-x N ( 0 <x ≦ 1) " it is to provide a process of forming a more composed buffer layer.
【0022】 [0022]
ただし、上記のバッファ層とは別に、更に、上記のバッファ層と略同組成(例:AlNや、AlGaN)の中間層を周期的に、又は他の層と交互に、或いは、多層構造が構成される様に、積層しても良い。 However, apart from the above-mentioned buffer layer, further, the above buffer layer and substantially the same composition (eg and AlN, AlGaN) intermediate layer periodically, or alternating with other layers, or a multilayer structure configured as is, it may be laminated.
【0023】 [0023]
この様なバッファ層(或いは、中間層)の積層により、格子定数差に起因する基板層(成長層)に働く応力を緩和できる等の従来と同様の作用原理により、結晶性を向上させることが可能となる。 Such buffer layer (or intermediate layer) by stacking, the conventional manner of working principle, such as that can alleviate the stress acting on the substrate layer due to lattice constant difference (growth layer), to improve the crystallinity It can become.
【0024】 [0024]
また、 第8の手段は、上記の第7の手段において、バッファ層の膜厚を突起部の縦方向の高さ以下に成膜することである。 Also, eighth means, in the seventh means described above is that the deposition of the film thickness of the buffer layer below the height of the longitudinal protrusion. また、絶対的な目安としては、バッファ層の膜厚は、およそ0.01μm以上、1μm以下が望ましい。 As the absolute measure, the thickness of the buffer layer is approximately 0.01μm or more, or less desirably 1 [mu] m.
この手段により、バッファ層の上に形成される所望の結晶層(例:GaN層)のみを良質に横方向に成長させることができる。 By this means, desired crystal layer formed on the buffer layer: can be grown only good quality in the transverse direction (eg GaN layer). 即ち、この手段により、バッファ層の上に形成される結晶層に結晶成長時に掛かる「格子定数差に基づく応力」が軽減され、転位密度が効果的に低減できる。 That is, by this means, applied during the crystal growth in the crystal layer formed on the buffer layer "stress based on the lattice constant difference" is reduced, the dislocation density can be effectively reduced.
【0025】 [0025]
バッファ層等を形成するAlNやAlGaN等は、下地基板の露出した表面の略全面に成膜され易く、また、元来、所望の結晶の成長層等を形成するGaNの方が、AlNやAlGaN等よりも横方向成長し易い傾向に有る様だが、上記の手段によれば、より確実に大きな「空洞」を突起部の側方に形成することができる。 AlN and AlGaN or the like to form a buffer layer or the like is liable to be deposited on substantially the entire surface of the exposed surface of the underlying substrate, also originally found the following GaN forming the growth layer and the like of the desired crystal, AlN or AlGaN as there laterally grown tendency than equal, but according to the above means, it is possible to form the side of the protrusion large "cavity" more reliably.
【0026】 [0026]
また、この手段により、基板層を下地基板から分離した際に、基板層の裏面(下地基板が有った側の面)にも、結晶層(バッファ層の上に形成される所望の層)が直に広範囲に露出する。 Also, by this means, when separating the substrate layer from the starting substrate, on the back surface (the surface of the base substrate there side) of the substrate layer, the crystal layer (desired layer to be formed on the buffer layer) There is exposed directly extensively. 従って、基板層の裏面に電極を形成する際に、電気抵抗を抑制することが容易となる。 Therefore, when forming the electrode on the back surface of the substrate layer, it is easy to suppress the electrical resistance.
【0027】 [0027]
尚、バッファ層の膜厚は、上記の通りおよそ0.01μm〜1μm程度が概ね妥当な範囲であるが、より望ましくは、0.1μm以上、0.5μm以下が良い。 The thickness of the buffer layer is as approximate 0.01μm~1μm about above are generally reasonable range, more preferably, 0.1 [mu] m or more, it is 0.5μm or less. この膜厚が厚過ぎると、空洞が小さくなり易くなり望ましくない。 When the thickness is too thick, undesirable liable cavity decreases. また、この膜厚を薄くし過ぎると、略均一にバッファ層を成膜することが困難となる。 Moreover, an excessively thin film thickness becomes substantially uniform difficult to depositing the buffer layer. 特に、突起部の上部付近においてバッファ層の成膜ムラ(十分に成膜されない部位)が生じると、結晶性にもムラが生じ易くなり、望ましくない。 In particular, the irregularity in film formation of the buffer layer (a portion not sufficiently deposited) occurs in the vicinity of the upper portion of the protrusion also tends to occur unevenness in crystallinity, undesirably.
【0028】 [0028]
また、 第9の手段は、上記の第1乃至第8の何れか1つの手段の結晶成長工程において、基板層の膜厚を50μm以上とすることである。 Further, the ninth means, in the crystal growth process of any one of the first to eighth above, is that the thickness of the substrate layer and the above 50 [mu] m.
【0029】 [0029]
結晶成長させる基板層(III族窒化物系化合物半導体)の厚さは、約50μm以上が望ましく、この厚さが厚い程、基板層に対する引っ張り応力が緩和されて、基板層の転位やクラックの発生密度を減少できる。 The thickness of the substrate layer where crystal growth (III nitride compound semiconductor) is preferably not less than about 50 [mu] m, the higher the thickness is thicker, is tensile stress relaxation to the substrate layer, generation of dislocations and cracks of the substrate layer It can reduce the density. また、更には、同時に基板層を強固にでき、上記の剪断応力を上記の突起部に集中させ易くなる。 Further, even, at the same time it can be a substrate layer firmly, easily the shear stress is concentrated to the projecting portion of the.
【0030】 [0030]
また、 第10の手段は、上記の第1乃至第9の何れか1つの手段の結晶成長工程において、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することである。 Further, means 10, in the crystal growth step of the first to ninth any one means described above, the slow crystal growth rate crystal growth method, the fast crystal growth rate crystal growth method, crystals in the middle it is to change the growth method.
【0031】 [0031]
例えば、結晶成長面が一連の略平面状に成るまでは、上記の差分(b−a)を略最大にし易い結晶成長法(例:MOVPE法)を採用し、その後は、膜厚を効率よく50μm以上にすることが容易な結晶成長法(例:HVPE法)を採用すれば、短時間に結晶性の良質な半導体結晶を得ることが可能となる。 For example, until the crystal growth surface is made into a series of generally planar, said difference (b-a) was substantially the maximum likely crystal growth method (eg: MOVPE method) adopted, then, efficiently thickness easy crystal growth method can be at least 50 [mu] m: by employing the (example HVPE method), it is possible to obtain a short time crystalline quality semiconductor crystal.
【0032】 [0032]
また、 第11の手段は、上記の第1乃至第10の何れか1つの手段の突起部形成工程において、突起部が略等間隔又は略一定周期で配置される様に上記の突起部を形成することである。 Further, means 11 are formed in the projecting portion forming step of any one of the first to tenth mentioned above, the protrusions as the projections are arranged at substantially equal intervals or substantially constant period It is to be.
【0033】 [0033]
これにより、横方向成長の成長条件が全体的に略均等となり、結晶性の良否にムラが生じ難くなる。 Thus, growth conditions of lateral growth overall becomes substantially equal, unevenness hardly occurs in crystalline quality. また、突起部間の谷部の上方が、基板層によって完全に覆われるまでの時間に、局所的なバラツキが生じ難くなるため、例えば、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更する場合に、その時期を的確に、早期に、或いは一意に決定することが容易となる。 Further, the upper valley between protrusions, the time until completely covered by the substrate layer, it becomes difficult to cause local variation, for example, the crystal from the growth rate slow crystal growth method, the crystal growth rate fast crystal growth method, when changing the crystal growth method in the middle, precisely the time, early, or can be easily determined uniquely.
また、本手段により、上記の空洞が各々略均等な大きさとなり、上記の剪断応力を各突起部に略均等に分配することが可能となるため、全突起部の破断がムラなく生じ、下地基板と基板層との分離が確実に実施できる様になる。 Further, the present device, the cavity of said becomes each substantially equal size, since the shear stress becomes possible to substantially uniformly distributed to the protrusions, the breaking of all the projections occurs evenly, base separation of the substrate and the substrate layer is such can be carried out reliably.
【0034】 [0034]
また、 第12の手段は、上記の第11の手段の突起部形成工程において、1辺が0.1μm以上の略正三角形を基調とする2次元三角格子の格子点上に突起部を形成することである。 Further, a twelfth means, in the projecting portion forming step of the eleventh means, to form a protrusion on a lattice point of a two-dimensional triangular lattice one side of tones and substantially equilateral triangle than 0.1μm it is.
この手段により、上記の第11の手段をより具体的に正確、確実に実施でき、よって、転位の数を確実に低減することができる。 By this means, the first means 11 of the more specific accurate, can be reliably performed, thus, it is possible to reliably reduce the number of dislocations.
【0035】 [0035]
また、 第13の手段は、上記の第1乃至第12の何れか1つの手段の突起部形成工程において、突起部の水平断面形状を、略正三角形、略正六角形、略円形、又は四角形に形成することである。 Further, it means 13, in the projecting portion forming step of the first to twelfth any one means described above, the horizontal cross-sectional shape of the protrusion, substantially equilateral triangle, substantially regular hexagon, substantially circular, or square formation that is to.
この手段により、III族窒化物系化合物半導体より形成される結晶の結晶軸の方向が各部で揃い易くなるため、或いは、任意の水平方向に対して突起部の水平方向の長さ(太さ)を略一様に制限できるため、転位の数を抑制することができる。 By this means, since the direction of the crystal axis of the crystal formed from the Group III nitride compound semiconductor is easily aligned with each unit, or the horizontal length of the protrusion with respect to an arbitrary horizontal direction (thickness) since it substantially uniformly limit, it is possible to suppress the number of dislocations. 特に、正六角形や正三角形は、半導体結晶の結晶構造と合致し易いのでより望ましい。 In particular, regular hexagon or an equilateral triangle is more preferable because it is easy to match the crystal structure of the semiconductor crystal. また、円形や四角形は製造技術の面で形成し易いと言う、現行一般の加工技術水準の現状に照らしたメリットが有る。 Further, the circular or square say easily formed in terms of manufacturing technology, there is merit in the light of the current state of processing technology level of the current general.
【0036】 [0036]
また、 第14の手段は、上記の第1乃至第13の何れか1つの手段の突起部形成工程において、突起部の配置間隔(配置周期)を0.1μm以上、10μm以下とすることである。 Further, means 14, in the projecting portion forming step of any one of the first to thirteenth mentioned above, the arrangement interval of the protrusions (the arrangement period) of 0.1μm or more is that it 10μm or less . より望ましくは、結晶成長の実施条件にも依存するが、突起部の配置間隔は、0.5〜8μm程度が良い。 More preferably, although depending on the implementation conditions of crystal growth, the arrangement interval of the protrusions is about 0.5~8μm good. ただし、この配置間隔とは、互いに接近する各突起部の中心点間の距離のことを言う。 However, the the arrangement interval refers to the distance between the center points of the protrusions which approach each other.
【0037】 [0037]
この手段により、突起部の谷部の上方を基板層で覆うことが可能となると同時に、突起部間に空洞を形成することが可能となる。 By this means, at the same time above the valley of the projection portion can be covered with a substrate layer, it is possible to form a cavity between the projections.
この値が小さ過ぎると、ELOの作用が殆ど得られなくなり、結晶性が劣化する。 If this value is too small, the effect of ELO almost obtained no longer, crystallinity is deteriorated. また、形成される空洞が小さくなり過ぎて、基板層の膜厚を必要以上に大きくしない限り、突起部を破断することが容易でなくなる。 In addition, the cavity is too small to be formed, unless the large thickness of the substrate layer than necessary, so it is not easy to break the protrusion.
【0038】 [0038]
また、この値が大きくなり過ぎると、確実に突起部の谷部の上方を基板層で覆うことができなくなり、結晶性が均質かつ良質の結晶(基板層)が得られなくなる。 Also, if this value is too large, certainly becomes the upper valley of the protrusion can not be covered with the substrate layer, crystallinity homogeneous and good quality crystal (substrate layer) can not be obtained.
或いは、この値が更に大き過ぎると、谷部の露出面が広大となり過ぎて、ELOの作用が殆ど得られなくなり、また、空洞が全く形成されなくなるため、結晶性が劣化し、また、基板層の膜厚を必要以上に大きくしない限り、突起部を破断することが容易でなくなる。 Alternatively, if this value is too further large, too a large exposed surface of the valley, the action of the ELO can not be obtained mostly, also, since the cavity is not formed at all, the crystallinity is deteriorated, and a substrate layer unless unnecessarily large thickness of, not easy to break the protrusion.
【0039】 [0039]
また、 第15の手段は、上記の第1乃至第14の何れか1つの手段の突起部形成工程において、突起部の縦方向の高さを0.5μm以上、20μm以下とすることである。 Further, fifteenth means, in projecting portion forming step of any one of the first to fourteenth above, the vertical height of the projections 0.5μm or more is that it 20μm or less. より望ましくは、結晶成長の実施条件にも依存するが、突起部の縦方向の高さは、0.8〜5μm程度が良い。 More preferably, although depending on the implementation conditions of crystal growth, the vertical height of the protrusions is about 0.8~5μm good.
この高さが短過ぎると、突起部が無い場合と同様に、ELOの作用が殆ど得られなくなり、結晶性が劣化する。 If the height is too short, as if there is no protruding portion, the action of the ELO almost obtained no longer, crystallinity is deteriorated. また、この高さが短過ぎると、上記の空洞が形成されなくなる。 Further, when the height is too short, the cavity of the can not be formed.
また、この高さが高過ぎると、突起部の形成自身が困難となったり、突起部の形成に必要以上に時間がかかったり、下地基板の材料が必要以上に消費されたりして望ましくない。 Further, when the height is too high, or a difficult to form its protrusions, it takes longer than necessary for the formation of the protrusion, unwanted or consumed unnecessarily underlying substrate material. また、この高さが高過ぎると、剪断応力が突起部の縦方向に分散されてしまい、突起部を確実に破断させることが難しくなる。 Further, when the height is too high, the shear stress will be dispersed in the longitudinal direction of the protrusion, it is difficult to reliably break the protrusion.
【0040】 [0040]
また、 第16の手段は、上記の第1乃至第15の何れか1つの手段の突起部形成工程において、突起部の横方向の太さ、幅、又は直径を0.1μm以上、10μm以下とすることである。 Further, it means 16, in the projecting portion forming step of any one of the first to fifteenth mentioned above, the lateral width of the protrusion, the width or diameter of 0.1μm or more, and 10μm or less It is to be. より望ましくは、結晶成長の実施条件にも依存するが、突起部の横方向の太さ、幅、又は直径は、0.5〜5μm程度が良い。 More preferably, although depending on the implementation conditions of crystal growth, the lateral thickness of the protrusions, the width, or diameter, of about 0.5~5μm good.
この太さが太過ぎると、格子定数差に基づいて基板層(成長層)に働く応力の影響が大きくなり、基板層の転位数が増加し易くなる。 When the thickness is too thick, the influence of the stress acting on the substrate layer (growth layer) on the basis of the lattice constant difference becomes large, number of dislocations substrate layer is likely to increase. また、細過ぎると、突起部自身の形成が困難となるか、或いは、突起部の頭頂部の結晶成長速度bが遅くなり、望ましくない。 Also, if too thin, or the formation of the protrusion itself becomes difficult, or the crystal growth rate b of the top portion of the protrusion it becomes slow, undesirable.
【0041】 [0041]
また、応力(剪断応力等)により突起部を破断させる際にも、突起部の横方向の太さ、幅、又は直径が大き過ぎると、確実に破断されない部分が生じ易くなり、望ましくない。 Further, even when to break the projections by stress (shear stress, etc.), the lateral width of the protrusion, width, or diameter is too large, easily not be reliably ruptured portion occurs, undesirable.
また、格子定数差に基づいて基板層(成長層)に働く応力の影響の大小は、突起部の横方向の太さ(長さ)だけに依るものではなく、突起部の配置間隔等にも依存する。 Also, the magnitude of the influence of the stress acting on the substrate layer (growth layer) on the basis of the lattice constant difference is not due only to the thickness of the lateral projections (length), also the arrangement interval or the like of the projections Dependent. そして、これらの設定範囲が不適切であれば、上記の様に格子定数差に基づく応力の影響が大きくなり、基板層の転位数が増加し易くなり、望ましくない。 Then, if improperly these set range, influence of stress based on the lattice constant difference as described above becomes large, easily translocation speed of the substrate layer is increased, undesirably.
【0042】 [0042]
また、突起部の頭頂部付近の横方向の太さ、幅、又は直径には、上記の様に最適値又は適正範囲があるため、突起部の上面、底面、又は水平断面の形状は、少なくとも局所的に閉じた形状(島状)、更には、外側に向かって凸状に閉じた形状が良く、より望ましくは、この上面、底面、又は水平断面の形状は、略円形や略正多角形等が良い。 Further, the lateral thickness of the vicinity of the top portion of the protrusion, width, or diameter, because of the optimum value or the proper range as described above, the upper surface of the projecting portion, the bottom surface, or the shape of the horizontal cross-section, at least locally closed shape (island shape), and further, good shape closed convex outwardly, more preferably, the top surface, bottom surface, or the shape of the horizontal cross-section, substantially circular or substantially regular polygon etc. is good. この様な設定により、任意の水平方向に対して確実に、上記の最適値又は適正範囲を実現することが容易となる。 With such setting, to ensure against any horizontal direction, it is easy to realize the optimum value or the proper range.
【0043】 [0043]
また、 第17の手段は、上記の第1乃至第16の何れか1つの手段において、結晶成長工程よりも前に、各種エッチング、電子線照射処理、光学的処理、化学的処理、或いは切削や研磨その他の物理的処理により、下地基板の突起部間の谷部の少なくとも一部の露出領域の結晶性又は分子構造を劣化又は変化させることにより、この露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aを低下させることである。 Further, it means 17, in any one of the first to sixteenth above, before the crystal growth process, various etching, electron beam irradiation treatment, optical histological processing, chemical treatment, or cutting the or polishing other physical treatment, by degrading or changing the crystalline or molecular structure of at least a portion of the exposed region of the valleys between the protrusions of the base substrate, III-nitride compound semiconductor in this exposed region it is to reduce the crystal growth rate a.
この手段により、前記の結晶成長速度の差分(b−a)をより大きくすることができる。 By this means, the difference (b-a) of the crystal growth rate can be more increased. 従って、この手段によれば、突起部の頭頂部付近の結晶成長速度が相対的に大きくなるため、前記と同様の作用により、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和され、基板層に転位やクラックが発生し難くなる。 Therefore, according to this means, since the crystal growth rate in the vicinity of the top portion of the protrusion becomes relatively large, by the same action, acting on the substrate layer during crystal growth of the substrate layer "of the base substrate and the substrate layer stress "based on the lattice constant difference between is reduced, dislocations and cracks hardly occur in the substrate layer.
【0044】 [0044]
また、 第18の手段は、上記の何れか1つの分離工程において、下地基板と基板層とから成る基板を成長装置の反応室に残し、略一定流量のアンモニア(NH 3 )ガスを反応室に流したままの状態で、基板を概ね「−100℃/min〜−0.5℃/min」程度の冷却速度で略常温まで冷却することである。 Further, it means 18, in any one of the separation processes described above, leaving the substrate comprising a base substrate and the substrate layer in a reaction chamber of the deposition apparatus, a substantially constant flow rate of ammonia (NH 3) gas into the reaction chamber in a state of flowing, it is to cool to approximately ambient temperature of the substrate substantially at a cooling rate of about "-100 ℃ / min~-0.5 ℃ / min."
例えば、この様な手段により、基板層の結晶性を良質に維持したまま、前記の分離工程を実施することができる。 For example, by such means, the crystallinity of the substrate layer while maintaining good quality, it is possible to implement the separation step.
【0045】 [0045]
また、 第19の手段は、少なくとも、上記の何れか1つの分離工程よりも後に、基板層の裏面に残った突起部の破断残骸を化学的或いは物理的な加工処理により除去する残骸除去工程を設けることである。 Further, means 19 is at least later than the one of the separation processes described above, debris removal step of removing the rear surface to the remaining broken remnants of-chemical or physical processing of the protruding portion of the substrate layer the is to provide.
この手段によれば、基板層の裏面(下地基板を剥離させた側の面)に、半導体発光素子等の電極を形成した際に、電極と基板層との界面付近に生じる電流ムラや電気抵抗を抑制でき、よって駆動電圧の低減や、或いは発光強度の向上等を図ることができる。 According to this means, the back surface of the substrate layer (the surface that was peeled underlying substrate), when forming the electrode such as a semiconductor light-emitting element, a current variation and electrical resistance generated in the vicinity of the interface between the electrode and the substrate layer the can be suppressed, thus it is possible to achieve reduction and the driving voltage or to improve of light emission intensity and the like.
【0046】 [0046]
更に、突起部の破断残骸を除去することにより、電極を半導体発光素子等の反射鏡としても利用する際には、鏡面付近での光の吸収や散乱が低減されて反射率が向上するので、発光強度が向上する。 Further, by removing the broken remnants of the protrusion, when also used as a reflecting mirror such as a semiconductor light-emitting element electrode, the light absorption and scattering reflectance is reduced in the vicinity of the mirror surface is improved, the emission intensity is improved.
また、例えば、研磨等の物理的な加工処理によりこの残骸除去工程を実施した場合等には、基板層の裏面のバッファ層までをも取り除いたり、或いは、基板層の裏面の平坦度を向上したりすることもできるので、電流ムラや電気抵抗の抑制、或いは、鏡面付近での光の吸収や散乱の低減等の、上記の作用効果を更に補強することができる。 Further, for example, in the like case embodying the debris removal process by physical processing such as polishing, or even removed to the buffer layer of the back surface of the substrate layer, or to improve the flatness of the rear surface of the substrate layer since it is also possible to or suppression of the current unevenness and electrical resistance, or a reduction of the light absorption and scattering in the vicinity of the mirror surface can further reinforce the effect of the above.
【0047】 [0047]
【0048】 [0048]
また、 第20の手段は、上記の第1乃至第19の何れか1つの手段に依る半導体結晶の製造方法を用いて製造された半導体結晶を結晶成長基板とした結晶成長により、III族窒化物系化合物半導体発光素子を製造することである。 Further, first means 20 uses the crystal growth of the manufactured semiconductor crystal was crystal growth substrate by using the manufacturing method of the semiconductor crystal due to any one of the first to nineteenth mentioned above, III-nitride it is to produce a system compound semiconductor light-emitting device.
この手段によれば、結晶性が良質で、内部応力の少ない半導体より、III族窒化物系化合物半導体発光素子を製造することが可能又は容易となる。 According to this means, a good crystallinity, less semiconductor internal stress becomes possible or easier to manufacture a Group III nitride compound semiconductor light-emitting device.
以上の手段により、前記の課題を解決することができる。 By the above means, it is possible to solve the above problems.
【0049】 [0049]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明を具体的な実施例に基づいて説明する。 It will be described with reference to specific embodiments thereof. ただし、本発明は以下に示す実施例に限定されるものではない。 However, the present invention is not intended to be limited to the following examples.
以下、本発明の実施例における半導体結晶(結晶成長基板)の製造手順の概要を例示する。 Hereinafter, illustrate an overview of the manufacturing steps of the semiconductor crystal in the embodiment of the present invention (crystal growth substrate).
【0050】 [0050]
〔1〕突起部形成工程 図2に示す様に、シリコンより成る単結晶の下地基板101のSi(111)面上に、フォトリソグラフィーを利用したドライエッチングにより、直径約1μm、高さ約1μmの略円柱形状の突起部101aを約2μmの配置間隔で形成した。 [1] As shown in the protrusion forming step diagrams 2, on Si (111) surface of the base substrate 101 made of silicon single crystal, by dry etching utilizing photolithography, about 1 [mu] m, a height of about 1 [mu] m in diameter a protrusion 101a of a substantially cylindrical shape formed at arrangement intervals of about 2 [mu] m. 配列形態としては、一辺が約2μmの略正三角形を基調とする2次元三角格子の各格子点上に突起部101aの円柱底面の中心が配置される様に、突起部101aを形成した。 The arrangement form, as the center of the cylindrical bottom surface of the protrusion 101a on each lattice point of a two-dimensional triangular lattice whose one side is tones and substantially equilateral triangle of about 2μm are arranged to form a protrusion 101a. ただし、下地基板101の厚さは約200μmとした。 However, the thickness of the base substrate 101 was about 200μm.
【0051】 [0051]
〔2〕結晶成長工程 本結晶成長工程では、図4に示す様に、結晶の成長面が、突起部101aの上面(初期状態)から各々互いに連結されて一連の略平面状に成長するまでの成長工程を有機金属化合物気相成長法(MOVPE法)に従って実施し、その後、この基板層(結晶層)が200μm程度の厚膜に成長するまでの成長工程をハイドライド気相成長法(HVPE法)に従って実施した。 In [2] crystal growth step the crystal growth process, as shown in FIG. 4, to the growth surface of the crystal is grown, respectively are connected to each other in a series of substantially flat from the upper surface of the projecting portion 101a (initial state) metal organic vapor phase epitaxy growth process was performed according to (MOVPE method), then, the substrate layer (crystal layer) is hydride vapor phase epitaxy growth process until grown to a thickness film of about 200 [mu] m (HVPE method) It was carried out in accordance with.
尚、本結晶成長工程では、アンモニア(NH 3 )ガス、キャリアガス(H 2 ,N 2 )、トリメチルガリウム(Ga(CH 3 ) 3 )ガス(以下「TMG」と記す)、及びトリメチルアルミニウム(Al(CH 3 ) 3 )ガス(以下「TMA」と記す)を用いた。 In the present crystal growth process, ammonia (NH 3) gas, a carrier gas (H 2, N 2), trimethylgallium (Ga (CH 3) 3) gas (hereinafter referred to as "TMG") and trimethylaluminum (Al (CH 3) 3) using a gas (hereinafter referred to as "TMA").
【0052】 [0052]
(a)まず、上記の突起部101aが設けられた下地基板101(図2)を有機洗浄及び酸処理により洗浄し、結晶成長装置の反応室に載置されたサセプタに装着し、常圧でH 2を反応室に流しながら温度1100℃で下地基板101をベーキングした。 (A) First, the above projections underlying substrate 101 which 101a is provided (Fig. 2) was cleaned by organic cleaning and acid treatment was mounted on a susceptor placed in a reaction chamber of the crystal growth apparatus, at atmospheric pressure It was baked base substrate 101 at a temperature 1100 ° C. while flowing of H 2 into the reaction chamber.
【0053】 [0053]
(b)次に、上記の下地基板101の上に、MOVPE法に従って、H 2 ,NH 3 ,TMG,TMAを供給して、AlGaNバッファ層(基板層第1層)102aを成膜した。 (B) Next, on the underlying substrate 101, according to the MOVPE method, by supplying H 2, NH 3, TMG, and TMA, was deposited AlGaN buffer layer (substrate layer a first layer) 102a. このAlGaNバッファ層102aの結晶成長温度は、約1100℃、膜厚は約0.3μmであった。 Crystal growth temperature of the AlGaN buffer layer 102a is about 1100 ° C., the film thickness was about 0.3 [mu] m. (図3) (Fig. 3)
(c)このAlGaNバッファ層(基板層第1層)102aの上に、基板層第2層の一部、即ち、膜厚約5μmのGaN層102bを、H 2 、NH 3及びTMGを供給して、成長温度1075℃で結晶成長させた。 (C) on the AlGaN buffer layer (substrate layer a first layer) 102a, a portion of the substrate layer a second layer, i.e., the GaN layer 102b having a thickness of about 5 [mu] m, supplying H 2, NH 3 and TMG Te, it was crystal growth at a growth temperature of 1075 ℃. この工程により、図4に示す様に、基板層第2層(GaN層102b)の一部が横方向成長し、谷部即ち突起部101aの側方に大きな空洞ができた。 By this step, as shown in FIG. 4, a portion the substrate layer a second layer of (GaN layer 102b) is laterally grown, could large cavity on the side of the valley or projection portion 101a.
尚、この時のTMG供給速度は、概ね40μmol/min程度であり、基板層第2層(GaN層102b)の結晶成長速度は、約1μm/Hr程度であった。 Incidentally, TMG feed rate at this time is generally about 40 [mu] mol / min, the crystal growth rate of the substrate layer a second layer (GaN layer 102b) was about 1 [mu] m / Hr.
【0054】 [0054]
(d)その後、ハイドライド気相成長法(HVPE法)に従って、上記のGaN層(基板層第2層)102bを、更に、200μmまで結晶成長させた。 (D) Thereafter, in accordance with a hydride vapor phase epitaxy (HVPE), said GaN layer (substrate layer a second layer) 102b, was further, crystal growth to 200 [mu] m. このHVPE法におけるGaN層102bの結晶成長速度は、約45μm/Hr程度であった。 Crystal growth rate of the GaN layer 102b in the HVPE method, was about 45 [mu] m / Hr.
【0055】 [0055]
〔3〕分離工程(a)上記の結晶成長工程の後、アンモニア(NH 3 )ガスを結晶成長装置の反応室に流したまま、下地基板101と、(AlGaNバッファ層102aとGaN層102bとから成る)基板層102を略常温まで冷却した。 [3] After the separation step (a) above crystal growth process, while the ammonia (NH 3) gas was flowed in the reaction chamber of the crystal growth apparatus, and a base substrate 101, and (AlGaN buffer layer 102a and the GaN layer 102b made) was cooled substrate layer 102 to approximately ambient temperature. この時の冷却速度は、概ね「−50℃/min〜−5℃/min」程度であった。 The cooling rate at this time was approximately "-50 ℃ / min~-5 ℃ / min" about.
【0056】 [0056]
(b)その後、これらを結晶成長装置の反応室から取り出すと、下地基板101から剥離したGaN結晶が得られた。 (B) Thereafter, when taken them from the reaction chamber of the crystal growth apparatus, GaN crystals peeled from the starting substrate 101 is obtained. ただし、この結晶は、GaN層102bの裏面に、AlGaNバッファ層102aの小さな一部分の残骸と突起部101aの破断残骸とが残留したままのものであった。 However, the crystals on the back surface of the GaN layer 102b, and remnants of the small portion of the AlGaN buffer layer 102a and the rupture debris protrusions 101a were of still remaining.
【0057】 [0057]
〔4〕破断残骸除去工程 上記の分離工程の後、フッ酸に硝酸を加えた混合液を用いたエッチング処理により、GaN結晶の裏面に残ったSiより成る突起部101aの破断残骸を除去した。 [4] After the break debris removal step above separation process, by etching using a mixture solution obtained by adding nitric acid to hydrofluoric acid, to remove broken remnants of protrusions 101a formed of Si remaining on the back surface of the GaN crystal.
【0058】 [0058]
以上の製造方法により、膜厚約200μmの結晶性の非常に優れた良質のGaN結晶(GaN層102b)、即ち、下地基板101から独立した所望の半導体基板を得ることができた。 By the above manufacturing method, the film thickness of about 200μm crystallinity very good quality GaN crystal (GaN layer 102b), i.e., it was possible to obtain a desired semiconductor substrate which is independent from the underlying substrate 101.
【0059】 [0059]
尚、上記の実施例では、図2に例示した様に、下地基板の突起部や谷部は鉛直面と水平面により構成されているが、これらは任意の斜面や曲面等から形成しても良い。 In the above embodiment, as illustrated in FIG. 2, although projections and valleys of the underlying substrate is composed of vertical and horizontal planes, it may be formed from any slopes and a curved surface or the like . 従って、図2(c)に例示した下地基板上に形成される谷部の断面形状は、略矩形の凹字型以外にも、例えば、略U字型や略V字型等の形に形成しても良く、一般にこれらの形状、大きさ、間隔、配置、配向等は任意である。 Therefore, the cross-sectional shape of the trough portion formed to the illustrated base substrate in FIG. 2 (c), in addition to concave type generally rectangular, for example, formed into such a substantially U-shaped or substantially V-shaped may be generally these shapes, sizes, spacing, arrangement, orientation, etc. it is arbitrary.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】 本発明の作用を説明する、突起部を有する下地基板と、その上に成長した半導体結晶の、部分的な断片の模式的な斜視図。 [1] describing the effects of the present invention, a base substrate having a protruding portion, of the grown semiconductor crystal thereon, schematic perspective view of a partial fragment.
【図2】 本発明の実施例に係わる、下地基板(Si基板)101の部分的な断片の模式的な斜視図(a)、平面図(b)、及び断面図(c)。 [2] according to an embodiment of the present invention, schematic perspective view of a partial fragment of the base substrate (Si substrate) 101 (a), a plan view (b), and cross-sectional view (c).
【図3】 基板層第1層(AlGaNバッファ層)102aが成膜された下地基板101の模式的な斜視図(a)、平面図(b)、及び断面図(c)。 [3] the substrate layer a first layer (AlGaN buffer layer) 102a is schematic perspective view of a base substrate 101 which is formed (a), a plan view (b), and cross-sectional view (c).
【図4】 基板層102(層102a及び層102b)が積層された下地基板101の模式的な斜視図(a)、平面図(b)、及び断面図(c)。 [4] The substrate layer 102 (layer 102a and the layer 102b) is schematic perspective view of a base substrate 101 which is laminated (a), a plan view (b), and cross-sectional view (c).
【図5】 従来の下地基板上の半導体結晶の模式的な断面図。 Figure 5 is a schematic sectional view of a semiconductor crystal on a conventional base substrate.
【符号の説明】 DESCRIPTION OF SYMBOLS
101 … 下地基板(Si基板) 101 ... the underlying substrate (Si substrate)
101a … 突起部 102 … 基板層(窒化物半導体層) 101a ... projections 102 ... substrate layer (nitride semiconductor layer)
102a … 基板層第1層(AlGaNバッファ層) 102a ... substrate layer a first layer (AlGaN buffer layer)
102b … 基板層第2層(GaN単結晶層) 102b ... substrate layer a second layer (GaN single-crystal layer)

Claims (20)

  1. 横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより、前記下地基板から独立した半導体結晶を得る方法であって、 Using the lateral crystal growth effect, by forming a substrate layer made of a Group III nitride compound semiconductor on a base substrate, a method for obtaining a semiconductor crystal which is independent from the underlying substrate,
    前記下地基板上に多数の突起部を形成する突起部形成工程と、 A protrusion forming step of forming a plurality of projections on the base substrate,
    前記突起部の表面の少なくとも一部を前記基板層が結晶成長を開始する最初の成長面として、この成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで、前記基板層を結晶成長させる結晶成長工程と、 As a first growth surface of the substrate layer at least a part of the surface of the protrusion begins to crystal growth until grow to at least a series of substantially flat the growth surface is respectively coupled to one another, the crystal growth of said substrate layer crystal and a growth step of,
    前記突起部を破断することにより、前記基板層と前記下地基板とを分離する分離工程とを有し、 By breaking the projections, and a separation step of separating the base substrate and the substrate layer,
    前記基板層と前記下地基板とを冷却または加熱することにより、前記基板層と前記下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して前記突起部を破断することを特徴とする半導体結晶の製造方法。 By cooling or heating with said base substrate and said substrate layer, said substrate layer and to generate stress based on the thermal expansion coefficient difference between the base substrate, breaking the protrusions by utilizing the stress the method of manufacturing a semiconductor crystal, characterized.
  2. 横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより、半導体結晶を得る方法であって、 Using the lateral crystal growth effect, by forming a substrate layer made of a Group III nitride compound semiconductor on a base substrate, a method for obtaining a semiconductor crystal,
    前記下地基板上に多数の突起部を形成する突起部形成工程と、 A protrusion forming step of forming a plurality of projections on the base substrate,
    前記突起部の表面の少なくとも一部を前記基板層が結晶成長を開始する最初の成長面として、この成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで、前記基板層を結晶成長させる結晶成長工程とを有し、 As a first growth surface of the substrate layer at least a part of the surface of the protrusion begins to crystal growth until grow to at least a series of substantially flat the growth surface is respectively coupled to one another, the crystal growth of said substrate layer It is to have a crystal growth process,
    前記結晶成長工程において、前記III族窒化物系化合物半導体の原料供給量qを調整することにより、 In the crystal growth process, by adjusting the material supply amount q of the group III nitride compound semiconductor,
    前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域における前記III族窒化物系化合物半導体の結晶成長速度aと、前記突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することを特徴とする半導体結晶の製造方法。 Wherein said group III nitride compound semiconductor crystal growth rate a in at least a portion of the exposed region of the valley between the protrusions of the base substrate, the difference between the crystal growth rate b at the top portion of the protrusion (b the method of manufacturing a semiconductor crystal, characterized by controlling -a) a substantially maximum value.
  3. 前記結晶成長工程において、前記III族窒化物系化合物半導体の原料供給量qを調整することにより、 In the crystal growth process, by adjusting the material supply amount q of the group III nitride compound semiconductor,
    前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域における前記III族窒化物系化合物半導体の結晶成長速度aと、前記突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することを特徴とする請求項1に記載の半導体結晶の製造方法。 Wherein said group III nitride compound semiconductor crystal growth rate a in at least a portion of the exposed region of the valley between the protrusions of the base substrate, the difference between the crystal growth rate b at the top portion of the protrusion (b the method of manufacturing a semiconductor crystal according to claim 1, wherein the controlling -a) a substantially maximum value.
  4. 前記原料供給量qを1μmol/min以上、100μmol/min以下としたことを特徴とする請求項2または請求項3に記載の半導体結晶の製造方法。 The raw material supply amount q of 1 [mu] mol / min or more, a manufacturing method of a semiconductor crystal according to claim 2 or claim 3, characterized in that not more than 100 [mu] mol / min.
  5. 前記下地基板の材料として、シリコン(Si)または炭化シリコン(SiC)を用いることを特徴とする請求項1乃至請求項4の何れか1項に記載の半導体結晶の製造方法。 Wherein as a base material of the substrate, a silicon (Si) or the method of manufacturing a semiconductor crystal according to any one of claims 1 to 4, characterized by using silicon carbide the (SiC).
  6. 前記下地基板の材料として、Si(111)を用い、 As the material of the base substrate, using a Si (111),
    前記突起部形成工程において、前記下地基板の前記突起部間の谷部の露出領域に、Si(111)面が露出しない様に前記突起部を形成することを特徴とする請求項1乃至請求項5の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, the exposed area of the valley between the protrusions of the base substrate, according to claim 1 to claim, characterized in that the Si (111) surface to form the protrusion so as not to expose the method of manufacturing a semiconductor crystal according to any one of 5.
  7. 前記突起部形成工程後、少なくとも前記突起部の表面に「Al x Ga 1-x N(0<x≦1)」より成るバッファ層を形成する工程を有することを特徴とする請求項1乃至請求項6の何れか1項に記載の半導体結晶の製造方法。 After the protrusion forming step, at least the the surface of the protrusion "Al x Ga 1-x N ( 0 <x ≦ 1) " claim 1 to claim characterized in that it comprises a step of forming a buffer layer made of the method of manufacturing a semiconductor crystal according to any one of claim 6.
  8. 前記バッファ層の膜厚を前記突起部の縦方向の高さ以下に成膜することを特徴とする請求項7に記載の半導体結晶の製造方法。 The method of manufacturing a semiconductor crystal according to claim 7, characterized in that the deposition of the film thickness of the buffer layer below the height of the longitudinal direction of the protrusion.
  9. 前記結晶成長工程において、前記基板層の膜厚を50μm以上としたことを特徴とする請求項1乃至請求項8の何れか1項に記載の半導体結晶の製造方法。 In the crystal growth process, a manufacturing method of a semiconductor crystal according to any one of claims 1 to 8, characterized in that the thickness of the substrate layer not less than 50 [mu] m.
  10. 前記結晶成長工程において、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することを特徴とする請求項1乃至請求項9の何れか1項に記載の半導体結晶の製造方法。 In the crystal growth process, the slow crystal growth rate crystal growth method, the fast crystal growth rate epitaxy method, any one of claims 1 to 9, characterized in that to change the crystal growth method in the course 1 the method of manufacturing a semiconductor crystal according to Item.
  11. 前記突起部形成工程において、前記突起部が略等間隔または略一定周期で配置される様に前記突起部を形成することを特徴とする請求項1乃至請求項10の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, according to any one of claims 1 to 10, characterized in that the protrusion is to form the protrusion so as to be arranged at substantially equal intervals or substantially constant period the method of manufacturing a semiconductor crystal.
  12. 前記突起部形成工程において、1辺が0.1μm以上の略正三角形を基調とする2次元三角格子の格子点上に前記突起部を形成することを特徴とする請求項11に記載の半導体結晶の製造方法。 In the protrusion forming step, a semiconductor crystal according to claim 11, characterized in that one side to form the projections on the grid points of a two-dimensional triangular lattice of tones and substantially equilateral triangle than 0.1μm the method of production.
  13. 前記突起部形成工程において、前記突起部の水平断面形状を、略正三角形、略正六角形、略円形、又は四角形に形成したことを特徴とする請求項1乃至請求項12の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, a horizontal cross-sectional shape of the protrusion, substantially equilateral triangle, substantially regular hexagon, substantially circular, or any one of claims 1 to 12, characterized in that formed in a quadrangular the method of manufacturing a semiconductor crystal according.
  14. 前記突起部形成工程において、前記突起部の配置間隔を0.1μm以上、10μm以下とすることを特徴とする請求項1乃至請求項13の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, the protrusion arrangement interval 0.1μm or more, the manufacturing method of the semiconductor crystal according to any one of claims 1 to 13, characterized in that the 10μm or less.
  15. 前記突起部形成工程において、前記突起部の縦方向の高さを 0.5μm以上、20μm以下とすることを特徴とする請求項1乃至請求項14の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, the protrusion longitudinal height 0.5μm or more, the manufacture of semiconductor crystal according to any one of claims 1 to 14, characterized in that the 20μm or less Method.
  16. 前記突起部形成工程において、前記突起部の横方向の太さ、幅、又は直径を0.1μm以上、10μm以下とすることを特徴とする請求項1乃至請求項15の何れか1項に記載の半導体結晶の製造方法。 In the protrusion forming step, the protrusion lateral thickness of, width, or diameter 0.1μm or more, according to any one of claims 1 to 15, characterized in that the 10μm or less the method of manufacturing a semiconductor crystal.
  17. 前記結晶成長工程よりも前に、 Before the crystal growth process,
    各種エッチング、電子線照射処理、光学的処理、化学的処理、或いは物理的処理により、 Various etching, electron beam irradiation treatment, optical histological processing, chemical treatment, walk by physical treatment,
    前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域の結晶性又は分子構造を劣化又は変化させることにより、前記露出領域における前記III族窒化物系化合物半導体の結晶成長速度aを低下させることを特徴とする請求項1乃至請求項16の何れか1項に記載の半導体結晶の製造方法。 By degrading or changing the crystalline or molecular structure of at least a portion of the exposed region of the valley between the projections of the underlying substrate, the crystal growth rate a of the Group III nitride compound semiconductor in the exposed region the method of manufacturing a semiconductor crystal according to any one of claims 1 to 16, characterized in that lowering.
  18. 前記分離工程において、 In the separation step,
    前記下地基板と前記基板層とから成る基板を成長装置の反応室に残し、略一定流量のアンモニア(NH 3 )ガスを前記反応室に流したままの状態で、 The left reaction chamber of the deposition apparatus a substrate comprising a base substrate and the substrate layer, a substantially constant flow rate of ammonia (NH 3) gas in a state of flowing in said reaction chamber,
    前記基板を概ね「−100℃/min〜−0.5℃/min」程度の冷却速度で略常温まで冷却することを特徴とする請求項1又は、請求項3乃至請求項17の何れか1項に記載の半導体結晶の製造方法。 Claim 1 or, characterized in that cooling to approximately room temperature at a cooling rate of about the substrate generally "-100 ℃ / min~-0.5 ℃ / min ", one of claims 3 to 17 1 the method of manufacturing a semiconductor crystal according to Item.
  19. 少なくとも前記分離工程よりも後に、 Later than at least the separation step,
    前記基板層の裏面に残った前記突起部の破断残骸を化学的或いは物理的な加工処理により除去する残骸除去工程を有することを特徴とする請求項1又は、請求項3乃至請求項18の何れか1項に記載の半導体結晶の製造方法。 Claim 1 or characterized in that it has a debris removing step of removing by the protrusions break debris to-chemical or physical processing of remaining on the back surface of the substrate layer, of claims 3 to 18 the method of manufacturing a semiconductor crystal according to any one.
  20. 請求項1乃至請求項19の何れか1項に記載の半導体結晶の製造方法を用いて製造された前記半導体結晶を結晶成長基板として、結晶成長により製造することを特徴とするIII族窒化物系化合物半導体発光素子の製造方法 As claims 1 to crystal growth substrate the semiconductor crystal manufactured using the manufacturing method of the semiconductor crystal according to any one of claims 19, III group nitride system, characterized in that to produce the crystal growth method of manufacturing a compound semiconductor light-emitting device.
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