JP4084541B2 - Manufacturing method of semiconductor crystal and semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor crystal and semiconductor light emitting device Download PDF

Info

Publication number
JP4084541B2
JP4084541B2 JP2001036604A JP2001036604A JP4084541B2 JP 4084541 B2 JP4084541 B2 JP 4084541B2 JP 2001036604 A JP2001036604 A JP 2001036604A JP 2001036604 A JP2001036604 A JP 2001036604A JP 4084541 B2 JP4084541 B2 JP 4084541B2
Authority
JP
Japan
Prior art keywords
crystal growth
crystal
protrusion
base substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2001036604A
Other languages
Japanese (ja)
Other versions
JP2002241192A (en
Inventor
誠二 永井
一義 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Gosei Co Ltd
Toyota Central R&D Labs Inc
Original Assignee
Toyoda Gosei Co Ltd
Toyota Central R&D Labs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Gosei Co Ltd, Toyota Central R&D Labs Inc filed Critical Toyoda Gosei Co Ltd
Priority to JP2001036604A priority Critical patent/JP4084541B2/en
Priority to TW91102216A priority patent/TW575908B/en
Priority to KR10-2003-7010636A priority patent/KR20030074824A/en
Priority to DE60233386T priority patent/DE60233386D1/en
Priority to CNB028046919A priority patent/CN100414005C/en
Priority to US10/467,566 priority patent/US7052979B2/en
Priority to PCT/JP2002/001159 priority patent/WO2002064864A1/en
Priority to EP02711474A priority patent/EP1367150B1/en
Publication of JP2002241192A publication Critical patent/JP2002241192A/en
Application granted granted Critical
Publication of JP4084541B2 publication Critical patent/JP4084541B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Led Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより結晶成長基板を得る、半導体結晶の製造方法に関する。
【0002】
【従来の技術】
図5に例示する様に、例えばシリコン(Si)等から成る下地基板上に窒化ガリウム(GaN)等の窒化物半導体を結晶成長させ、その後常温まで冷却すると、窒化物半導体層に転位やクラックが多数入ることが一般に知られている。
【0003】
【発明が解決しようとする課題】
この様に、成長層(窒化物半導体層)に転位やクラックが多数入ると、その上にデバイスを作製した場合に、デバイス中に格子欠陥や転位、変形、クラック等が多数生じる結果となり、デバイス特性の劣化を引き起こす原因となる。
また、例えばシリコン(Si)等から成る下地基板を除去し、成長層のみを残して、独立した基板(結晶)を得ようとする場合、上記の転位やクラック等の作用により、大面積(1cm2以上)のものが得られない。
【0004】
本発明は、上記の課題を解決するために成されたものであり、その目的は、クラックが無く、転位の密度が低い高品質の半導体結晶(結晶成長基板)を得ることである。
【0005】
【課題を解決するための手段、並びに、作用及び発明の効果】
上記の課題を解決するためには、以下の手段が有効である。
即ち、第1の手段は、横方向結晶成長作用を利用して下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより下地基板から独立した半導体結晶を得る製造工程において、下地基板上に多数の突起部を形成する突起部形成工程と、この突起部の表面の少なくとも一部を基板層が結晶成長を開始する最初の成長面としてこの成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで基板層を結晶成長させる結晶成長工程と、突起部を破断することにより基板層と下地基板とを分離する分離工程とを設け、基板層と下地基板とを冷却または加熱することにより、基板層と下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して上記の突起部の破断を実施することである。
【0006】
ただし、ここで言う「III族窒化物系化合物半導体」一般には、2元、3元、又は4元の「AlxGayIn(1-x-y)N(0≦x≦1,0≦y≦1,0≦x+y≦1)」成る一般式で表される任意の混晶比の半導体が含まれ、更に、p型或いはn型の不純物が添加された半導体も、本明細書の「III族窒化物系化合物半導体」の範疇とする。
また、上記のIII族元素(Al,Ga,In)の内の一部をボロン(B)やタリウム(Tl)等で置換したり、或いは、窒素(N)の一部をリン(P)、砒素(As)、アンチモン(Sb)、ビスマス(Bi)等で置換したりした半導体等もまた、本明細書の「III族窒化物系化合物半導体」の範疇とする。
また、上記のp型の不純物としては、例えば、マグネシウム(Mg)や、或いはカルシウム(Ca)等を添加することができる。
また、上記のn型の不純物としては、例えば、シリコン(Si)や、硫黄(S)、セレン(Se)、テルル(Te)、或いはゲルマニウム(Ge)等を添加することができる。
また、これらの不純物は、同時に2元素以上を添加しても良いし、同時に両型(p型とn型)を添加しても良い。
【0007】
例えば、図1に例示する様に、多数の突起部を有する下地基板上にIII族窒化物系化合物より成る基板層(半導体結晶)を成長させる場合、突起部の大きさや配置間隔や結晶成長諸条件等を調整することにより、各突起部間(突起部の側方)に、半導体結晶が積層されていない「空洞」が形成可能となる。このため、突起部の高さに比して基板層の厚さを十分に大きくすれば、内部応力または外部応力がこの突起部に集中的に作用し易くなる。その結果、特にこれらの応力は、突起部に対する剪断応力等として作用し、この応力が大きくなった時に、突起部が破断する。従って、この応力を利用すれば、容易に下地基板と基板層とを分離(剥離)することが可能となる。この手段により、下地基板から独立した結晶(基板層)を得ることができる。
また、上記の「空洞」が大きく形成される程、突起部に応力(剪断応力)が集中し易くなる。
【0008】
また、例えば、図1からも分かる様に、上記の様な突起部を形成することにより、下地基板と基板層(又は、所望の半導体結晶層)との接触部位が狭く限定されるため、両者の格子定数差に基づく歪が生じ難くなり、「下地基板と基板層の間の格子定数差に基づく応力」が緩和される。このため、基板層(所望の半導体結晶)が結晶成長する際に、成長中の基板層に働く不要な応力が抑制されて転位やクラックの発生密度が低減される。
【0009】
尚、下地基板と基板層とを分離(剥離)する際に、下地基板側に基板層の一部が残っても良いし、或いは、基板層側に下地基板の一部(例:突起部の破断残骸)が残っても良い。即ち、上記の分離工程は、これらの材料の一部の残骸を皆無とする様な各材料の完全な分離を前提(必要条件)とするものではない。
【0010】
また、基板層と下地基板との熱膨張係数差に基づく応力を容易に生成することが可能となる。
【0011】
また、第2の手段は、横方向結晶成長作用を利用して下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより半導体結晶を得る製造工程において、下地基板上に多数の突起部を形成する突起部形成工程と、この突起部の表面の少なくとも一部を基板層が結晶成長を開始する最初の成長面としてこの成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで基板層を結晶成長させる結晶成長工程とを設け、この結晶成長工程においてIII族窒化物系化合物半導体の原料供給量qを調整することにより、下地基板の突起部間の谷部の少なくとも一部の露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aと、突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することである。
【0012】
この手段によれば、突起部の頭頂部付近の結晶成長速度が相対的に大きくなり、上記の露出領域付近の結晶成長は比較的抑制されて、頭頂部付近からの結晶成長が支配的となる。この結果、突起部の頭頂部付近から開始される基板層の横方向成長(ELO)が顕著となり、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和される。従って、基板層の結晶構造が安定し、基板層に転位やクラックが発生し難くなる。
また、基板層の横方向成長(ELO)が顕著となれば、例えば、突起部の側方(各突起部間)に比較的大きな空洞ができる場合もある。
【0013】
例えば、図1に例示する様に、適当な大きさ、間隔、或いは周期で下地基板の表面上に凹凸を形成した場合、一般に、下地基板の外周側壁付近の周辺部分以外では、凸部(突起部)の上面付近に比べて、凹部(谷部)の方が結晶材料の単位時間・単位面積当たりの供給量は少なくなり易い。この傾向は、結晶材料のガス流の流量、温度、方向等にも依存するが、これらの諸条件を最適、或いは好適に制御することにより、上記の差分(b−a)を略最大値に制御することが可能となる。
【0014】
また、第3の手段は、上記の第1の手段の結晶成長工程において、III族窒化物系化合物半導体の原料供給量qを調整することにより、下地基板の突起部間の谷部の少なくとも一部の露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aと、突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御することである。
【0015】
この場合にも、上記の手段と同様に、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和され、基板層の結晶構造が安定し、基板層に転位やクラックが発生し難くなる。この作用・効果は、各突起部間(突起部の側方)に空洞ができる程に横方向成長が顕著な場合に、比較的顕著となる。
また、突起部の側方(各突起部間)に空洞が形成されれば、突起部に剪断応力が集中し易くなり、上記の分離工程において下地基板と基板層とを剪断応力により分離し易くなる。この作用・効果は、各突起部間(突起部の側方)の空洞が大きくなる程、顕著となる。
【0016】
また、第4の手段は、上記の第2または第3の手段において、上記の原料供給量qを1μmol/min以上、100μmol/min以下とすることである。
【0017】
より望ましくは、上記の原料供給量qは、5μmol/min以上、90μmol/min以下が良い。更に望ましい値としては、形成される突起部の大きさや形、配置間隔等の下地基板の仕様や、供給原料の種類や供給流方向、結晶成長法等の諸条件にも依るが、概ね10〜80μmol/min程度が理想的である。この値は、大き過ぎると上記の差分(b−a)を略最大値に制御することが難しくなるので、各突起部間(突起部の側方)に大きな空洞を形成することが難しくなる。従って、この様な場合には、格子定数差に基づく結晶内の応力が比較的緩和され難く、転位が発生する等、基板層の単結晶の結晶性が劣化し易くなってしまい望ましくない。
【0018】
また、応力(剪断応力)により、下地基板と基板層とを分離する際にも、突起部側方の空洞が無いか或いはこの空洞が小さいと、突起部に応力が集中し難くなり、突起部の破断が起り難くなってしまい望ましくない。
一方、原料供給量qが小さ過ぎると、結晶成長時間が掛かり過ぎて生産性の面で不利となり、望ましくない。
【0019】
また、第5の手段は、上記の第1乃至第4の何れか1つの手段において、下地基板の材料として、シリコン(Si)または炭化シリコン(SiC)を用いることである。
また、その他の下地基板の材料としては、例えば、GaN,AlN,GaAs,InP,GaP,MgO,ZnO,MgAl24等が有用で、また、サファイア、スピネル、酸化マンガン、酸化ガリウムリチウム(LiGaO2)、硫化モリブデン(MoS)等も使用可能である。
ただし、熱膨張係数差に基づく剪断応力を用いて下地基板と基板層とを分離する場合には、両材料間の熱膨張係数差が小さくならない組み合わせを選択することが望ましく、また、下地基板側には、破断が起り易い材料を選択することが望ましい。
【0020】
また、第6の手段は、上記の第1乃至第5の何れか1つの手段において、下地基板の材料としてSi(111)を用い、突起部形成工程において下地基板の突起部間の谷部の露出領域にSi(111)面が露出しない様に突起部を形成することである。
本手段によれば、上記の谷部の露出面の結晶成長速度aを小さく抑制できるため、上記の差分(b−a)を、結晶性を維持したまま安定的に略最大化することが可能となる。
【0021】
また、第7の手段は、上記の第1乃至第6の何れか1つの手段の突起部形成工程後に、少なくとも突起部の表面に「AlxGa1-xN(0<x≦1)」より成るバッファ層を形成する工程を設けることである。
【0022】
ただし、上記のバッファ層とは別に、更に、上記のバッファ層と略同組成(例:AlNや、AlGaN)の中間層を周期的に、又は他の層と交互に、或いは、多層構造が構成される様に、積層しても良い。
【0023】
この様なバッファ層(或いは、中間層)の積層により、格子定数差に起因する基板層(成長層)に働く応力を緩和できる等の従来と同様の作用原理により、結晶性を向上させることが可能となる。
【0024】
また、第8の手段は、上記の第7の手段において、バッファ層の膜厚を突起部の縦方向の高さ以下に成膜することである。また、絶対的な目安としては、バッファ層の膜厚は、およそ0.01μm以上、1μm以下が望ましい。
この手段により、バッファ層の上に形成される所望の結晶層(例:GaN層)のみを良質に横方向に成長させることができる。即ち、この手段により、バッファ層の上に形成される結晶層に結晶成長時に掛かる「格子定数差に基づく応力」が軽減され、転位密度が効果的に低減できる。
【0025】
バッファ層等を形成するAlNやAlGaN等は、下地基板の露出した表面の略全面に成膜され易く、また、元来、所望の結晶の成長層等を形成するGaNの方が、AlNやAlGaN等よりも横方向成長し易い傾向に有る様だが、上記の手段によれば、より確実に大きな「空洞」を突起部の側方に形成することができる。
【0026】
また、この手段により、基板層を下地基板から分離した際に、基板層の裏面(下地基板が有った側の面)にも、結晶層(バッファ層の上に形成される所望の層)が直に広範囲に露出する。従って、基板層の裏面に電極を形成する際に、電気抵抗を抑制することが容易となる。
【0027】
尚、バッファ層の膜厚は、上記の通りおよそ0.01μm〜1μm程度が概ね妥当な範囲であるが、より望ましくは、0.1μm以上、0.5μm以下が良い。この膜厚が厚過ぎると、空洞が小さくなり易くなり望ましくない。また、この膜厚を薄くし過ぎると、略均一にバッファ層を成膜することが困難となる。特に、突起部の上部付近においてバッファ層の成膜ムラ(十分に成膜されない部位)が生じると、結晶性にもムラが生じ易くなり、望ましくない。
【0028】
また、第9の手段は、上記の第1乃至第8の何れか1つの手段の結晶成長工程において、基板層の膜厚を50μm以上とすることである。
【0029】
結晶成長させる基板層(III族窒化物系化合物半導体)の厚さは、約50μm以上が望ましく、この厚さが厚い程、基板層に対する引っ張り応力が緩和されて、基板層の転位やクラックの発生密度を減少できる。また、更には、同時に基板層を強固にでき、上記の剪断応力を上記の突起部に集中させ易くなる。
【0030】
また、第10の手段は、上記の第1乃至第9の何れか1つの手段の結晶成長工程において、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することである。
【0031】
例えば、結晶成長面が一連の略平面状に成るまでは、上記の差分(b−a)を略最大にし易い結晶成長法(例:MOVPE法)を採用し、その後は、膜厚を効率よく50μm以上にすることが容易な結晶成長法(例:HVPE法)を採用すれば、短時間に結晶性の良質な半導体結晶を得ることが可能となる。
【0032】
また、第11の手段は、上記の第1乃至第10の何れか1つの手段の突起部形成工程において、突起部が略等間隔又は略一定周期で配置される様に上記の突起部を形成することである。
【0033】
これにより、横方向成長の成長条件が全体的に略均等となり、結晶性の良否にムラが生じ難くなる。また、突起部間の谷部の上方が、基板層によって完全に覆われるまでの時間に、局所的なバラツキが生じ難くなるため、例えば、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更する場合に、その時期を的確に、早期に、或いは一意に決定することが容易となる。
また、本手段により、上記の空洞が各々略均等な大きさとなり、上記の剪断応力を各突起部に略均等に分配することが可能となるため、全突起部の破断がムラなく生じ、下地基板と基板層との分離が確実に実施できる様になる。
【0034】
また、第12の手段は、上記の第11の手段の突起部形成工程において、1辺が0.1μm以上の略正三角形を基調とする2次元三角格子の格子点上に突起部を形成することである。
この手段により、上記の第11の手段をより具体的に正確、確実に実施でき、よって、転位の数を確実に低減することができる。
【0035】
また、第13の手段は、上記の第1乃至第12の何れか1つの手段の突起部形成工程において、突起部の水平断面形状を、略正三角形、略正六角形、略円形、又は四角形に形成することである。
この手段により、III族窒化物系化合物半導体より形成される結晶の結晶軸の方向が各部で揃い易くなるため、或いは、任意の水平方向に対して突起部の水平方向の長さ(太さ)を略一様に制限できるため、転位の数を抑制することができる。特に、正六角形や正三角形は、半導体結晶の結晶構造と合致し易いのでより望ましい。また、円形や四角形は製造技術の面で形成し易いと言う、現行一般の加工技術水準の現状に照らしたメリットが有る。
【0036】
また、第14の手段は、上記の第1乃至第13の何れか1つの手段の突起部形成工程において、突起部の配置間隔(配置周期)を0.1μm以上、10μm以下とすることである。より望ましくは、結晶成長の実施条件にも依存するが、突起部の配置間隔は、0.5〜8μm程度が良い。ただし、この配置間隔とは、互いに接近する各突起部の中心点間の距離のことを言う。
【0037】
この手段により、突起部の谷部の上方を基板層で覆うことが可能となると同時に、突起部間に空洞を形成することが可能となる。
この値が小さ過ぎると、ELOの作用が殆ど得られなくなり、結晶性が劣化する。また、形成される空洞が小さくなり過ぎて、基板層の膜厚を必要以上に大きくしない限り、突起部を破断することが容易でなくなる。
【0038】
また、この値が大きくなり過ぎると、確実に突起部の谷部の上方を基板層で覆うことができなくなり、結晶性が均質かつ良質の結晶(基板層)が得られなくなる。
或いは、この値が更に大き過ぎると、谷部の露出面が広大となり過ぎて、ELOの作用が殆ど得られなくなり、また、空洞が全く形成されなくなるため、結晶性が劣化し、また、基板層の膜厚を必要以上に大きくしない限り、突起部を破断することが容易でなくなる。
【0039】
また、第15の手段は、上記の第1乃至第14の何れか1つの手段の突起部形成工程において、突起部の縦方向の高さを0.5μm以上、20μm以下とすることである。より望ましくは、結晶成長の実施条件にも依存するが、突起部の縦方向の高さは、0.8〜5μm程度が良い。
この高さが短過ぎると、突起部が無い場合と同様に、ELOの作用が殆ど得られなくなり、結晶性が劣化する。また、この高さが短過ぎると、上記の空洞が形成されなくなる。
また、この高さが高過ぎると、突起部の形成自身が困難となったり、突起部の形成に必要以上に時間がかかったり、下地基板の材料が必要以上に消費されたりして望ましくない。また、この高さが高過ぎると、剪断応力が突起部の縦方向に分散されてしまい、突起部を確実に破断させることが難しくなる。
【0040】
また、第16の手段は、上記の第1乃至第15の何れか1つの手段の突起部形成工程において、突起部の横方向の太さ、幅、又は直径を0.1μm以上、10μm以下とすることである。より望ましくは、結晶成長の実施条件にも依存するが、突起部の横方向の太さ、幅、又は直径は、0.5〜5μm程度が良い。
この太さが太過ぎると、格子定数差に基づいて基板層(成長層)に働く応力の影響が大きくなり、基板層の転位数が増加し易くなる。また、細過ぎると、突起部自身の形成が困難となるか、或いは、突起部の頭頂部の結晶成長速度bが遅くなり、望ましくない。
【0041】
また、応力(剪断応力等)により突起部を破断させる際にも、突起部の横方向の太さ、幅、又は直径が大き過ぎると、確実に破断されない部分が生じ易くなり、望ましくない。
また、格子定数差に基づいて基板層(成長層)に働く応力の影響の大小は、突起部の横方向の太さ(長さ)だけに依るものではなく、突起部の配置間隔等にも依存する。そして、これらの設定範囲が不適切であれば、上記の様に格子定数差に基づく応力の影響が大きくなり、基板層の転位数が増加し易くなり、望ましくない。
【0042】
また、突起部の頭頂部付近の横方向の太さ、幅、又は直径には、上記の様に最適値又は適正範囲があるため、突起部の上面、底面、又は水平断面の形状は、少なくとも局所的に閉じた形状(島状)、更には、外側に向かって凸状に閉じた形状が良く、より望ましくは、この上面、底面、又は水平断面の形状は、略円形や略正多角形等が良い。この様な設定により、任意の水平方向に対して確実に、上記の最適値又は適正範囲を実現することが容易となる。
【0043】
また、第17の手段は、上記の第1乃至第16の何れか1つの手段において、結晶成長工程よりも前に、各種エッチング、電子線照射処理、光学的処理、化学的処理、或いは切削や研磨その他の物理的処理により、下地基板の突起部間の谷部の少なくとも一部の露出領域の結晶性又は分子構造を劣化又は変化させることにより、この露出領域におけるIII族窒化物系化合物半導体の結晶成長速度aを低下させることである。
この手段により、前記の結晶成長速度の差分(b−a)をより大きくすることができる。従って、この手段によれば、突起部の頭頂部付近の結晶成長速度が相対的に大きくなるため、前記と同様の作用により、基板層の結晶成長時に基板層に働く「下地基板と基板層の間の格子定数差に基づく応力」が緩和され、基板層に転位やクラックが発生し難くなる。
【0044】
また、第18の手段は、上記の何れか1つの分離工程において、下地基板と基板層とから成る基板を成長装置の反応室に残し、略一定流量のアンモニア(NH3)ガスを反応室に流したままの状態で、基板を概ね「−100℃/min〜−0.5℃/min」程度の冷却速度で略常温まで冷却することである。
例えば、この様な手段により、基板層の結晶性を良質に維持したまま、前記の分離工程を実施することができる。
【0045】
また、第19の手段は、少なくとも、上記の何れか1つの分離工程よりも後に、基板層の裏面に残った突起部の破断残骸を化学的或いは物理的な加工処理により除去する残骸除去工程を設けることである。
この手段によれば、基板層の裏面(下地基板を剥離させた側の面)に、半導体発光素子等の電極を形成した際に、電極と基板層との界面付近に生じる電流ムラや電気抵抗を抑制でき、よって駆動電圧の低減や、或いは発光強度の向上等を図ることができる。
【0046】
更に、突起部の破断残骸を除去することにより、電極を半導体発光素子等の反射鏡としても利用する際には、鏡面付近での光の吸収や散乱が低減されて反射率が向上するので、発光強度が向上する。
また、例えば、研磨等の物理的な加工処理によりこの残骸除去工程を実施した場合等には、基板層の裏面のバッファ層までをも取り除いたり、或いは、基板層の裏面の平坦度を向上したりすることもできるので、電流ムラや電気抵抗の抑制、或いは、鏡面付近での光の吸収や散乱の低減等の、上記の作用効果を更に補強することができる。
【0047】
【0048】
また、第20の手段は、上記の第1乃至第19の何れか1つの手段に依る半導体結晶の製造方法を用いて製造された半導体結晶を結晶成長基板とした結晶成長により、III族窒化物系化合物半導体発光素子を製造することである。
この手段によれば、結晶性が良質で、内部応力の少ない半導体より、III族窒化物系化合物半導体発光素子を製造することが可能又は容易となる。
以上の手段により、前記の課題を解決することができる。
【0049】
【発明の実施の形態】
以下、本発明を具体的な実施例に基づいて説明する。ただし、本発明は以下に示す実施例に限定されるものではない。
以下、本発明の実施例における半導体結晶(結晶成長基板)の製造手順の概要を例示する。
【0050】
〔1〕突起部形成工程
図2に示す様に、シリコンより成る単結晶の下地基板101のSi(111)面上に、フォトリソグラフィーを利用したドライエッチングにより、直径約1μm、高さ約1μmの略円柱形状の突起部101aを約2μmの配置間隔で形成した。配列形態としては、一辺が約2μmの略正三角形を基調とする2次元三角格子の各格子点上に突起部101aの円柱底面の中心が配置される様に、突起部101aを形成した。ただし、下地基板101の厚さは約200μmとした。
【0051】
〔2〕結晶成長工程
本結晶成長工程では、図4に示す様に、結晶の成長面が、突起部101aの上面(初期状態)から各々互いに連結されて一連の略平面状に成長するまでの成長工程を有機金属化合物気相成長法(MOVPE法)に従って実施し、その後、この基板層(結晶層)が200μm程度の厚膜に成長するまでの成長工程をハイドライド気相成長法(HVPE法)に従って実施した。
尚、本結晶成長工程では、アンモニア(NH3)ガス、キャリアガス(H2,N2)、トリメチルガリウム(Ga(CH3)3)ガス(以下「TMG」と記す)、及びトリメチルアルミニウム(Al(CH3)3)ガス(以下「TMA」と記す)を用いた。
【0052】
(a)まず、上記の突起部101aが設けられた下地基板101(図2)を有機洗浄及び酸処理により洗浄し、結晶成長装置の反応室に載置されたサセプタに装着し、常圧でH2を反応室に流しながら温度1100℃で下地基板101をベーキングした。
【0053】
(b)次に、上記の下地基板101の上に、MOVPE法に従って、H2,NH3,TMG,TMAを供給して、AlGaNバッファ層(基板層第1層)102aを成膜した。このAlGaNバッファ層102aの結晶成長温度は、約1100℃、膜厚は約0.3μmであった。(図3)
(c)このAlGaNバッファ層(基板層第1層)102aの上に、基板層第2層の一部、即ち、膜厚約5μmのGaN層102bを、H2、NH3及びTMGを供給して、成長温度1075℃で結晶成長させた。この工程により、図4に示す様に、基板層第2層(GaN層102b)の一部が横方向成長し、谷部即ち突起部101aの側方に大きな空洞ができた。
尚、この時のTMG供給速度は、概ね40μmol/min程度であり、基板層第2層(GaN層102b)の結晶成長速度は、約1μm/Hr程度であった。
【0054】
(d)その後、ハイドライド気相成長法(HVPE法)に従って、上記のGaN層(基板層第2層)102bを、更に、200μmまで結晶成長させた。このHVPE法におけるGaN層102bの結晶成長速度は、約45μm/Hr程度であった。
【0055】
〔3〕分離工程
(a)上記の結晶成長工程の後、アンモニア(NH3)ガスを結晶成長装置の反応室に流したまま、下地基板101と、(AlGaNバッファ層102aとGaN層102bとから成る)基板層102を略常温まで冷却した。この時の冷却速度は、概ね「−50℃/min〜−5℃/min」程度であった。
【0056】
(b)その後、これらを結晶成長装置の反応室から取り出すと、下地基板101から剥離したGaN結晶が得られた。ただし、この結晶は、GaN層102bの裏面に、AlGaNバッファ層102aの小さな一部分の残骸と突起部101aの破断残骸とが残留したままのものであった。
【0057】
〔4〕破断残骸除去工程
上記の分離工程の後、フッ酸に硝酸を加えた混合液を用いたエッチング処理により、GaN結晶の裏面に残ったSiより成る突起部101aの破断残骸を除去した。
【0058】
以上の製造方法により、膜厚約200μmの結晶性の非常に優れた良質のGaN結晶(GaN層102b)、即ち、下地基板101から独立した所望の半導体基板を得ることができた。
【0059】
尚、上記の実施例では、図2に例示した様に、下地基板の突起部や谷部は鉛直面と水平面により構成されているが、これらは任意の斜面や曲面等から形成しても良い。従って、図2(c)に例示した下地基板上に形成される谷部の断面形状は、略矩形の凹字型以外にも、例えば、略U字型や略V字型等の形に形成しても良く、一般にこれらの形状、大きさ、間隔、配置、配向等は任意である。
【図面の簡単な説明】
【図1】 本発明の作用を説明する、突起部を有する下地基板と、その上に成長した半導体結晶の、部分的な断片の模式的な斜視図。
【図2】 本発明の実施例に係わる、下地基板(Si基板)101の部分的な断片の模式的な斜視図(a)、平面図(b)、及び断面図(c)。
【図3】 基板層第1層(AlGaNバッファ層)102aが成膜された下地基板101の模式的な斜視図(a)、平面図(b)、及び断面図(c)。
【図4】 基板層102(層102a及び層102b)が積層された下地基板101の模式的な斜視図(a)、平面図(b)、及び断面図(c)。
【図5】 従来の下地基板上の半導体結晶の模式的な断面図。
【符号の説明】
101 … 下地基板(Si基板)
101a … 突起部
102 … 基板層(窒化物半導体層)
102a … 基板層第1層(AlGaNバッファ層)
102b … 基板層第2層(GaN単結晶層)
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor crystal manufacturing method for obtaining a crystal growth substrate by forming a substrate layer made of a group III nitride compound semiconductor on a base substrate by utilizing a lateral crystal growth action.
[0002]
[Prior art]
As illustrated in FIG. 5, when a nitride semiconductor such as gallium nitride (GaN) is grown on a base substrate made of, for example, silicon (Si), and then cooled to room temperature, dislocations and cracks are formed in the nitride semiconductor layer. It is generally known to enter a large number.
[0003]
[Problems to be solved by the invention]
In this way, when a large number of dislocations and cracks enter the growth layer (nitride semiconductor layer), when a device is fabricated thereon, a large number of lattice defects, dislocations, deformations, cracks, etc. occur in the device. It causes deterioration of characteristics.
In addition, when the base substrate made of silicon (Si) or the like is removed and only the growth layer is left to obtain an independent substrate (crystal), a large area (1 cm) is obtained due to the above-described dislocations and cracks. 2 The above) is not obtained.
[0004]
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a high-quality semiconductor crystal (crystal growth substrate) free from cracks and having a low dislocation density.
[0005]
[Means for Solving the Problem, Action, and Effect of the Invention]
In order to solve the above problems, the following means are effective.
That is, the first means is a manufacturing process for obtaining a semiconductor crystal independent of the base substrate by forming a substrate layer made of a group III nitride compound semiconductor on the base substrate using a lateral crystal growth action. A protrusion forming step for forming a large number of protrusions on the base substrate, and at least a part of the surface of the protrusion as a first growth surface on which the substrate layer starts crystal growth; A crystal growth process for crystal growth of the substrate layer until it grows in a series of substantially flat surfaces and a separation process for separating the substrate layer and the base substrate by breaking the protrusions are provided. Then, by cooling or heating the substrate layer and the base substrate, a stress based on the difference in thermal expansion coefficient between the substrate layer and the base substrate is generated, and the protrusions are ruptured using this stress. That is.
[0006]
However, the “Group III nitride compound semiconductor” mentioned here is generally a binary, ternary or quaternary “Al”. x Ga y In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) ”is included, and semiconductors having an arbitrary mixed crystal ratio represented by the general formula“ N ”are added, and p-type or n-type impurities are added. These semiconductors are also included in the category of “Group III nitride compound semiconductor” in this specification.
Further, a part of the above group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or a part of nitrogen (N) is phosphorus (P), Semiconductors substituted with arsenic (As), antimony (Sb), bismuth (Bi), and the like are also included in the category of “Group III nitride compound semiconductor” in this specification.
Moreover, as said p-type impurity, magnesium (Mg), calcium (Ca), etc. can be added, for example.
As the n-type impurity, for example, silicon (Si), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), or the like can be added.
Further, two or more elements of these impurities may be added simultaneously, or both types (p-type and n-type) may be added simultaneously.
[0007]
For example, as illustrated in FIG. 1, when a substrate layer (semiconductor crystal) made of a group III nitride compound is grown on a base substrate having a large number of protrusions, the size of the protrusions, the arrangement interval, the crystal growth By adjusting the conditions and the like, a “cavity” in which no semiconductor crystal is stacked can be formed between the protrusions (sides of the protrusions). For this reason, if the thickness of the substrate layer is made sufficiently larger than the height of the protrusion, internal stress or external stress tends to act on the protrusion. As a result, these stresses in particular act as shear stresses on the protrusions, and when the stresses increase, the protrusions break. Therefore, if this stress is used, the base substrate and the substrate layer can be easily separated (peeled). By this means, a crystal (substrate layer) independent of the base substrate can be obtained.
Further, the larger the “cavity” is, the more easily stress (shear stress) is concentrated on the protrusion.
[0008]
Further, as can be seen from FIG. 1, for example, by forming the projections as described above, the contact portion between the base substrate and the substrate layer (or a desired semiconductor crystal layer) is narrowly limited. The strain based on the difference in the lattice constant is less likely to occur, and “stress based on the difference in the lattice constant between the base substrate and the substrate layer” is relieved. For this reason, when the substrate layer (desired semiconductor crystal) grows, unnecessary stress acting on the growing substrate layer is suppressed, and the generation density of dislocations and cracks is reduced.
[0009]
Note that when separating (separating) the base substrate and the substrate layer, a part of the substrate layer may remain on the base substrate side, or a part of the base substrate (eg, a protrusion portion) on the substrate layer side. Breaking debris) may remain. That is, the above separation step does not assume (necessary conditions) the complete separation of each material so that some of the remnants of these materials are eliminated.
[0010]
Also, Based on the difference in thermal expansion coefficient between the substrate layer and the underlying substrate Stress can be easily generated.
[0011]
Also, Second In the manufacturing process of obtaining a semiconductor crystal by forming a substrate layer made of a group III nitride compound semiconductor on the base substrate using the lateral crystal growth action, a number of protrusions are formed on the base substrate. A projection layer forming step, and at least a part of the surface of the projection portion as a first growth surface on which the substrate layer starts crystal growth until the growth surfaces are connected to each other and grown to at least a series of substantially flat surfaces. A crystal growth step for crystal growth, and adjusting the raw material supply amount q of the group III nitride compound semiconductor in this crystal growth step, thereby exposing at least a part of the valleys between the protrusions of the base substrate Is to control the difference (b−a) between the crystal growth rate a of the group III nitride compound semiconductor and the crystal growth rate b at the top of the protrusion to a substantially maximum value.
[0012]
According to this means, the crystal growth rate in the vicinity of the top of the protrusion is relatively increased, the crystal growth in the vicinity of the exposed region is relatively suppressed, and the crystal growth from the vicinity of the top becomes dominant. . As a result, the lateral growth (ELO) of the substrate layer starting from the vicinity of the top of the protrusion becomes prominent, and acts on the substrate layer during the crystal growth of the substrate layer “based on the lattice constant difference between the base substrate and the substrate layer. "Stress" is relieved. Therefore, the crystal structure of the substrate layer is stabilized, and dislocations and cracks are less likely to occur in the substrate layer.
Further, if the lateral growth (ELO) of the substrate layer becomes significant, for example, a relatively large cavity may be formed on the side of the protrusion (between the protrusions).
[0013]
For example, as illustrated in FIG. 1, when irregularities are formed on the surface of the base substrate with an appropriate size, interval, or period, generally, a convex portion (protrusion) is formed in a portion other than the peripheral portion near the outer peripheral side wall of the base substrate. Compared with the vicinity of the upper surface of the portion), the amount of the crystal material supplied per unit time / unit area tends to be smaller in the concave portion (valley portion). This tendency depends on the flow rate, temperature, direction, etc. of the gas flow of the crystal material, but the above difference (b−a) is made to be approximately the maximum value by optimally or suitably controlling these conditions. It becomes possible to control.
[0014]
Also, Third Means above First In the crystal growth step of the means, by adjusting the raw material supply amount q of the group III nitride compound semiconductor, the group III nitride compound semiconductor in the at least part of the exposed region of the valley between the protrusions of the base substrate The difference (b−a) between the crystal growth rate a and the crystal growth rate b at the top of the protrusion is controlled to a substantially maximum value.
[0015]
In this case as well, as in the above-mentioned means, the “stress based on the lattice constant difference between the base substrate and the substrate layer” acting on the substrate layer during crystal growth of the substrate layer is relaxed, and the crystal structure of the substrate layer is stabilized. Dislocations and cracks are less likely to occur in the substrate layer. This action / effect becomes relatively remarkable when the lateral growth is so remarkable that a cavity is formed between the protrusions (sides of the protrusions).
Further, if a cavity is formed on the side of the protrusion (between the protrusions), the shear stress tends to concentrate on the protrusion, and the base substrate and the substrate layer can be easily separated by the shear stress in the separation process. Become. This action / effect becomes more prominent as the cavity between the protrusions (the sides of the protrusions) becomes larger.
[0016]
Also, 4th Means above Second or third In the means, the raw material supply amount q is set to 1 μmol / min or more and 100 μmol / min or less.
[0017]
More preferably, the raw material supply amount q is 5 μmol / min or more and 90 μmol / min or less. More desirable values depend on the specifications of the base substrate such as the size and shape of the projections to be formed, the arrangement interval, and other conditions such as the type of feed material, the feed flow direction, and the crystal growth method. About 80 μmol / min is ideal. If this value is too large, it becomes difficult to control the difference (b−a) to a substantially maximum value, so that it becomes difficult to form a large cavity between the protrusions (sides of the protrusions). Therefore, in such a case, the stress in the crystal based on the difference in lattice constant is relatively less relaxed, and dislocations are likely to occur. This makes the single crystal crystallinity of the substrate layer easily deteriorated, which is not desirable.
[0018]
Also, when the base substrate and the substrate layer are separated by stress (shear stress), if there is no cavity on the side of the protrusion or if this cavity is small, the stress is difficult to concentrate on the protrusion. This is not desirable because it is difficult to break.
On the other hand, if the raw material supply amount q is too small, it takes too much time for crystal growth, which is disadvantageous in terms of productivity, which is not desirable.
[0019]
Also, 5th Means above 1st to 4th In any one of the means, silicon (Si) or silicon carbide (SiC) is used as a material for the base substrate.
As other base substrate materials, for example, GaN, AlN, GaAs, InP, GaP, MgO, ZnO, MgAl 2 O Four Etc., and sapphire, spinel, manganese oxide, lithium gallium oxide (LiGaO 2 ), Molybdenum sulfide (MoS), and the like can also be used.
However, when separating the base substrate and the substrate layer using shear stress based on the difference in thermal expansion coefficient, it is desirable to select a combination that does not reduce the difference in thermal expansion coefficient between the two materials. For this, it is desirable to select a material that easily breaks.
[0020]
Also, 6th Means above 1st to 5th In any one of the means, Si (111) is used as the material of the base substrate, and the protrusion is formed so that the Si (111) surface is not exposed in the exposed region of the valley between the protrusions of the base substrate in the protrusion formation process. Is to form.
According to this means, since the crystal growth rate a of the exposed surface of the valley can be suppressed small, the difference (b−a) can be stably and substantially maximized while maintaining the crystallinity. It becomes.
[0021]
Also, 7th Means above 1st to 6th After the protrusion forming step of any one means, at least the surface of the protrusion is “Al x Ga 1-x A step of forming a buffer layer made of N (0 <x ≦ 1) ”.
[0022]
However, in addition to the buffer layer, an intermediate layer of substantially the same composition (eg, AlN or AlGaN) as the buffer layer is formed periodically or alternately with other layers, or a multilayer structure is formed. As is done, they may be stacked.
[0023]
Crystallinity can be improved by the same principle of action as in the past, such as the buffer layer (or intermediate layer) being laminated to relieve stress acting on the substrate layer (growth layer) due to the difference in lattice constant. It becomes possible.
[0024]
Also, 8th Means above 7th In the means, the film thickness of the buffer layer is formed to be equal to or less than the height in the vertical direction of the protrusion. Also, as an absolute guide, the buffer layer thickness is preferably about 0.01 μm or more and 1 μm or less.
By this means, only a desired crystal layer (eg, GaN layer) formed on the buffer layer can be grown in the lateral direction with good quality. That is, by this means, the “stress based on the difference in lattice constant” applied to the crystal layer formed on the buffer layer during crystal growth is reduced, and the dislocation density can be effectively reduced.
[0025]
AlN, AlGaN, and the like that form the buffer layer and the like are easily formed on almost the entire exposed surface of the base substrate, and GaN that originally forms a growth layer of a desired crystal is more likely to be AlN or AlGaN. However, according to the above means, a large “cavity” can be more reliably formed on the side of the protrusion.
[0026]
Further, when the substrate layer is separated from the base substrate by this means, the crystal layer (desired layer formed on the buffer layer) is also formed on the back surface of the substrate layer (the surface on which the base substrate is present). Is directly exposed over a wide area. Therefore, it is easy to suppress the electrical resistance when forming the electrode on the back surface of the substrate layer.
[0027]
As described above, the thickness of the buffer layer is generally in the range of about 0.01 μm to 1 μm, more preferably 0.1 μm or more and 0.5 μm or less. If this film thickness is too thick, the cavity tends to be small, which is not desirable. If the film thickness is too thin, it is difficult to form the buffer layer substantially uniformly. In particular, if uneven film formation of the buffer layer (portion where film formation is not sufficient) occurs in the vicinity of the upper portion of the protrusion, unevenness of the crystallinity tends to occur, which is not desirable.
[0028]
Also, 9th Means above 1st to 8th In the crystal growth step of any one means, the film thickness of the substrate layer is set to 50 μm or more.
[0029]
The thickness of the substrate layer (Group III nitride compound semiconductor) for crystal growth is preferably about 50 μm or more. The thicker the thickness, the more the tensile stress on the substrate layer is relaxed, and the generation of dislocations and cracks in the substrate layer. Density can be reduced. Furthermore, the substrate layer can be strengthened at the same time, and the shear stress can be easily concentrated on the protrusions.
[0030]
Also, 10th Means above 1st to 9th In the crystal growth step of any one means, the crystal growth method is changed midway from a crystal growth method having a low crystal growth rate to a crystal growth method having a high crystal growth rate.
[0031]
For example, a crystal growth method (e.g., MOVPE method) that makes it easy to maximize the above difference (b−a) is adopted until the crystal growth surface becomes a series of substantially planar shapes. Employing a crystal growth method (eg, HVPE method) that can easily be 50 μm or more makes it possible to obtain a high-quality semiconductor crystal in a short time.
[0032]
Also, Eleventh Means above 1st to 10th In the protrusion forming step of any one means, the protrusions are formed so that the protrusions are arranged at substantially equal intervals or at a substantially constant period.
[0033]
As a result, the growth conditions for the lateral growth are substantially uniform as a whole, and unevenness in crystallinity is less likely to occur. In addition, since local variations are less likely to occur during the time until the upper portion of the valley between the protrusions is completely covered by the substrate layer, for example, from a crystal growth method with a slow crystal growth rate, When the crystal growth method is changed to a fast crystal growth method, it becomes easy to determine the timing accurately, early, or uniquely.
In addition, this means that the cavities are approximately equal in size, and the shear stress can be distributed substantially evenly to the respective protrusions. The substrate and the substrate layer can be reliably separated.
[0034]
Also, 12th Means above Eleventh In the protrusion forming step of the means, the protrusions are formed on the lattice points of a two-dimensional triangular lattice based on a substantially equilateral triangle having one side of 0.1 μm or more.
By this means, the above Eleventh The means can be implemented more specifically and accurately, and thus the number of dislocations can be reliably reduced.
[0035]
Also, Thirteenth Means above 1st to 12th In the projection forming step of any one means, the horizontal cross-sectional shape of the projection is formed into a substantially regular triangle, a substantially regular hexagon, a substantially circle, or a quadrangle.
This means that the crystal axis direction of the crystal formed from the group III nitride compound semiconductor can be easily aligned in each part, or the horizontal length (thickness) of the protrusion with respect to an arbitrary horizontal direction. Therefore, the number of dislocations can be suppressed. In particular, regular hexagons and regular triangles are more desirable because they easily match the crystal structure of the semiconductor crystal. Further, there is a merit in light of the current state of the general processing technology level that a circle or a rectangle is easy to form in terms of manufacturing technology.
[0036]
Also, 14th Means above 1st to 13th In the projection forming step of any one means, the arrangement interval (arrangement period) of the projections is set to 0.1 μm or more and 10 μm or less. More desirably, the arrangement interval of the protrusions is preferably about 0.5 to 8 μm, although it depends on the conditions of crystal growth. However, this arrangement | positioning space | interval means the distance between the center points of each projection part which mutually approaches.
[0037]
By this means, it is possible to cover the upper part of the valley of the protrusion with the substrate layer, and at the same time, it is possible to form a cavity between the protrusions.
If this value is too small, the effect of ELO is hardly obtained, and the crystallinity is deteriorated. In addition, the formed cavity becomes too small, and it is not easy to break the protrusion unless the film thickness of the substrate layer is increased more than necessary.
[0038]
Further, if this value becomes too large, the upper part of the valleys of the protrusions cannot be reliably covered with the substrate layer, and crystals having a uniform crystallinity and a good quality (substrate layer) cannot be obtained.
Alternatively, if this value is too large, the exposed surface of the valley becomes too large, and the effect of ELO is hardly obtained, and no cavities are formed at all, so that the crystallinity deteriorates and the substrate layer Unless the film thickness is increased more than necessary, it is not easy to break the protrusion.
[0039]
Also, 15th Means above 1st to 14th In the projection forming step of any one means, the vertical height of the projection is set to 0.5 μm or more and 20 μm or less. More desirably, although depending on the crystal growth conditions, the height of the protrusions in the vertical direction is preferably about 0.8 to 5 μm.
If this height is too short, as in the case where there is no protrusion, the effect of ELO is hardly obtained and the crystallinity deteriorates. On the other hand, if the height is too short, the above-mentioned cavity is not formed.
On the other hand, if the height is too high, the formation of the protrusion itself becomes difficult, it takes more time than necessary to form the protrusion, and the material of the base substrate is unnecessarily consumed. On the other hand, if the height is too high, the shear stress is dispersed in the longitudinal direction of the protrusions, making it difficult to reliably break the protrusions.
[0040]
Also, 16th Means above 1st to 15th In the projection forming step of any one means, the lateral thickness, width, or diameter of the projection is set to 0.1 μm or more and 10 μm or less. More desirably, the thickness, width, or diameter in the lateral direction of the protrusion is preferably about 0.5 to 5 μm, although it depends on the conditions for crystal growth.
If the thickness is too thick, the influence of stress acting on the substrate layer (growth layer) based on the difference in lattice constant increases, and the number of dislocations in the substrate layer tends to increase. On the other hand, if it is too thin, the formation of the projection itself becomes difficult, or the crystal growth rate b at the top of the projection becomes slow, which is not desirable.
[0041]
Also, when the protrusion is broken by stress (shear stress or the like), if the width, width, or diameter in the lateral direction of the protrusion is too large, a portion that is not surely broken is likely to occur, which is not desirable.
In addition, the magnitude of the influence of stress acting on the substrate layer (growth layer) based on the difference in lattice constant does not depend only on the lateral thickness (length) of the protrusions, but also on the arrangement interval of the protrusions, etc. Dependent. If these setting ranges are inappropriate, the influence of stress based on the lattice constant difference becomes large as described above, and the number of dislocations in the substrate layer tends to increase, which is not desirable.
[0042]
In addition, since the lateral thickness, width, or diameter in the vicinity of the top of the protrusion has an optimum value or an appropriate range as described above, the shape of the top surface, bottom surface, or horizontal section of the protrusion is at least A locally closed shape (island shape) or a convexly closed shape toward the outside is preferable. More preferably, the shape of the top surface, the bottom surface, or the horizontal cross section is substantially circular or substantially regular polygonal. Etc. are good. With such a setting, it becomes easy to reliably realize the optimum value or the appropriate range in any horizontal direction.
[0043]
Also, 17th Means above 1st to 16th In any one method, various etching and electron beam irradiation treatments are performed before the crystal growth step. ,light Chemical treatment, chemical treatment, or cutting and polishing Other The crystal growth of the group III nitride compound semiconductor in this exposed region is deteriorated or changed by degrading or changing the crystallinity or molecular structure of at least a part of the valley between the protrusions of the base substrate by physical treatment of It is to reduce the speed a.
By this means, the difference (b−a) in the crystal growth rate can be further increased. Therefore, according to this means, the crystal growth rate in the vicinity of the top of the protrusion is relatively increased. The stress based on the difference in the lattice constant between them is relaxed, and dislocations and cracks are less likely to occur in the substrate layer.
[0044]
Also, 18th In any one of the separation steps described above, the means leaves a substrate composed of a base substrate and a substrate layer in the reaction chamber of the growth apparatus, so that ammonia (NH Three ) With the gas flowing in the reaction chamber, the substrate is cooled to approximately room temperature at a cooling rate of approximately “−100 ° C./min to −0.5 ° C./min”.
For example, the above separation step can be performed by such means while maintaining the crystallinity of the substrate layer in good quality.
[0045]
Also, 19th The means is that at least after any one of the above-described separation steps, the broken debris of the protrusions remaining on the back surface of the substrate layer Turn into It is to provide a debris removal step that is removed by chemical or physical processing.
According to this means, when an electrode such as a semiconductor light emitting device is formed on the back surface of the substrate layer (the surface on which the base substrate is peeled off), current unevenness and electrical resistance generated near the interface between the electrode and the substrate layer Therefore, it is possible to reduce the driving voltage or improve the light emission intensity.
[0046]
Furthermore, by removing the broken debris from the protrusions, when the electrode is also used as a reflector such as a semiconductor light emitting device, the absorption and scattering of light near the mirror surface is reduced and the reflectance is improved. The emission intensity is improved.
In addition, for example, when this debris removal step is performed by physical processing such as polishing, even the buffer layer on the back surface of the substrate layer is removed, or the flatness of the back surface of the substrate layer is improved. Therefore, it is possible to further reinforce the above-mentioned effects such as suppression of current unevenness and electrical resistance, or reduction of light absorption and scattering near the mirror surface.
[0047]
[0048]
Also, 20th Means above 1st to 19th A group III nitride compound semiconductor light emitting device is manufactured by crystal growth using a semiconductor crystal manufactured by a semiconductor crystal manufacturing method according to any one means as a crystal growth substrate.
According to this means, a group III nitride compound semiconductor light-emitting element can be produced or facilitated from a semiconductor with good crystallinity and low internal stress.
The above-described problems can be solved by the above means.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on specific examples. However, the present invention is not limited to the following examples.
Hereinafter, the outline of the manufacturing procedure of the semiconductor crystal (crystal growth substrate) in the embodiment of the present invention will be exemplified.
[0050]
[1] Projection forming process
As shown in FIG. 2, a substantially cylindrical projection 101a having a diameter of about 1 μm and a height of about 1 μm is formed on the Si (111) surface of a single crystal base substrate 101 made of silicon by dry etching using photolithography. Were formed at an interval of about 2 μm. As the arrangement form, the protrusion 101a was formed so that the center of the cylindrical bottom surface of the protrusion 101a was arranged on each lattice point of a two-dimensional triangular lattice having a substantially equilateral triangle having a side of about 2 μm. However, the thickness of the base substrate 101 was about 200 μm.
[0051]
[2] Crystal growth process
In this crystal growth process, as shown in FIG. 4, the growth process is performed until the crystal growth surface is connected to each other from the upper surface (initial state) of the protrusion 101a to grow into a series of substantially planar shapes. It implemented according to the vapor phase epitaxy method (MOVPE method), and the growth process until this board | substrate layer (crystal layer) grew to about 200 micrometers thick film was implemented according to the hydride vapor phase epitaxy method (HVPE method) after that.
In this crystal growth process, ammonia (NH Three ) Gas, carrier gas (H 2 , N 2 ), Trimethylgallium (Ga (CH Three ) Three ) Gas (hereinafter referred to as “TMG”), and trimethylaluminum (Al (CH Three ) Three ) Gas (hereinafter referred to as “TMA”) was used.
[0052]
(A) First, the base substrate 101 (FIG. 2) provided with the protrusion 101a is cleaned by organic cleaning and acid treatment, and is attached to a susceptor placed in a reaction chamber of a crystal growth apparatus, and is at normal pressure. H 2 The base substrate 101 was baked at a temperature of 1100 ° C. while flowing into the reaction chamber.
[0053]
(B) Next, on the base substrate 101, according to the MOVPE method, H 2 , NH Three , TMG and TMA were supplied to form an AlGaN buffer layer (substrate layer first layer) 102a. The crystal growth temperature of the AlGaN buffer layer 102a was about 1100 ° C., and the film thickness was about 0.3 μm. (Figure 3)
(C) On this AlGaN buffer layer (substrate layer first layer) 102a, a part of the substrate layer second layer, that is, a GaN layer 102b having a thickness of about 5 μm, is 2 , NH Three And TMG were supplied to grow a crystal at a growth temperature of 1075 ° C. As a result of this step, as shown in FIG. 4, a part of the second substrate layer (GaN layer 102b) grew in the lateral direction, and a large cavity was formed on the side of the trough, that is, the protrusion 101a.
At this time, the TMG supply rate was about 40 μmol / min, and the crystal growth rate of the second substrate layer (GaN layer 102b) was about 1 μm / Hr.
[0054]
(D) Then, according to the hydride vapor phase epitaxy method (HVPE method), the above-mentioned GaN layer (substrate layer second layer) 102b was further grown to 200 μm. The crystal growth rate of the GaN layer 102b in this HVPE method was about 45 μm / Hr.
[0055]
[3] Separation process
(A) After the above crystal growth step, ammonia (NH Three The base substrate 101 and the substrate layer 102 (consisting of the AlGaN buffer layer 102a and the GaN layer 102b) were cooled to substantially room temperature while the gas was allowed to flow into the reaction chamber of the crystal growth apparatus. The cooling rate at this time was about “−50 ° C./min to −5 ° C./min”.
[0056]
(B) Thereafter, when these were taken out from the reaction chamber of the crystal growth apparatus, a GaN crystal separated from the base substrate 101 was obtained. However, this crystal was such that a small part of the AlGaN buffer layer 102a and a broken part of the protrusion 101a remained on the back surface of the GaN layer 102b.
[0057]
[4] Broken debris removal process
After the above separation step, the fracture debris of the protrusion 101a made of Si remaining on the back surface of the GaN crystal was removed by an etching process using a mixed solution in which nitric acid was added to hydrofluoric acid.
[0058]
With the above manufacturing method, a high-quality GaN crystal (GaN layer 102b) having a film thickness of about 200 μm and excellent crystallinity, that is, a desired semiconductor substrate independent of the base substrate 101 could be obtained.
[0059]
In the above embodiment, as illustrated in FIG. 2, the protrusions and valleys of the base substrate are constituted by a vertical surface and a horizontal surface. . Accordingly, the cross-sectional shape of the valley formed on the base substrate illustrated in FIG. 2C is formed in, for example, a substantially U-shape or a substantially V-shape other than the substantially rectangular concave shape. Generally, these shapes, sizes, intervals, arrangements, orientations and the like are arbitrary.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view of a partial fragment of a base substrate having protrusions and a semiconductor crystal grown thereon, for explaining the operation of the present invention.
FIG. 2 is a schematic perspective view (a), a plan view (b), and a sectional view (c) of a partial fragment of a base substrate (Si substrate) 101 according to an embodiment of the present invention.
FIG. 3 is a schematic perspective view (a), a plan view (b), and a sectional view (c) of a base substrate 101 on which a first substrate layer (AlGaN buffer layer) 102a is formed.
FIG. 4 is a schematic perspective view (a), a plan view (b), and a cross-sectional view (c) of a base substrate 101 on which a substrate layer 102 (layer 102a and layer 102b) is stacked.
FIG. 5 is a schematic cross-sectional view of a semiconductor crystal on a conventional base substrate.
[Explanation of symbols]
101 ... Base substrate (Si substrate)
101a ... Projection
102 ... Substrate layer (nitride semiconductor layer)
102a: substrate layer first layer (AlGaN buffer layer)
102b ... Substrate layer second layer (GaN single crystal layer)

Claims (20)

横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより、前記下地基板から独立した半導体結晶を得る方法であって、
前記下地基板上に多数の突起部を形成する突起部形成工程と、
前記突起部の表面の少なくとも一部を前記基板層が結晶成長を開始する最初の成長面として、この成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで、前記基板層を結晶成長させる結晶成長工程と、
前記突起部を破断することにより、前記基板層と前記下地基板とを分離する分離工程とを有し、
前記基板層と前記下地基板とを冷却または加熱することにより、前記基板層と前記下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して前記突起部を破断することを特徴とする半導体結晶の製造方法。
A method of obtaining a semiconductor crystal independent from the base substrate by forming a substrate layer made of a group III nitride compound semiconductor on the base substrate using lateral crystal growth action,
A protrusion forming step of forming a large number of protrusions on the base substrate;
Crystal growth of the substrate layer until at least a part of the surface of the protrusion is the first growth surface on which the substrate layer starts crystal growth, and the growth surfaces are connected to each other to grow to at least a series of substantially flat surfaces. Crystal growth process
A separation step of separating the substrate layer and the base substrate by breaking the protrusion,
By cooling or heating the substrate layer and the base substrate, a stress based on a difference in thermal expansion coefficient between the substrate layer and the base substrate is generated, and the protrusion is broken using the stress. A method for producing a semiconductor crystal.
横方向結晶成長作用を利用して、下地基板上にIII族窒化物系化合物半導体から成る基板層を形成することにより、半導体結晶を得る方法であって、
前記下地基板上に多数の突起部を形成する突起部形成工程と、
前記突起部の表面の少なくとも一部を前記基板層が結晶成長を開始する最初の成長面として、この成長面が各々互いに連結されて少なくとも一連の略平面に成長するまで、前記基板層を結晶成長させる結晶成長工程と
を有し、
前記結晶成長工程において、前記III族窒化物系化合物半導体の原料供給量qを調整することにより、
前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域における前記III族窒化物系化合物半導体の結晶成長速度aと、前記突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御する
ことを特徴とする半導体結晶の製造方法。
A method of obtaining a semiconductor crystal by forming a substrate layer made of a group III nitride compound semiconductor on a base substrate using a lateral crystal growth action,
A protrusion forming step of forming a large number of protrusions on the base substrate;
Crystal growth of the substrate layer until at least a part of the surface of the protrusion is the first growth surface on which the substrate layer starts crystal growth, and the growth surfaces are connected to each other to grow to at least a series of substantially flat surfaces. And a crystal growth step
In the crystal growth step, by adjusting the raw material supply amount q of the group III nitride compound semiconductor,
The difference (b) between the crystal growth rate a of the group III nitride compound semiconductor in the at least part of the exposed region of the valley between the projections of the base substrate and the crystal growth rate b at the top of the projection. -A) is controlled to a substantially maximum value.
前記結晶成長工程において、前記III族窒化物系化合物半導体の原料供給量qを調整することにより、
前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域における前記III族窒化物系化合物半導体の結晶成長速度aと、前記突起部の頭頂部における結晶成長速度bとの差分(b−a)を略最大値に制御する
ことを特徴とする請求項1に記載の半導体結晶の製造方法。
In the crystal growth step, by adjusting the raw material supply amount q of the group III nitride compound semiconductor,
The difference (b) between the crystal growth rate a of the group III nitride compound semiconductor in the at least part of the exposed region of the valley between the projections of the base substrate and the crystal growth rate b at the top of the projection. 2. The method for producing a semiconductor crystal according to claim 1 , wherein -a) is controlled to a substantially maximum value.
前記原料供給量qを1μmol/min以上、100μmol/min以下としたことを特徴とする請求項2または請求項3に記載の半導体結晶の製造方法。4. The method for producing a semiconductor crystal according to claim 2, wherein the raw material supply amount q is 1 μmol / min or more and 100 μmol / min or less. 前記下地基板の材料として、シリコン(Si)または炭化シリコン(SiC)を用いることを特徴とする請求項1乃至請求項4の何れか1項に記載の半導体結晶の製造方法。5. The method of manufacturing a semiconductor crystal according to claim 1 , wherein silicon (Si) or silicon carbide (SiC) is used as a material for the base substrate. 前記下地基板の材料として、Si(111)を用い、
前記突起部形成工程において、前記下地基板の前記突起部間の谷部の露出領域に、Si(111)面が露出しない様に前記突起部を形成することを特徴とする請求項1乃至請求項5の何れか1項に記載の半導体結晶の製造方法。
Si (111) is used as the material of the base substrate,
In the protrusion forming step, the exposed area of the valley between the protrusions of the base substrate, according to claim 1 to claim, characterized in that the Si (111) surface to form the protrusion so as not to expose 6. The method for producing a semiconductor crystal according to any one of 5 above.
前記突起部形成工程後、少なくとも前記突起部の表面に「AlxGa1-xN(0<x≦1)」より成るバッファ層を形成する工程を有することを特徴とする請求項1乃至請求項6の何れか1項に記載の半導体結晶の製造方法。2. The method according to claim 1, further comprising a step of forming a buffer layer made of “Al x Ga 1-x N (0 <x ≦ 1)” on at least a surface of the protruding portion after the protruding portion forming step. 7. The method for producing a semiconductor crystal according to any one of items 6 . 前記バッファ層の膜厚を前記突起部の縦方向の高さ以下に成膜することを特徴とする請求項7に記載の半導体結晶の製造方法。The method of manufacturing a semiconductor crystal according to claim 7 , wherein the buffer layer is formed to have a film thickness equal to or less than a vertical height of the protrusion. 前記結晶成長工程において、前記基板層の膜厚を50μm以上としたことを特徴とする請求項1乃至請求項8の何れか1項に記載の半導体結晶の製造方法。9. The method of manufacturing a semiconductor crystal according to claim 1 , wherein in the crystal growth step, the thickness of the substrate layer is set to 50 μm or more. 前記結晶成長工程において、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することを特徴とする請求項1乃至請求項9の何れか1項に記載の半導体結晶の製造方法。The crystal growth method according to any one of claims 1 to 9, wherein, in the crystal growth step, the crystal growth method is changed in the middle from a crystal growth method having a low crystal growth rate to a crystal growth method having a high crystal growth rate. A method for producing a semiconductor crystal according to Item . 前記突起部形成工程において、前記突起部が略等間隔または略一定周期で配置される様に前記突起部を形成することを特徴とする請求項1乃至請求項10の何れか1項に記載の半導体結晶の製造方法。11. The protrusion according to claim 1 , wherein in the protrusion forming step, the protrusion is formed so that the protrusions are arranged at substantially equal intervals or at a substantially constant period. Manufacturing method of semiconductor crystal. 前記突起部形成工程において、1辺が0.1μm以上の略正三角形を基調とする2次元三角格子の格子点上に前記突起部を形成することを特徴とする請求項11に記載の半導体結晶の製造方法。12. The semiconductor crystal according to claim 11 , wherein, in the projecting portion forming step, the projecting portions are formed on lattice points of a two-dimensional triangular lattice based on a substantially equilateral triangle having a side of 0.1 [mu] m or more. Manufacturing method. 前記突起部形成工程において、前記突起部の水平断面形状を、略正三角形、略正六角形、略円形、又は四角形に形成したことを特徴とする請求項1乃至請求項12の何れか1項に記載の半導体結晶の製造方法。13. The method according to claim 1 , wherein, in the protrusion forming step, a horizontal cross-sectional shape of the protrusion is formed into a substantially regular triangle, a substantially regular hexagon, a substantially circular, or a quadrangle. The manufacturing method of the semiconductor crystal of description. 前記突起部形成工程において、前記突起部の配置間隔を0.1μm以上、10μm以下とすることを特徴とする請求項1乃至請求項13の何れか1項に記載の半導体結晶の製造方法。14. The method of manufacturing a semiconductor crystal according to claim 1 , wherein, in the protrusion forming step, an interval between the protrusions is 0.1 μm or more and 10 μm or less. 前記突起部形成工程において、前記突起部の縦方向の高さを 0.5μm以上、20μm以下とすることを特徴とする請求項1乃至請求項14の何れか1項に記載の半導体結晶の製造方法。The semiconductor crystal manufacturing method according to any one of claims 1 to 14, wherein, in the protruding portion forming step, a vertical height of the protruding portion is set to 0.5 µm or more and 20 µm or less. Method. 前記突起部形成工程において、前記突起部の横方向の太さ、幅、又は直径を0.1μm以上、10μm以下とすることを特徴とする請求項1乃至請求項15の何れか1項に記載の半導体結晶の製造方法。 16. The method according to claim 1 , wherein, in the projecting portion forming step, a lateral thickness, width, or diameter of the projecting portion is set to 0.1 μm or more and 10 μm or less. A method for producing a semiconductor crystal. 前記結晶成長工程よりも前に、
各種エッチング、電子線照射処理、光学的処理、化学的処理、或いは物理的処理により、
前記下地基板の前記突起部間の谷部の少なくとも一部の露出領域の結晶性又は分子構造を劣化又は変化させることにより、前記露出領域における前記III族窒化物系化合物半導体の結晶成長速度aを低下させることを特徴とする請求項1乃至請求項16の何れか1項に記載の半導体結晶の製造方法。
Before the crystal growth step,
Various etching, electron beam irradiation treatment, optical histological processing, chemical treatment, walk by physical treatment,
By reducing or changing the crystallinity or molecular structure of at least a part of the exposed region of the valley between the protrusions of the base substrate, the crystal growth rate a of the group III nitride compound semiconductor in the exposed region is increased. The method for manufacturing a semiconductor crystal according to any one of claims 1 to 16 , wherein the semiconductor crystal is reduced.
前記分離工程において、
前記下地基板と前記基板層とから成る基板を成長装置の反応室に残し、略一定流量のアンモニア(NH3)ガスを前記反応室に流したままの状態で、
前記基板を概ね「−100℃/min〜−0.5℃/min」程度の冷却速度で略常温まで冷却することを特徴とする請求項1又は、請求項3乃至請求項17の何れか1項に記載の半導体結晶の製造方法。
In the separation step,
The substrate composed of the base substrate and the substrate layer is left in the reaction chamber of the growth apparatus, and a substantially constant flow rate of ammonia (NH 3 ) gas is allowed to flow into the reaction chamber.
18. The substrate according to claim 1 or any one of claims 3 to 17, wherein the substrate is cooled to substantially room temperature at a cooling rate of approximately "-100 [deg.] C./min to -0.5 [deg.] C./min". A method for producing a semiconductor crystal according to Item .
少なくとも前記分離工程よりも後に、
前記基板層の裏面に残った前記突起部の破断残骸を化学的或いは物理的な加工処理により除去する残骸除去工程を有する
ことを特徴とする請求項1又は、請求項3乃至請求項18の何れか1項に記載の半導体結晶の製造方法。
At least after the separation step,
Claim 1 or characterized in that it has a debris removing step of removing by the protrusions break debris to-chemical or physical processing of remaining on the back surface of the substrate layer, of claims 3 to 18 The manufacturing method of the semiconductor crystal of any one .
請求項1乃至請求項19の何れか1項に記載の半導体結晶の製造方法を用いて製造された前記半導体結晶を結晶成長基板として、結晶成長により製造することを特徴とするIII族窒化物系化合物半導体発光素子の製造方法21. A group III nitride system produced by crystal growth using the semiconductor crystal produced by the method for producing a semiconductor crystal according to claim 1 as a crystal growth substrate. A method for producing a compound semiconductor light emitting device.
JP2001036604A 2001-02-14 2001-02-14 Manufacturing method of semiconductor crystal and semiconductor light emitting device Expired - Lifetime JP4084541B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2001036604A JP4084541B2 (en) 2001-02-14 2001-02-14 Manufacturing method of semiconductor crystal and semiconductor light emitting device
TW91102216A TW575908B (en) 2001-02-14 2002-02-07 Method for producing semiconductor crystal and semiconductor light-emitting element
DE60233386T DE60233386D1 (en) 2001-02-14 2002-02-12 METHOD FOR PRODUCING SEMICONDUCTOR CRYSTALS AND SEMICONDUCTOR LIGHT ELEMENTS
CNB028046919A CN100414005C (en) 2001-02-14 2002-02-12 Production method for semiconductor crystal and semiconductor luminous element
KR10-2003-7010636A KR20030074824A (en) 2001-02-14 2002-02-12 Production method for semiconductor crystal and semiconductor luminous element
US10/467,566 US7052979B2 (en) 2001-02-14 2002-02-12 Production method for semiconductor crystal and semiconductor luminous element
PCT/JP2002/001159 WO2002064864A1 (en) 2001-02-14 2002-02-12 Production method for semiconductor crystal and semiconductor luminous element
EP02711474A EP1367150B1 (en) 2001-02-14 2002-02-12 Production method for semiconductor crystal and semiconductor luminous element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001036604A JP4084541B2 (en) 2001-02-14 2001-02-14 Manufacturing method of semiconductor crystal and semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JP2002241192A JP2002241192A (en) 2002-08-28
JP4084541B2 true JP4084541B2 (en) 2008-04-30

Family

ID=18899862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001036604A Expired - Lifetime JP4084541B2 (en) 2001-02-14 2001-02-14 Manufacturing method of semiconductor crystal and semiconductor light emitting device

Country Status (3)

Country Link
JP (1) JP4084541B2 (en)
CN (1) CN100414005C (en)
TW (1) TW575908B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216367B2 (en) 2005-06-14 2012-07-10 Showa Denko K.K. Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4201541B2 (en) 2002-07-19 2008-12-24 豊田合成株式会社 Semiconductor crystal manufacturing method and group III nitride compound semiconductor light emitting device manufacturing method
GB0326321D0 (en) * 2003-11-12 2003-12-17 Univ Warwick Formation of lattice-tuning semiconductor substrates
KR100553366B1 (en) 2004-05-14 2006-02-20 엘지전자 주식회사 Method for manufacturing semiconductor device of Nitride chemical
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR100695118B1 (en) * 2005-12-27 2007-03-14 삼성코닝 주식회사 Fabrication method of multi-freestanding gan wafer
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
JP2008053602A (en) * 2006-08-28 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor element, and manufacturing method thereof
WO2008030574A1 (en) 2006-09-07 2008-03-13 Amberwave Systems Corporation Defect reduction using aspect ratio trapping
JP4996186B2 (en) * 2006-09-25 2012-08-08 株式会社東芝 Semiconductor device, compound semiconductor substrate and manufacturing method thereof
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
JP4915282B2 (en) * 2007-05-28 2012-04-11 三菱化学株式会社 Base substrate for group III nitride semiconductor growth and method for growing group III nitride semiconductor
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
DE112008002387B4 (en) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a multijunction solar cell, method of forming a photonic device, photovoltaic multijunction cell and photovoltaic multijunction cell device,
EP2285736A2 (en) * 2008-05-06 2011-02-23 Kyma Technologies, INC. Group iii nitride templates and related heterostructures, devices, and methods for making them
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
CN102160145B (en) 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
JP5426178B2 (en) * 2009-01-13 2014-02-26 日本碍子株式会社 Method for producing group III metal nitride single crystal
KR101064068B1 (en) * 2009-02-25 2011-09-08 엘지이노텍 주식회사 Manufacturing method of light emitting device
CN102379046B (en) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 Devices formed from a non-polar plane of a crystalline material and method of making the same
US8154034B1 (en) * 2010-11-23 2012-04-10 Invenlux Limited Method for fabricating vertical light emitting devices and substrate assembly for the same
TWI458129B (en) * 2010-12-21 2014-10-21 Lextar Electronics Corp Light emitting diode chip structure and fabrication method thereof
TWI446583B (en) * 2011-06-29 2014-07-21 Univ Nat Chiao Tung Method of semiconductor manufacturing process
JP2012006830A (en) * 2011-08-12 2012-01-12 Mitsubishi Chemicals Corp Ground substrate for growing group iii nitride semiconductor, and method for growing group iii nitride semiconductor
CN103165771B (en) * 2013-03-28 2015-07-15 天津三安光电有限公司 Nitride bottom layer with embedded hole structure and preparation method of nitride bottom layer
US9558943B1 (en) * 2015-07-13 2017-01-31 Globalfoundries Inc. Stress relaxed buffer layer on textured silicon surface
CN106816509B (en) * 2017-04-07 2018-12-21 厦门乾照光电股份有限公司 Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit
CN108598237B (en) * 2018-07-12 2023-11-10 广东省半导体产业技术研究院 Semiconductor device and method for manufacturing the same
CN111430220A (en) * 2020-03-26 2020-07-17 江苏南大光电材料股份有限公司 Preparation method of GaN self-supporting substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146457A (en) * 1997-07-03 2000-11-14 Cbl Technologies, Inc. Thermal mismatch compensation to produce free standing substrates by epitaxial deposition
JP3525061B2 (en) * 1998-09-25 2004-05-10 株式会社東芝 Method for manufacturing semiconductor light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216367B2 (en) 2005-06-14 2012-07-10 Showa Denko K.K. Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate

Also Published As

Publication number Publication date
TW575908B (en) 2004-02-11
CN1863944A (en) 2006-11-15
CN100414005C (en) 2008-08-27
JP2002241192A (en) 2002-08-28

Similar Documents

Publication Publication Date Title
JP4084541B2 (en) Manufacturing method of semiconductor crystal and semiconductor light emitting device
US6964705B2 (en) Method for producing semiconductor crystal
EP1367150B1 (en) Production method for semiconductor crystal and semiconductor luminous element
JP4084544B2 (en) Semiconductor substrate and semiconductor device manufacturing method
KR100629558B1 (en) GaN SINGLE CRYSTALLINE SUBSTRATE AND METHOD OF PRODUCING THE SAME
US7163876B2 (en) Method for manufacturing group-III nitride compound semiconductor, and group-III nitride compound semiconductor device
JP5531983B2 (en) Method for manufacturing group III-V nitride semiconductor substrate
JP3589200B2 (en) Nitride semiconductor substrate, method of manufacturing the same, and nitride semiconductor device using the nitride semiconductor substrate
US7615472B2 (en) Method for manufacturing nitride semiconductor substrate
JP2003163370A (en) Method of manufacturing semiconductor crystal
US7011707B2 (en) Production method for semiconductor substrate and semiconductor element
JP4115187B2 (en) Semiconductor crystal manufacturing method and group III nitride compound semiconductor light emitting device
CN1296970C (en) Nitride semiconductor, semiconductor device and mfg. method thereof
JP4749583B2 (en) Manufacturing method of semiconductor substrate
JP2002299253A5 (en)
US8148178B2 (en) Method of growing nitride single crystal and method of manufacturing nitride semiconductor light emitting device
US6946370B2 (en) Semiconductor crystal producing method
JP2003282551A (en) Single-crystal sapphire substrate and its manufacturing method
JP4749584B2 (en) Manufacturing method of semiconductor substrate
JP2002270970A (en) Nitride semiconductor light emitting element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040720

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071120

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080212

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080215

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4084541

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110222

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110222

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120222

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120222

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313532

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130222

Year of fee payment: 5

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140222

Year of fee payment: 6

EXPY Cancellation because of completion of term